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Journal articles on the topic 'Switch Buffering Architectures'

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Author: Grafiati

Published: 10 December 2022

Last updated: 29 January 2023

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Haijun Yang and S. J. B. Yoo. "All-optical variable buffering strategies and switch fabric architectures for future all-optical data routers." Journal of Lightwave Technology 23, no. 10 (October 2005): 3321–30. http://dx.doi.org/10.1109/jlt.2005.856166.

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Badran, Hosein F., and H. T. Mouftah. "ATM switch architectures with input-output-buffering: effect of input traffic correlation, contention resolution policies, buffer allocation strategies and delay in backpressure signal." Computer Networks and ISDN Systems 26, no. 9 (May 1994): 1187–213. http://dx.doi.org/10.1016/0169-7552(94)90018-3.

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Et. al., Vishal Chandra ,. "VLSI Design of A Chip With High Speed Atm Switch-A Review." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (April 10, 2021): 1655–59. http://dx.doi.org/10.17762/turcomat.v12i2.1451.

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In current computer communication network, it is overwhelmed by two technologies, in particular Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Association situated ATM is the awesome constant administrations which require ensured nature of-administration like video conferencing. Be that as it may, connectionless IP is more proficient than ATM for non-ongoing administrations like email. Right now, the significant exploration challenge is on the most proficient method to coordinate ATM and IP into a solitary network effectively. It is shown by the acknowledgment of the highlight of the A/I Net architecture: the A/I Switch. In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. In view of a piece cut architecture, the whole 16x16 switch is acknowledged utilizing four indistinguishable chips. It accomplishes elite by using dispersed control and accelerate with the input-output buffering technique. A need structure, which upholds four-level, permits the postponement delicate ATM cells to be switched with the briefest inertness. It likewise empowers the non-interleaving directing plan of IP cells.

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Reza, Ahmed Galib, and Hyotaek Lim. "Hybrid buffering architecture for packet contention resolution of an optical packet switch." Optik 122, no. 7 (April 2011): 591–93. http://dx.doi.org/10.1016/j.ijleo.2010.04.017.

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Geldenhuys, R., Y. Liu, M. T. Hill, G. D. Khoe, F. W. Leuschner, and H. J. S. Dorren. "Architectures and Buffering for All-Optical Packet-Switched Cross-Connects." Photonic Network Communications 11, no. 1 (January 2006): 65–75. http://dx.doi.org/10.1007/s11107-006-5324-0.

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Yang, Shuna, and Norvald Stol. "A novel delay line buffering architecture for asynchronous optical packet switched networks." International Journal of Information, Communication Technology and Applications 1, no. 1 (March 9, 2015): 69–82. http://dx.doi.org/10.17972/ajicta20151112.

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Optical buffering is one major challenge in realizing all-optical packet switching. In this paper we focus on a delay-line buffer architecture, named a Multiple-Input Single-Output (MISO) optical buffer, which is realized by cascaded fiber delay lines (FDLs). This architecture reduces the physical size of a buffer by up to an order of magnitude or more by allowing reuse of its delay line elements. We consider the MISO buffers in a network scenario where the incoming packets are asynchronous and of fixed length. A novel Markov model is developed to analyze the performance of our buffering scheme, in terms of packet loss ratio, average packet delay and the output link utilization. Both simulation and analytical results show that the length value of basic FDL element will significantly affect the performance of this buffer. This paper gives clear guidelines for designing optimal basic FDL lengths under different network scenarios. It is noticeable that this optimal length value is independent of the buffer sizes for specific traffic load and pattern.

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Li, Lin, Jitender S. Deogun, and Stephen D. Scott. "Performance analysis of optical packet switches with a hybrid buffering architecture [Invited]." Journal of Optical Networking 3, no. 6 (2004): 433. http://dx.doi.org/10.1364/jon.3.000433.

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C.D., Jaidhar, and A. V. Reddy. "Efficient Variable Length Block Switching Mechanism." International Journal of Computers Communications & Control 2, no. 3 (September 1, 2007): 269. http://dx.doi.org/10.15837/ijccc.2007.3.2359.

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Most popular and widely used packet switch architecture is the crossbar. Its attractive characteristics are simplicity, non-blocking and support for simultaneous multiple packet transmission across the switch. The special version of crossbar switch is Combined Input Crossbar Queue (CICQ) switch. It overcomes the limitations of un-buffered crossbar by employing buffers at each crosspoint in addition to buffering at each input port. Adoption of Crosspoint Buffer (CB) simplifies the scheduling complexity and adapts the distributed nature of scheduling. As a result, matching operation is not needed. Moreover, it supports variable length packets transmission without segmentation. Native switching of variable length packet transmission results in unfairness. To overcome this unfairness, Fixed Length Block Transfer mechanism has been proposed. It has the following drawbacks: (a) Fragmented packets are reassembled at the Crosspoint Buffer (CB). Hence, minimum buffer requirement at each crosspoint is twice the maximum size of the block. When number of ports are more, existence of such a switch is infeasible, due to the restricted memory available in switch core. (b) Reassembly circuit at each crosspoint adds the cost of the switch. (c) Packet is eligible to transfer from CB to output only when the entire packet arrives at the CB, which increases the latency of the fragmented packet in the switch. To overcome these drawbacks, this paper presents Variable Length Block Transfer mechanism. It does not require internal speedup, segmentation and reassembly circuits. Using simulation it is shown that proposed mechanism is superior to Fixed Length Block Transfer mechanism in terms of delay and throughput.

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Terzenidis, Nikos, Miltiadis Moralis-Pegios, George Mourgias-Alexandris, Konstantinos Vyrsokinos, and Nikos Pleros. "High-port low-latency optical switch architecture with optical feed-forward buffering for 256-node disaggregated data centers." Optics Express 26, no. 7 (March 26, 2018): 8756. http://dx.doi.org/10.1364/oe.26.008756.

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Wang, Jingyan, Conor McArdle, and Liam P. Barry. "Optical packet switch with energy-efficient hybrid optical/electronic buffering for data center and HPC networks." Photonic Network Communications 32, no. 1 (November 21, 2015): 89–103. http://dx.doi.org/10.1007/s11107-015-0578-z.

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Zheng, Ling, Zhiliang Qiu, Shiyong Sun, Weitao Pan, Ya Gao, and Zhiyi Zhang. "Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers." Journal of Communications and Networks 20, no. 6 (December 2018): 578–92. http://dx.doi.org/10.1109/jcn.2018.000090.

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Keezer, D. C., D. Minier, P. Ducharme, D. Viens, G. Flynn, and J. McKillop. "MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing." VLSI Design 2008 (May 27, 2008): 1–8. http://dx.doi.org/10.1155/2008/291686.

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We describe the use of microelectromechanical system (MEMS) switches and SiGe logic devices for both passive and active loopback testing of wide data buses at rates up to 6.4 Gbps per signal. Target applications include HyperTransport, fully buffered DIMM, and PCI Express, among others. Recently introduced MEMS devices provide >7 GHz bandwidth in a very small package (needed to handle wide buses). SiGe logic supports >7 Gbps signals when active shaping of the waveform is required. Each loopback module typically supports between 9 and 16 differential channels. Multiple cards are used to handle applications with very wide buses or multiple ports. Passive cards utilize MEMS for switching between the loopback (self-test) mode and traditional automated test equipment (ATE) source/receiver channels. Future active card designs may provide additional waveform-shaping functions, such as buffering, amplitude attenuation/modulation, deskew, delay adjustment, jitter injection, and so forth. The modular approach permits precalibration of the loopback electronics and easy reconfiguration between debug or characterization testing and high-volume production screening.

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Papamanolis, Panteleimon, Dominik Bortis, Florian Krismer, David Menzi, and Johann Walter Kolar. "New EV Battery Charger PFC Rectifier Front-End Allowing Full Power Delivery in 3-Phase and 1-Phase Operation." Electronics 10, no. 17 (August 26, 2021): 2069. http://dx.doi.org/10.3390/electronics10172069.

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A new universal front-end PFC rectifier topology of a battery charger for Electric Vehicles (EVs) is proposed, which allows fast charging at rated and/or full power level in case of 3-phase (Europe) as well as 1-phase (USA) mains supply. In this regard, a conventional 3-phase PFC rectifier would facilitate only one-third of the rated power in case of 1-phase operation. The new topology is based on a two-level six-switch (2LB6) 3-phase boost-type PFC rectifier, which is extended with a diode bridge-leg and additional windings of the Common-Mode (CM) chokes of the EMI filter. Besides this extension of the power circuit, the general design of the new converter is explained, and the generated Differential Mode (DM) and Common Mode (CM) EMI disturbances are investigated for 3-phase and 1-phase operation, resulting in guidelines for the EMI filter design. The EMI performance (CISPR 11 class-B QP) is experimentally verified for 1-phase and 3-phase operation at an output power of 4.5 kW, using a full-scale hardware prototype that implements the proposed extensions for a 2LB6 3-phase boost-type PFC rectifier and that is designed for output power levels of 22 kW and 19 kW in case of 3-phase and 1-phase operation, respectively. Compared to a conventional 2LB6 PFC rectifier, the volume of the extended system increases from 2.7 dm3 to 3.4 dm3, of which 0.5 dm3 is due to the additional dc-link capacitance for buffering the power pulsation with twice the mains frequency occurring for 1-phase operation.

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Shukla, Vaibhav, Nikunj Sharma, and Dilip Kumar Choubey. "Performance Evaluation of a Hybrid Buffer-Based Optical Packet Switch Router." Journal of Optical Communications, February 14, 2020. http://dx.doi.org/10.1515/joc-2019-0230.

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AbstractRecently, in the present day’s data center systems an explosive growth has been observed in data traffic, which restricts the speed of exiting data communication network. To solve such problem, fiber optical-based optical communication system is preferred choice. In this paper, an arrayed waveguide grating (AWG)-based optical packet switch is presented in which priority among packets is implemented effectively. This switch is a recirculating loop buffer-based switch in which a hybrid buffering (optical + electrical) technique is used for storing packets into the buffer. The power budget analysis of switch is presented in various conditions, when packet passes through the optical or electronic buffers. Comparison of optical and electronic buffering is done in terms of power required for the correct operation of the switch. In this paper, a comparison is performed between our proposed switch with recently published switch designs. The result presented in this paper clearly reveals that the performance of our proposed switch is far better than other previously published switch architecture. The major beauty of our proposed switch is that in this design priority among packets implemented effectively.

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Meng, Jiacheng, Wei Wang, Ningbo Xie, Duorui Gao, Jiaxuan Zhu, Zhaofeng Bai, and Xiaoping Xie. "160 Gbps capacity and sub-us latency of polarization-independent optical packet switch architecture for free-space optical network using PLZT optical switch." Modern Physics Letters B, November 28, 2022. http://dx.doi.org/10.1142/s0217984922501457.

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In this paper, we discuss the challenges and limitations of current free-space optical (FSO) networks toward scaling beyond the 100 Gbps switch capacity era while achieving low-latency and high-reliability. Owing to the slowdown of Moore’s law, to avoid electronically-induced bottlenecks, we construct an FSO switch network and experimentally evaluate the feasibility of ultrafast optical packet switch architecture based on polarization-independent plomb lanthanum zirconate titanate (PLZT) switch without buffering. The bit error ratio of 160 Gbps ([Formula: see text]) data was validated based on measurements while still preserving the sub-us latency metrics ([Formula: see text] ns). The experimental results may offer a significant reference for FSO communication and network.

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