Relevant bibliographies by topics / Switch Buffering Architectures

Academic literature on the topic 'Switch Buffering Architectures'

Author: Grafiati
Published: 10 December 2022
Last updated: 29 January 2023

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Journal articles on the topic "Switch Buffering Architectures"

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Haijun Yang and S. J. B. Yoo. "All-optical variable buffering strategies and switch fabric architectures for future all-optical data routers." Journal of Lightwave Technology 23, no. 10 (October 2005): 3321–30. http://dx.doi.org/10.1109/jlt.2005.856166.

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Badran, Hosein F., and H. T. Mouftah. "ATM switch architectures with input-output-buffering: effect of input traffic correlation, contention resolution policies, buffer allocation strategies and delay in backpressure signal." Computer Networks and ISDN Systems 26, no. 9 (May 1994): 1187–213. http://dx.doi.org/10.1016/0169-7552(94)90018-3.

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Et. al., Vishal Chandra ,. "VLSI Design of A Chip With High Speed Atm Switch-A Review." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (April 10, 2021): 1655–59. http://dx.doi.org/10.17762/turcomat.v12i2.1451.

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In current computer communication network, it is overwhelmed by two technologies, in particular Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Association situated ATM is the awesome constant administrations which require ensured nature of-administration like video conferencing. Be that as it may, connectionless IP is more proficient than ATM for non-ongoing administrations like email. Right now, the significant exploration challenge is on the most proficient method to coordinate ATM and IP into a solitary network effectively. It is shown by the acknowledgment of the highlight of the A/I Net architecture: the A/I Switch. In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. In view of a piece cut architecture, the whole 16x16 switch is acknowledged utilizing four indistinguishable chips. It accomplishes elite by using dispersed control and accelerate with the input-output buffering technique. A need structure, which upholds four-level, permits the postponement delicate ATM cells to be switched with the briefest inertness. It likewise empowers the non-interleaving directing plan of IP cells.
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Reza, Ahmed Galib, and Hyotaek Lim. "Hybrid buffering architecture for packet contention resolution of an optical packet switch." Optik 122, no. 7 (April 2011): 591–93. http://dx.doi.org/10.1016/j.ijleo.2010.04.017.

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Geldenhuys, R., Y. Liu, M. T. Hill, G. D. Khoe, F. W. Leuschner, and H. J. S. Dorren. "Architectures and Buffering for All-Optical Packet-Switched Cross-Connects." Photonic Network Communications 11, no. 1 (January 2006): 65–75. http://dx.doi.org/10.1007/s11107-006-5324-0.

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Yang, Shuna, and Norvald Stol. "A novel delay line buffering architecture for asynchronous optical packet switched networks." International Journal of Information, Communication Technology and Applications 1, no. 1 (March 9, 2015): 69–82. http://dx.doi.org/10.17972/ajicta20151112.

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Optical buffering is one major challenge in realizing all-optical packet switching. In this paper we focus on a delay-line buffer architecture, named a Multiple-Input Single-Output (MISO) optical buffer, which is realized by cascaded fiber delay lines (FDLs). This architecture reduces the physical size of a buffer by up to an order of magnitude or more by allowing reuse of its delay line elements. We consider the MISO buffers in a network scenario where the incoming packets are asynchronous and of fixed length. A novel Markov model is developed to analyze the performance of our buffering scheme, in terms of packet loss ratio, average packet delay and the output link utilization. Both simulation and analytical results show that the length value of basic FDL element will significantly affect the performance of this buffer. This paper gives clear guidelines for designing optimal basic FDL lengths under different network scenarios. It is noticeable that this optimal length value is independent of the buffer sizes for specific traffic load and pattern.
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Li, Lin, Jitender S. Deogun, and Stephen D. Scott. "Performance analysis of optical packet switches with a hybrid buffering architecture [Invited]." Journal of Optical Networking 3, no. 6 (2004): 433. http://dx.doi.org/10.1364/jon.3.000433.

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C.D., Jaidhar, and A. V. Reddy. "Efficient Variable Length Block Switching Mechanism." International Journal of Computers Communications & Control 2, no. 3 (September 1, 2007): 269. http://dx.doi.org/10.15837/ijccc.2007.3.2359.

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Most popular and widely used packet switch architecture is the crossbar. Its attractive characteristics are simplicity, non-blocking and support for simultaneous multiple packet transmission across the switch. The special version of crossbar switch is Combined Input Crossbar Queue (CICQ) switch. It overcomes the limitations of un-buffered crossbar by employing buffers at each crosspoint in addition to buffering at each input port. Adoption of Crosspoint Buffer (CB) simplifies the scheduling complexity and adapts the distributed nature of scheduling. As a result, matching operation is not needed. Moreover, it supports variable length packets transmission without segmentation. Native switching of variable length packet transmission results in unfairness. To overcome this unfairness, Fixed Length Block Transfer mechanism has been proposed. It has the following drawbacks: (a) Fragmented packets are reassembled at the Crosspoint Buffer (CB). Hence, minimum buffer requirement at each crosspoint is twice the maximum size of the block. When number of ports are more, existence of such a switch is infeasible, due to the restricted memory available in switch core. (b) Reassembly circuit at each crosspoint adds the cost of the switch. (c) Packet is eligible to transfer from CB to output only when the entire packet arrives at the CB, which increases the latency of the fragmented packet in the switch. To overcome these drawbacks, this paper presents Variable Length Block Transfer mechanism. It does not require internal speedup, segmentation and reassembly circuits. Using simulation it is shown that proposed mechanism is superior to Fixed Length Block Transfer mechanism in terms of delay and throughput.
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Terzenidis, Nikos, Miltiadis Moralis-Pegios, George Mourgias-Alexandris, Konstantinos Vyrsokinos, and Nikos Pleros. "High-port low-latency optical switch architecture with optical feed-forward buffering for 256-node disaggregated data centers." Optics Express 26, no. 7 (March 26, 2018): 8756. http://dx.doi.org/10.1364/oe.26.008756.

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Wang, Jingyan, Conor McArdle, and Liam P. Barry. "Optical packet switch with energy-efficient hybrid optical/electronic buffering for data center and HPC networks." Photonic Network Communications 32, no. 1 (November 21, 2015): 89–103. http://dx.doi.org/10.1007/s11107-015-0578-z.

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Dissertations / Theses on the topic "Switch Buffering Architectures"

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Shell, Michael David. "Cascaded All-Optical Shared-Memory Architecture Packet Switches Using Channel Grouping Under Bursty Traffic." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4892.

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This work develops an exact logical operation model to predict the performance of the all-optical shared-memory architecture (OSMA) class of packet switches and provides a means to obtain a reasonable approximation of OSMA switch performance within certain types of networks, including the Banyan family. All-optical packet switches have the potential to far exceed the bandwidth capability of their current electronic counterparts. However, all-optical switching technology is currently not mature. Consequently, all-optical switch fabrics and buffers are more constrained in size and can cost several orders of magnitude more than those of electronic switches. The use of shared-memory buffers and/or links with multiple parallel channels (channel grouping) have been suggested as ways to maximize switch performance with buffers of limited size. However, analysis of shared-memory switches is far more difficult than for other commonly used buffering strategies. Obtaining packet loss performance by simulation is often not a viable alternative to modeling if low loss rates or large networks are encountered. Published models of electronic shared-memory packet switches (ESMP) have primarily involved approximate models to allow analysis of switches with a large number of ports and/or buffer cells. Because most ESMP models become inaccurate for small switches, and OSMA switches, unlike ESMP switches, do not buffer packets unless contention occurs, existing ESMP models cannot be applied to OSMA switches. Previous models of OSMA switches were confined to isolated (non-networked), symmetric OSMA switches using channel grouping under random traffic. This work is far more general in that it also encompasses OSMA switches that (1) are subjected to bursty traffic and/or with input links that have arbitrary occupancy probability distributions, (2) are interconnected to form a network and (3) are asymmetric.
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Conference papers on the topic "Switch Buffering Architectures"

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Li, Lin, Stephen D. Scott, and Jitender S. Deogun. "Performance analysis of WDM optical packet switches with a hybrid buffering architecture." In OptiComm 2003: Optical Networking and Communications, edited by Arun K. Somani and Zhensheng Zhang. SPIE, 2003. http://dx.doi.org/10.1117/12.533538.

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Ji, Wei, Min Zhang, and Peida Ye. "Analysis of optical packet switches with improved performance due to shared buffering and input wavelength-conversion architecture." In Asia-Pacific Optical Communications, edited by S. J. Ben Yoo, Gee-Kung Chang, Guangcheng Li, and Kwok-wai Cheung. SPIE, 2005. http://dx.doi.org/10.1117/12.570555.

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Kehayas, E., L. Stampoulidis, K. Vyrsokinos, D. Apostolopoulos, and H. Avramopoulos. "Architecture, design and physical layer modelling of an all-optical buffering system for all-optical label switched routers." In 2006 International Conference on Photonics in Switching. IEEE, 2006. http://dx.doi.org/10.1109/ps.2006.4350166.

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