Academic literature on the topic 'SW Co-Optimization'
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Journal articles on the topic "SW Co-Optimization":
Yan, Xiaohu, Fazhi He, Neng Hou, and Haojun Ai. "An Efficient Particle Swarm Optimization for Large-Scale Hardware/Software Co-Design System." International Journal of Cooperative Information Systems 27, no. 01 (March 2018): 1741001. http://dx.doi.org/10.1142/s0218843017410015.
WEI, WENLONG, BIN LI, YI ZOU, WENCONG ZHANG, and ZHENQUAN ZHUANG. "A MULTI-OBJECTIVE HW–SW CO-SYNTHESIS ALGORITHM BASED ON QUANTUM-INSPIRED EVOLUTIONARY ALGORITHM." International Journal of Computational Intelligence and Applications 07, no. 02 (June 2008): 129–48. http://dx.doi.org/10.1142/s146902680800220x.
Niu, Wen Liang, Wen Zheng Li, and Kai Shuang Yin. "Application of DFG Model on SOPC Technology." Applied Mechanics and Materials 198-199 (September 2012): 696–700. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.696.
Yanhua Li, Youhui Zhang, and Weiming Zheng. "HW/SW co-optimization for stencil computation: Beginning with a customizable core." Tsinghua Science and Technology 21, no. 5 (October 2016): 570–80. http://dx.doi.org/10.1109/tst.2016.7590326.
Khoud, Khaled Ben, Soufiene Bouallègue, and Mounir Ayadi. "Design and co-simulation of a fuzzy gain-scheduled PID controller based on particle swarm optimization algorithms for a quad tilt wing unmanned aerial vehicle." Transactions of the Institute of Measurement and Control 40, no. 14 (January 8, 2018): 3933–52. http://dx.doi.org/10.1177/0142331217740947.
Zhao, Zhongyuan, Weiguang Sheng, Jinchao Li, Pengfei Ye, Qin Wang, and Zhigang Mao. "Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA." Electronics 10, no. 18 (September 9, 2021): 2210. http://dx.doi.org/10.3390/electronics10182210.
ISSAD, M., B. BOUDRAA, M. ANANE, and N. ANANE. "SOFTWARE/HARDWARE CO-DESIGN OF MODULAR EXPONENTIATION FOR EFFICIENT RSA CRYPTOSYSTEM." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450032. http://dx.doi.org/10.1142/s0218126614500327.
Loupis, Michalis. "Embedded Systems Development Tools: A MODUS-oriented Market Overview." Business Systems Research Journal 5, no. 1 (March 1, 2014): 6–20. http://dx.doi.org/10.2478/bsrj-2014-0001.
Terenchenko, A. S., and A. S. Stryapunin. "Estimation of CO emissions from 2 KAMAZ-54901 truck with the use of Regulation (EU) 2017/2400 methodology." Trudy NAMI, no. 4 (December 28, 2023): 61–68. http://dx.doi.org/10.51187/0135-3152-2023-4-61-68.
Ahmed, M. Elmuzafar, Abdullah S. Sultan, Abdulkarim Al-Sofi, and Hasan S. Al-Hashim. "Optimization of surfactant-polymer flooding for enhanced oil recovery." Journal of Petroleum Exploration and Production Technology, June 15, 2023. http://dx.doi.org/10.1007/s13202-023-01651-0.
Dissertations / Theses on the topic "SW Co-Optimization":
Deb, Abhishek. "HW/SW mechanisms for instruction fusion, issue and commit in modern u-processors." Doctoral thesis, Universitat Politècnica de Catalunya, 2012. http://hdl.handle.net/10803/81561.
En aquesta tesis hem explorat el paradigma de les màquines issue i commit per processadors actuals. Hem implementat una màquina virtual que tradueix binaris x86 a micro-ops de tipus RISC. Aquestes traduccions es guarden com a superblocks, que en realitat no és més que una traça de virtuals co-dissenyades. En particular, hem proposat mecanismes hw/sw per a la fusió d’instruccions, blocs bàsics. Aquests superblocks s’optimitzen utilitzant optimizacions especualtives i d’altres no speculatives. En cas de les optimizations especulatives es consideren mecanismes per a la gestió de errades en l’especulació. Al llarg d’aquesta tesis s’han fet les següents contribucions: Primer, hem proposat una nova unitat functional programmable (PFU) per tal de millorar l’execució d’aplicacions de proposit general. La PFU està formada per un conjunt d’unitats funcionals, similar al CCA, amb un banc de registres intern a la PFU distribuït a les unitats funcionals que la composen. Les entrades de la macro-operació que s’executa en la PFU es mouen del banc de registres físic convencional al intern fent servir un conjunt de moves i loads. Un algorisme de fusió combina més micro-operacions en temps d’execució. Aquest algorisme es basa en un pas de planificació que mesura el benefici de les decisions de fusió. Les micro operacions corresponents a la macro operació s’emmagatzemen com a senyals de control en una configuració. Les macro-operacions tenen associat un identificador de configuració que ajuda a localitzar d’aquestes. Una petita cache de configuracions està present dintre de la PFU per tal de guardar-les. En cas de que la configuració no estigui a la cache, les configuracions es carreguen de la cache d’instruccions. Per altre banda, per tal de donar support al commit atòmic dels superblocks que sobrepassen el tamany del ROB s’ha proposat un mecanisme de commit especulatiu. Per aquest mecanisme hem proposat una taula de mapeig especulativa dels registres, que es copia a la taula no especulativa quan totes les instruccions del superblock han comitejat. Segon, hem proposat un processador en order co-dissenyat que combina dos tipus d’acceleradors. Aquests acceleradors executen un parell d’instruccions fusionades. S’han considerat dos tipus de fusió d’instructions. Primer, combinem un parell de loads independents formant loads vectorials i els executem en una unitat vectorial. Segon, fusionem parells d’instruccions simples d’alu que són dependents i que s’executaran en una Interlock Collapsing ALU (ICALU). Per altra aquestes tecniques les hem evaluat conjuntament amb diverses optimizacions com list scheduling, load-store telescoping i hoisting de loads, entre d’altres. Aquesta proposta ha estat comparada amb un processador fora d’ordre. Tercer, hem proposat un processador fora d’ordre co-dissenyat efficient reduint-ne la complexitat en dos areas principals. En primer lloc, hem co-disenyat el mecanisme de commit per tal de permetre un eficient commit atòmic del superblocks. En aquesta solució hem substituït el ROB convencional, i en lloc hem introduït el Superblock Ordering Buffer (SOB). El SOB manté l’odre de programa a granularitat de superblock. L’estat del programa consisteix en registres i memòria. L’estat dels registres es manté en una taula per superblock, mentre que l’estat de memòria es guarda en un buffer i s’actulitza atòmicament. La segona gran area de reducció de complexitat considerarada és l’ús de FIFOs a la lògica d’issue. En aquest últim àmbit hem proposat una heurística de distribució que solventa les ineficiències de l’heurística basada en dependències anteriorment proposada. Finalment, i junt amb les FIFOs, s’ha proposat un mecanisme per alliberar les entrades de la FIFO anticipadament.
Bouzidi, Halima. "Efficient Deployment of Deep Neural Networks on Hardware Devices for Edge AI." Electronic Thesis or Diss., Valenciennes, Université Polytechnique Hauts-de-France, 2024. http://www.theses.fr/2024UPHF0006.
Neural Networks (NN) have become a leading force in today's digital landscape. Inspired by the human brain, their intricate design allows them to recognize patterns, make informed decisions, and even predict forthcoming scenarios with impressive accuracy. NN are widely deployed in Internet of Things (IoT) systems, further elevating interconnected devices' capabilities by empowering them to learn and auto-adapt in real-time contexts. However, the proliferation of data produced by IoT sensors makes it difficult to send them to a centralized cloud for processing. This is where the allure of edge computing becomes captivating. Processing data closer to where it originates -at the edge- reduces latency, makes real-time decisions with less effort, and efficiently manages network congestion.Integrating NN on edge devices for IoT systems enables more efficient and responsive solutions, ushering in a new age of self-sustaining Edge AI. However, Deploying NN on resource-constrained edge devices presents a myriad of challenges: (i) The inherent complexity of neural network architectures, which requires significant computational and memory capabilities. (ii) The limited power budget of IoT devices makes the NN inference prone to rapid energy depletion, drastically reducing system utility. (iii) The hurdle of ensuring harmony between NN and HW designs as they evolve at different rates. (iv) The lack of adaptability to the dynamic runtime environment and the intricacies of input data.Addressing these challenges, this thesis aims to establish innovative methods that extend conventional NN design frameworks, notably Neural Architecture Search (NAS). By integrating HW and runtime contextual features, our methods aspire to enhance NN performances while abstracting the need for the human-in-loop}. Firstly, we incorporate HW properties into the NAS by tailoring the design of NN to clock frequency variations (DVFS) to minimize energy footprint. Secondly, we leverage dynamicity within NN from a design perspective, culminating in a comprehensive Hardware-aware Dynamic NAS with DVFS features. Thirdly, we explore the potential of Graph Neural Networks (GNN) at the edge by developing a novel HW-aware NAS with distributed computing features on heterogeneous MPSoC. Fourthly, we address the SW/HW co-optimization on heterogeneous MPSoCs by proposing an innovative scheduling strategy that leverages NN adaptability and parallelism across computing units. Fifthly, we explore the prospect of ML4ML -- Machine Learning for Machine Learning by introducing techniques to estimate NN performances on edge devices using neural architectural features and ML-based predictors. Finally, we develop an end-to-end self-adaptive evolutionary HW-aware NAS framework that progressively learns the importance of NN parameters to guide the search process toward Pareto optimality effectively.Our methods can contribute to elaborating an end-to-end design framework for neural networks on edge hardware devices. They enable leveraging multiple optimization opportunities at both the software and hardware levels, thus improving the performance and efficiency of Edge AI
Ming-ChungLi and 李明峻. "Hw/Sw Data Transfer Optimization Co-Design of Embedded JPEG Image Compress." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/12464595123506991299.
Book chapters on the topic "SW Co-Optimization":
Mohamed, Khaled Salah. "HW/SW Co-Optimization and Co-Protection." In Synthesis Lectures on Digital Circuits & Systems, 153–70. Cham: Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-56152-8_6.
Salhi, Afef, Fahmi Ghozzi, and Ahmed Fakhfakh. "Approximation Algorithm for Scheduling a Chain of Tasks for Motion Estimation on Heterogeneous Systems MPSoC." In Engineering Problems - Uncertainties, Constraints and Optimization Techniques [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.97676.
Conference papers on the topic "SW Co-Optimization":
Nezhadi, Ali, Shaahin Angizi, and Arman Roohi. "EaseMiss: HW/SW Co-Optimization for Efficient Large Matrix-Matrix Multiply Operations." In 2022 IEEE 15th Dallas Circuit And System Conference (DCAS). IEEE, 2022. http://dx.doi.org/10.1109/dcas53974.2022.9845629.
Xu, Susan, and Hugh Pollitt-Smith. "Optimization of HW/SW Co-Design: Relevance to Configurable Processor and FPGA Technology." In 2007 Canadian Conference on Electrical and Computer Engineering. IEEE, 2007. http://dx.doi.org/10.1109/ccece.2007.423.
Matsuoka, Yusuke, Patrick Schaumont, Kris Tiri, and Ingrid Verbauwhede. "Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques." In the 2004 international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1023833.1023874.
Branković, Aleksandar, Kyriakos Stavrou, Enric Gibert, and Antonio González. "Warm-Up Simulation Methodology for HW/SW Co-Designed Processors." In CGO '14: 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization. New York, NY, USA: ACM, 2014. http://dx.doi.org/10.1145/2544137.2544142.
Wu, Youfeng, Shiliang Hu, Edson Borin, and Cheng Wang. "A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing." In 2011 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO). IEEE, 2011. http://dx.doi.org/10.1109/cgo.2011.5764691.
Corsetto, Nicola, and Francesco Fittipaldi. "Five senses: integrated ergonomic/stylistic design for aircraft interiors." In 15th International Conference on Applied Human Factors and Ergonomics (AHFE 2024). AHFE International, 2024. http://dx.doi.org/10.54941/ahfe1004822.