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Journal articles on the topic 'SUBMICRON TECHNOLOGIES'

Author: Grafiati

Published: 11 September 2023

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1

Claeys, Cor, Jan Vanhellemont, and Eddy Simoen. "Defect Engineering in Submicron CMOS Technologies." Solid State Phenomena 19-20 (January 1991): 95–108. http://dx.doi.org/10.4028/www.scientific.net/ssp.19-20.95.

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2

Gal, Laszlo, C. Prunty, and R. Kumar. "Comparative study of submicron BiCMOS technologies." Microelectronics Journal 23, no. 1 (March 1992): 59–74. http://dx.doi.org/10.1016/0026-2692(92)90097-k.

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3

Zhu, Tao, Hai Rong Li, Yan Dong Wan, Sha Chen, and Hai Bing Liu. "Recognizability and Controlling Technology of Submicron Particles." Applied Mechanics and Materials 182-183 (June 2012): 369–73. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.369.

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In view of the toxicology and hazardous nature of the submicron particles, it is paid more and more attentions of the domestic and foreign research scholars. In this paper, we introduce the research progress on recognition, attributed and formation mechanism of submicron particles in the world. Simultaneously, the controlling technologies of submicron particles are discussed. The application tendency and the existence problems of the controlling technologies are analyzed. At last, the future research directions are put forward for submicron particles control.

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4

Liu, Xiaoxiao, Guangsheng Ma, Jingbo Shao, Zhi Yang, and Guanjun Wang. "Interconnect crosstalk noise evaluation in deep-submicron technologies." Microelectronics Reliability 49, no. 2 (February 2009): 170–77. http://dx.doi.org/10.1016/j.microrel.2008.11.013.

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5

Jarron, P., G. Anelli, T. Calin, J. Cosculluela, M. Campbell, M. Delmastro, F. Faccio, et al. "Deep submicron CMOS technologies for the LHC experiments." Nuclear Physics B - Proceedings Supplements 78, no. 1-3 (August 1999): 625–34. http://dx.doi.org/10.1016/s0920-5632(99)00615-5.

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6

Chong, Y. F., K. L. Pey, A. T. S. Wee, A. See, Z. X. Shen, C. H. Tung, R. Gopalakrishnan, and Y. F. Lu. "Laser-induced titanium disilicide formation for submicron technologies." Journal of Electronic Materials 30, no. 12 (December 2001): 1549–53. http://dx.doi.org/10.1007/s11664-001-0172-2.

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7

Achkasov, A., Maksim Solodilov, Nikolay Litvinov, Pavel Chubunov, V. Zolnikov, Dmitriy Shehovcov, and Oleg Bordyuzha. "Features of the design of microcircuits made using deep-submicron technologies." Modeling of systems and processes 15, no. 4 (December 13, 2022): 7–17. http://dx.doi.org/10.12737/2219-0767-2022-15-4-7-17.

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Noise and signal integrity are important factors influencing the design process of microcircuits made using submicron technology. Currently, there is some difference in what design engineers can design and what can be manufactured with the right level of quality and reliability. Therefore, it is necessary to create a fundamentally new methodology for verifying VLSI projects with deep submicron design standards. In order to calculate the percentage of good chips manufactured, it is required to identify vulnerable effects and phenomena from the point of view of submicron technology. In this paper, the effect of noise on various types of microcircuits is studied and recommendations are given for limiting noise. One of the options for achieving the optimal balance between noise, noise immunity and microcircuit parameters is to add margins when calculating the VLSI parameters. The paper shows that VLSI projects with nanometer topological norms must undergo an additional process of verifying the parameters and functioning in general before issuing information for the production of photomasks. Verification requires the use of an integrated set of software tools that are certified in real production conditions.

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8

Schwalke, U., M. Kerber, K. Koller, and H. J. Jacobs. "EXTIGATE: The ultimate process architecture for submicron CMOS technologies." IEEE Transactions on Electron Devices 44, no. 11 (1997): 2070–77. http://dx.doi.org/10.1109/16.641386.

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9

Nikolaidis, T., and C. Papadas. "ESD production for deep submicron triple well CMOS technologies." Electronics Letters 35, no. 23 (1999): 2025. http://dx.doi.org/10.1049/el:19991393.

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10

Чубур, K. Chubur, Яньков, A. Yankov, Зольников, Konstantin Zolnikov, Ачкасов, and A. Achkasov. "ALGORITHMIC BASIS OF MODELING FAILURES IN DEEP-SUBMICRON TECHNOLOGIES." Modeling of systems and processes 8, no. 1 (July 2, 2015): 15–17. http://dx.doi.org/10.12737/12014.

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An algorithm for evaluation of resistance to single chip events. Calculate the spatial and temporal distribution of the effect of the particles on the chip. The result is a map of VLSI failure as a temporary sequence

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11

Shields, Christopher. "Submicron Filtration Media." International Nonwovens Journal os-14, no. 3 (September 2005): 1558925005os—14. http://dx.doi.org/10.1177/1558925005os-1400305.

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Biopharmaceutical processes, membrane pretreatment, water purification and food and beverage applications all require fine filtration. There are many different types of filter media that can be used for these applications. The types of media vary by materials of construction, processing method and performance characteristics. Each process produces a media with unique properties that have advantages in different applications. These industries have traditionally relied on membranes for their submicron filtration needs. Nonwoven media have not been successful in finer filtration applications due to the relatively large fibers that are produced or the technical and/or operational difficulties in producing fine fiber media. A significant amount of research has been expended over the last few years on developing high efficiency wetlaid media and producing fine diameter synthetic fibers in drylaid operations. Nonwoven media have begun to compete with membranes and other separation technologies in these fine filtration applications. High efficiency nonwoven media composites have equivalent efficiency as many types of membranes but with significantly higher dirt holding capacity or life. This paper will discuss the different types of wetlaid, drylaid and membrane media available for submicron filtration and compare their methods of construction, performance and cost.

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12

Claeys, C., J. Vanhellemont, T. Cavioni, and F. Gualandris. "Structural and Electrical Characterization of SWAMI Techniques for Submicron Technologies." Journal of The Electrochemical Society 136, no. 9 (September 1, 1989): 2619–24. http://dx.doi.org/10.1149/1.2097519.

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13

Yao, Chunhua, Kewal K. Saluja, and Parameswaran Ramanathan. "Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 2 (February 2011): 317–22. http://dx.doi.org/10.1109/tcad.2010.2079350.

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14

Mogul, H. C., T. A. Rost, and Der-Gao Lin. "Advantages of LDD-only implanted fluorine with submicron CMOS technologies." IEEE Transactions on Electron Devices 44, no. 3 (March 1997): 388–94. http://dx.doi.org/10.1109/16.556148.

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15

Ponomarev, Y. V., P. A. Stolk, C. Salm, J. Schmitz, and P. H. Woerlee. "High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates." IEEE Transactions on Electron Devices 47, no. 4 (April 2000): 848–55. http://dx.doi.org/10.1109/16.831003.

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16

Manghisoni, M., L. Ratti, V. Re, and V. Speziali. "Submicron CMOS technologies for low-noise analog front-end circuits." IEEE Transactions on Nuclear Science 49, no. 4 (August 2002): 1783–90. http://dx.doi.org/10.1109/tns.2002.801540.

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17

Deleonibus, S., P. Molle, L. Tosti, and M. C. Taccusel. "Sealing Silicon Nitride Removal in SILO Field Isolation for Submicron Technologies." Journal of The Electrochemical Society 138, no. 12 (December 1, 1991): 3739–42. http://dx.doi.org/10.1149/1.2085491.

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18

Priya, M. Geetha, K. Baskaran, and D. Krishnaveni. "Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications." Procedia Engineering 30 (2012): 1163–70. http://dx.doi.org/10.1016/j.proeng.2012.01.976.

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19

Hansen, D. L. "Proton Cross-Sections from Heavy-Ion Data in Deep-Submicron Technologies." IEEE Transactions on Nuclear Science 62, no. 6 (December 2015): 2874–80. http://dx.doi.org/10.1109/tns.2015.2482360.

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20

Vincent, E., S. Bruyere, C. Papadas, and P. Mortini. "Dielectric reliability in deep-submicron technologies: From thin to ultrathin oxides." Microelectronics Reliability 37, no. 10-11 (October 1997): 1499–506. http://dx.doi.org/10.1016/s0026-2714(97)00095-4.

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21

Kobeda, E., J. D. Warnock, J. P. Gambino, S. B. Brodsky, B. Cunningham, and S. Basavaiah. "Diffusion barrier properties of TiN films for submicron silicon bipolar technologies." Journal of Applied Physics 72, no. 7 (October 1992): 2743–48. http://dx.doi.org/10.1063/1.351525.

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22

Deura, Manabu, Yasuo Nara, Tatsuya Yamazaki, Kenichi Gotoh, Fumio Ohtake, Hajime Kurata, and Toshihiro Sugii. "Deep-submicron CMOS technologies for low-power and high-performance operation." Electronics and Communications in Japan (Part II: Electronics) 79, no. 11 (1996): 1–9. http://dx.doi.org/10.1002/ecjb.4420791101.

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23

NGAN, A. H. W., P. C. WO, L. ZUO, H. LI, and N. AFRIN. "THE STRENGTH OF SUBMICRON-SIZED MATERIALS." International Journal of Modern Physics B 20, no. 25n27 (October 30, 2006): 3579–86. http://dx.doi.org/10.1142/s0217979206040027.

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Recent rapid advancements in nano- and micro-machinery technologies call for an urgent need to understand the mechanical behaviour of materials of dimensions in the sub-micron regime. The initial yield strength of submicron crystals exhibits remarkable statistical scatter as well as dependence upon size and time under load. Submicron-sized materials are also found to creep many orders of magnitude faster than bulk counterparts. In this paper, the recent experimental evidence for these phenomena is reviewed. Theoretical explanation of these phenomena is also discussed. The statistical scatter and time dependence of the yield strength are interpreted by a scaling model derived from atomistic simulations. The results indicate that, within a certain load range, the strength of a sub-micron sized material is not deterministic and can only be described by a survival probability. The much faster creep in the submicron regime is interpreted in terms of the much shorter diffusion length compared to bulk creep.

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24

Liu, Xiao Xiao, Jing Bo Shao, and Ling Ling Zhao. "An Efficient Methodology for Estimating Interconnect Crosstalk Noise in Deep-Submicron Technologies." Advanced Materials Research 989-994 (July 2014): 2647–50. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.2647.

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To solve the crosstalk noise question in deep-submicron technologies, an efficient methodology for estimating interconnect crosstalk noise is proposed in this paper. PCA and ICA techniques are applied to reduce correlations of process variations, and moment matching scheme is used to obtain the PDF of crosstalk noise in victim coupled with multiple aggressors. Experimental results show that our method maintains the efficiency of past approaches, and significantly improves on their accuracy.

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25

Ачкасов, A. Achkasov, Яньков, A. Yankov, Зольников, Konstantin Zolnikov, Чубур, and K. Chubur. "THE ALGORITHMIC BASIS OF MODELLING OF FAILURES FROM EXPOSURE TO HEAVY CHARGED PARTICLES IN VLSI, MADE BY DEEP-SUBMICRON TECHNOLOGIES." Modeling of systems and processes 8, no. 3 (January 11, 2016): 36–38. http://dx.doi.org/10.12737/17166.

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In the article the questions of modeling of failures of all types from exposure to heavy charged particles in semiconductor structures for integrated circuits, made by deep-submicron technologies. Based on the simulation estimates of the dependence of failure section from the amount of energy of the particles.

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26

Kalra, Shruti. "On the mathematical insight of moderate inversion for ultradeep submicron CMOS technologies." Journal of Computational Electronics 17, no. 1 (November 16, 2017): 205–10. http://dx.doi.org/10.1007/s10825-017-1109-1.

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27

Simoen, E., and C. Claeys. "Reliability aspects of the low-frequency noise behaviour of submicron CMOS technologies." Semiconductor Science and Technology 14, no. 8 (January 1, 1999): R61—R71. http://dx.doi.org/10.1088/0268-1242/14/8/201.

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28

Claeys, Cor, Geert Eneman, Mireia Bargallo Gonzalez, Sofie Put, and Eddy Simoen. "Electrical Performance and Reliability Aspects of Strain Engineered Deep Submicron CMOS Technologies." ECS Transactions 8, no. 1 (December 19, 2019): 15–22. http://dx.doi.org/10.1149/1.2767280.

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29

Kim, Jisu, Kyungho Ryu, Jung Pill Kim, Seung H. Kang, and Seong-Ook Jung. "STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 7 (July 2014): 1630–34. http://dx.doi.org/10.1109/tvlsi.2013.2272587.

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30

Endzhievskaya, I. G., A. V. Demina, and M. A. Galkin. "Industrial waste-based submicron additives in cement mortars." Vestnik Tomskogo gosudarstvennogo arkhitekturno-stroitel'nogo universiteta. JOURNAL of Construction and Architecture 24, no. 3 (June 26, 2022): 114–27. http://dx.doi.org/10.31675/1607-1859-2022-24-3-114-127.

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Purpose: The aim of this work is the development of materials and technologies, which provide their repeated life cycle. Methodology/approach: Scanning electron microscopy, thermogravimetric analysis, X-ray diffraction analysis. Research findings: The processing method is proposed for fluorocarbon-containing waste (RUSAL, Krasnoyarsk) resulting in the formation of submicron-sized carbon in the form of a coal-water slurry for solution and/or concrete modification. It is shown that carbon in the coal-water slurry represents flat plates with the submicron-sized particles. The degree of cement hydration increases with the addition of wastes, indicating the material strengthening, which is consistent with the results of strength tests. The acicular spike crystals of hydrated calcium silicates become larger and thicker, that confirms the assumption that hydration increases with the addition of submicron-sized carbon particles. Practical implications: The obtained physical and mechanical properties of the cement-sand mortar show the possibility of using the proposed modifiers in the production of materials with high bending strength at early stages to reduce cracking, especially in thin concrete layers with a large coverage area.

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31

Staman, J. W., R. L. Hodges, G. A. Dixit, F. R. Bryant, R. Sundaresan, C. C. Wei, and F. T. Liou. "Characterization of defects resulting from the poly-buffered local oxidation isolation process." Proceedings, annual meeting, Electron Microscopy Society of America 50, no. 2 (August 1992): 1392–93. http://dx.doi.org/10.1017/s0424820100131590.

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As device dimensions are being scaled down in today's advanced VLSI circuits, isolation has been one of the key technologies to achieve the submicron geometries. The conventional local oxidation (LOCOS) process results in a large bird's beak, rendering it ineffective for submicron technology. Poly buffered local oxidation (PBL) is a manufacturable process and can achieve a smaller bird's beak which makes it attractive for submicron device isolation. In PBL, a thin layer of poly silicon is sandwiched between the protective nitride and oxide. The polysilicon layer acts as a buffer to the nitride and oxidation induced stresses on the silicon substrate and thus a thicker nitride can be used to obtain a shorter bird's beak. Many papers have been published which describe the PBL process, however, very few of them have explored the physical and chemical nature of the defects associated with the PBL process. In this paper, we report the results of transmission electron microscopy (TEM) and electron energy loss spectroscopy (EELS) analysis of these defects and relate them to the traditional Kooi effect.

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32

Schmitz, A., and R. Tielert. "A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies." Advances in Radio Science 3 (May 13, 2005): 355–58. http://dx.doi.org/10.5194/ars-3-355-2005.

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Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

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33

Claeys, Cor, Sofie Put, Alessio Griffoni, Andrea Cester, Simone Gerardin, G. Meneghesso, Alessandro Paccagnella, and Eddy Simoen. "Impact of Radiation on the Operation and Reliability of Deep Submicron CMOS Technologies." ECS Transactions 27, no. 1 (December 17, 2019): 39–46. http://dx.doi.org/10.1149/1.3360593.

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34

Kleczek, R., and P. Kmon. "Comparative analysis of the readout front-end electronics implemented in deep submicron technologies." Journal of Instrumentation 13, no. 11 (November 5, 2018): C11002. http://dx.doi.org/10.1088/1748-0221/13/11/c11002.

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35

La Rosa, Giuseppe, and Stewart E. Rauch. "Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies." Microelectronics Reliability 47, no. 4-5 (April 2007): 552–58. http://dx.doi.org/10.1016/j.microrel.2007.01.031.

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36

Ekekwe, Ndubuisi, and Ralph Etienne-Cummings. "Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies." Microelectronics Journal 37, no. 9 (September 2006): 851–60. http://dx.doi.org/10.1016/j.mejo.2006.03.008.

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37

Ismail, Ayman, and Mohamed Elmasry. "Analysis of the Flash ADC Bandwidth–Accuracy Tradeoff in Deep-Submicron CMOS Technologies." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 10 (October 2008): 1001–5. http://dx.doi.org/10.1109/tcsii.2008.2001979.

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38

Amerasekera, Ajith, and Amitava Chatterjee. "An investigation of BiCMOS ESD protection circuit elements and applications in submicron technologies." Journal of Electrostatics 31, no. 2-3 (December 1993): 145–60. http://dx.doi.org/10.1016/0304-3886(93)90006-s.

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39

Agrawal, Pankaj, and Nikhil Saxena. "Leakage current analysis for stack based Nano CMOS Digital Circuits." International Journal of Electrical and Electronics Research 2, no. 2 (June 30, 2014): 5–11. http://dx.doi.org/10.37391/ijeer.020202.

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Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.

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40

Lee, Jin Woo. "3D Nanoprinting Technologies for Tissue Engineering Applications." Journal of Nanomaterials 2015 (2015): 1–14. http://dx.doi.org/10.1155/2015/213521.

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Tissue engineering recovers an original function of tissue by replacing the damaged part with a new tissue or organ regenerated using various engineering technologies. This technology uses a scaffold to support three-dimensional (3D) tissue formation. Conventional scaffold fabrication methods do not control the architecture, pore shape, porosity, or interconnectivity of the scaffold, so it has limited ability to stimulate cell growth and to generate new tissue. 3D printing technologies may overcome these disadvantages of traditional fabrication methods. These technologies use computers to assist in design and fabrication, so the 3D scaffolds can be fabricated as designed and standardized. Particularly, because nanofabrication technology based on two-photon absorption (2PA) and on controlled electrospinning can generate structures with submicron resolution, these methods have been evaluated in various areas of tissue engineering. Recent combinations of 3D nanoprinting technologies with methods from molecular biology and cell dynamics have suggested new possibilities for improved tissue regeneration. If the interaction between cells and scaffold system with biomolecules can be understood and controlled and if an optimal 3D environment for tissue regeneration can be realized, 3D nanoprinting will become an important tool in tissue engineering.

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41

Viswadha, Singathala Guru. "Next Generation Computing Using Quantum Dot Cellular Automata Nano Technology, New Promising Alternative to CMOS." Asian Journal of Computer Science and Technology 8, S3 (June 5, 2019): 19–24. http://dx.doi.org/10.51983/ajcst-2019.8.s3.2111.

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CMOS technology is one of the most popular technology in the computer chip design industry and broadly used today to form integrated circuits in numerous and varied applications and it has transformed the field of electronics. Over the time the design methodologies and processing technologies of CMOS devices have greatest activity with the Moore’s law. Now CMOS technology has to face challenges to survive through the submicron ranges. The scaling in CMOS has reached higher limit, not only from technological and Physical point of view but also from economical and material aspects. This concept inspires the researches to look for new alternatives to CMOS which gives better performance and power consumption. One of the alternative technologies to digital designing in CMOS is the Quantum dot Cellular Automata (QCA). QCA is a technology it works on Electronic interaction between the cells. The QCA cell basically consists of Quantum dots separated by certain distance. The transmission of information done via the interaction between the Electrons present in these quantum dots. In this paper the limitations to CMOS in submicron range and concepts for designing in QCA have been discussed and also the building blocks are explained using QCA designer implementations with focus on cell interaction and clocking mechanism.

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42

Wirth, Gilson. "Bulk built in current sensors for single event transient detection in deep-submicron technologies." Microelectronics Reliability 48, no. 5 (May 2008): 710–15. http://dx.doi.org/10.1016/j.microrel.2008.01.002.

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43

Hu Zhi-Yuan, Liu Zhang-Li, Shao Hua, Zhang Zheng-Xuan, Ning Bing-Xu, Bi Da-Wei, Chen Ming, and Zou Shi-Chang. "The influence of channel length on total ionizing dose effect in deep submicron technologies." Acta Physica Sinica 61, no. 5 (2012): 050702. http://dx.doi.org/10.7498/aps.61.050702.

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44

Fazeli, M., S. G. Miremadi, A. Ejlali, and A. Patooghy. "Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies." IET Computers & Digital Techniques 3, no. 3 (2009): 289. http://dx.doi.org/10.1049/iet-cdt.2008.0099.

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45

Jenkins, K. A., J. N. Burghartz, and P. D. Agnello. "Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance." IEEE Transactions on Electron Devices 43, no. 5 (May 1996): 759–65. http://dx.doi.org/10.1109/16.491253.

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46

Sallagoity, P., M. Ada-Hanifi, M. Paoli, and M. Haond. "Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies." IEEE Transactions on Electron Devices 43, no. 11 (1996): 1900–1906. http://dx.doi.org/10.1109/16.543025.

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47

Leonenko, Nina. "Integration of fiber lasers in processes of mineral raw material processing." E3S Web of Conferences 56 (2018): 03020. http://dx.doi.org/10.1051/e3sconf/20185603020.

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The application of laser technologies (LT) in the economy of the most developed countries. The possibility of using laser technologies for processing technogenic mineral raw materials is considered. The possibilities of integration of fiber-optic lasers into the processes of enrichment and processing of mineral raw materials are explored. The effects of interaction of laser radiation with mineral media - objects of Amur placer technogenic deposits containing submicron gold not extracted by modern gravitational methods are analyzed. The formation of selforganizing gold structures on the surface of a silicate matrix was established, general patterns of agglomeration and concentration of “nonextractable forms” of gold were revealed.

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48

Lukyanenko, A. V., and T. E. Smolyarova. "Alternative technology for creating nanostructures using Dip Pen Nanolithography." Физика и техника полупроводников 52, no. 5 (2018): 519. http://dx.doi.org/10.21883/ftp.2018.05.45863.52.

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AbstractFor modern microelectronics, at the present time, the technologies of consciousness smart structures play an important role, which can provide accuracy, stability and high quality of the structures. Submicron lithography methods are quite expensive and have natural size limitations, not allowing the production of structures with an extremely small lateral limitation. Therefore, an intensive search was conducted for alternative methods for creating submicron resolution structures. Especially attractive one is the possibility of self-organization effects utilization, where the nanostructure of a certain size is formed under the influence of internal forces. The dip pen nanolithography method based on a scanning probe microscope uses a directwrite technology and allows one to carry out a playback of small size structures with high accuracy. In the experiment, a substrate coated with Au (15 nm) using a DPN technique is applied to the polymer to form a desired pattern nano-sized channel. The experiment was conducted using a pointed probe SiN, coated MHA-Acetonitrile, on the Si(111)/Fe_3Si/Au structure.

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Liu, Xiao Xiao, Jing Bo Shao, and Ling Ling Zhao. "A New Spatial Correlation Model Based on the Distributed RC-_∏ Model." Advanced Materials Research 989-994 (July 2014): 2204–7. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.2204.

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To solve the crosstalk noise question in deep-submicron technologies, a new spatial correlation model based on the distributed RC-π model is proposed in this paper. Quiet aggressor net and tree branch reduction techniques are introduced to the distributed RC-π model, and a new spatial correlation model of both Gaussian and non-Gaussian process variations among segments is created. Experimental results show that our method maintains the efficiency of past approaches, and significantly improves on their accuracy.

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Boyes, E. D. "LVEDS For Advanced Materials and Semiconductor Technologies." Microscopy and Microanalysis 5, S2 (August 1999): 314–15. http://dx.doi.org/10.1017/s1431927600014896.

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The need to analyze bulk samples containing features with submicron dimensions has driven revaluation of the processes controlling the interaction of electron beams with inorganic, polymer and semiconductor materials, and to development of LVEDS analysis at lower beam energies of E0 <5kV (1,2).It has previously been shown (1,2) that the physics is much as expected with the vertical penetration range (R) along the beam direction in many cases predicted quite accurately for beam energy E0 by the simple Bethe (e.g. in 3) power law with R = F(E0)5/3. These same factors are effective to varying degrees in all three dimensions. The strong dependence of the range on energy has practical importance for the identification of sub-micron particles, including to help to determine the root cause of a defect Fig. 1 is an example of the sequential analysis of the exact same sub-micron particle, with the very real potential for a processing disaster, on the surface of a silicon wafer. When this feature is analyzed with a 3kV electron beam we learn it is alumina (A12O3). The analysis comes only from the target particle and the data have a simple relationship to the chemistry and the sensitivity for the light element (O) is excellent, providing simple and direct qualitative identification of the oxide compound.

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