Log in

Relevant bibliographies by topics / SUB MICRON TECHNOLOGIES / Journal articles

To see the other types of publications on this topic, follow the link: SUB MICRON TECHNOLOGIES.

Journal articles on the topic 'SUB MICRON TECHNOLOGIES'

Author: Grafiati

Published: 11 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'SUB MICRON TECHNOLOGIES.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

DESPOTULI, ALEXANDER, and ALEXANDRA ANDREEVA. "A SHORT REVIEW ON DEEP-SUB-VOLTAGE NANOELECTRONICS AND RELATED TECHNOLOGIES." International Journal of Nanoscience 08, no. 04n05 (August 2009): 389–402. http://dx.doi.org/10.1142/s0219581x09006328.

Full text

Abstract:

The decrease of energy consumption per 1 bit processing (ε) and power supply voltage (V dd ) of integrated circuits (ICs) are long-term tendencies in micro- and nanoelectronics. In this framework, deep-sub-voltage nanoelectronics (DSVN), i.e., ICs of ~1011–1012 cm-2 component densities operating near the theoretical limit of ε, is sure to find application in the next 10 years. In nanoelectronics, the demand on high-capacity capacitors of micron sizes sharply increases with a decrease of technological norms, ε and V dd . Creation of high-capacity capacitors of micron size to meet the challenge of DSVN and related technologies is considered. The necessity of developing all-solid-state impulse micron-sized supercapacitors on the basis of advanced superionic conductors (nanoionic supercapacitors) is discussed. Theoretical estimates and experimental data on prototype nanoionic supercapacitors with capacity density δC ≈ 100 μF/cm2 are presented. Future perspectives of nanoionic devices are briefly discussed.

APA, Harvard, Vancouver, ISO, and other styles

2

Yamazaki, T., K. Imai, H. Yoshida, Y. Kinoshita, and H. Suzuki. "Process integration technologies for sub-half micron BiCMOS LSls." Electrical Engineering 79, no. 5 (October 1996): 329–33. http://dx.doi.org/10.1007/bf01235873.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Bude, J. D., and M. Mastrapasqua. "Impact ionization and distribution functions in sub-micron nMOSFET technologies." IEEE Electron Device Letters 16, no. 10 (October 1995): 439–41. http://dx.doi.org/10.1109/55.464810.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Manolopoulos, Spyros, K. Mathieson, and R. Turchetta. "Simulation of monolithic active pixels in deep sub-micron technologies." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 487, no. 1-2 (July 2002): 181–87. http://dx.doi.org/10.1016/s0168-9002(02)00963-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Boyes, E. D. "LVEDS For Advanced Materials and Semiconductor Technologies." Microscopy and Microanalysis 5, S2 (August 1999): 314–15. http://dx.doi.org/10.1017/s1431927600014896.

Full text

Abstract:

The need to analyze bulk samples containing features with submicron dimensions has driven revaluation of the processes controlling the interaction of electron beams with inorganic, polymer and semiconductor materials, and to development of LVEDS analysis at lower beam energies of E0 <5kV (1,2).It has previously been shown (1,2) that the physics is much as expected with the vertical penetration range (R) along the beam direction in many cases predicted quite accurately for beam energy E0 by the simple Bethe (e.g. in 3) power law with R = F(E0)5/3. These same factors are effective to varying degrees in all three dimensions. The strong dependence of the range on energy has practical importance for the identification of sub-micron particles, including to help to determine the root cause of a defect Fig. 1 is an example of the sequential analysis of the exact same sub-micron particle, with the very real potential for a processing disaster, on the surface of a silicon wafer. When this feature is analyzed with a 3kV electron beam we learn it is alumina (A12O3). The analysis comes only from the target particle and the data have a simple relationship to the chemistry and the sensitivity for the light element (O) is excellent, providing simple and direct qualitative identification of the oxide compound.

APA, Harvard, Vancouver, ISO, and other styles

6

Duruk, Alper, Ece Olcay Güneş, and Hakan Kuntman. "A new low voltage CMOS differential OTRA for sub-micron technologies." AEU - International Journal of Electronics and Communications 61, no. 5 (May 2007): 291–99. http://dx.doi.org/10.1016/j.aeue.2006.05.009.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Kaloyeros, Alain E., and Michael A. Fury. "Chemical Vapor Deposition of Copper for Multilevel Metallization." MRS Bulletin 18, no. 6 (June 1993): 22–29. http://dx.doi.org/10.1557/s0883769400047291.

Full text

Abstract:

Since the birth of integrated circuitry about thirty five years ago, microelectronics design and manufacturing technologies have evolved toward higher integration density with smaller design rules. As the semiconductor industry moves into ultra-large-scale integration (ULSI), device geometries continue to shrink into the sub-half-micron region while circuit densities increase to optimize reliability and improve performance. The resulting demands on interconnect technologies necessitate the exploitation of all development avenues: design, materials, and manufacturing.Emerging sub-half-micron technologies require multilevel metallization (MLM) design schemes that reduce interconnection lengths and lead to lower signal transmission delays and enhanced device speeds. MLM schemes also permit increased device density, due to the ability to use the third (vertical) dimension, and easier signal routing because of higher flexibility in architectural design. These schemes, in turn, demand interconnect metals that can handle the higher current densities resulting from the decreasing size of device features, without the loss of electrical and structural integrity, and deliver the sheet resistance needed to meet performance demands. They also require reliable deposition techniques to successfully fabricate the increasingly complex architectures as lateral feature sizes are scaled down more rapidly than conductor or insulator thicknesses.

APA, Harvard, Vancouver, ISO, and other styles

8

Bude, Jeff D. "Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures." VLSI Design 8, no. 1-4 (January 1, 1998): 13–19. http://dx.doi.org/10.1155/1998/10649.

Full text

Abstract:

Although impact ionization feedback is recognized as an important current multiplication mechanism, its importance as a carrier heating mechanism has been largely overlooked. This work emphasizes the inclusion of impact ionization feedback in Monte Carlo device simulations, and its implications for carrier heating in sub-micron CMOS and EEPROM technologies.

APA, Harvard, Vancouver, ISO, and other styles

9

Vishnoi, U., and T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies." Advances in Radio Science 10 (September 18, 2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.

Full text

Abstract:

Abstract. The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz−1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

APA, Harvard, Vancouver, ISO, and other styles

10

Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.

Full text

Abstract:

Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.

APA, Harvard, Vancouver, ISO, and other styles

11

Baldi, L., B. Franzini, D. Pandini, and R. Zafalon. "Design solutions for the interconnection parasitic effects in deep sub-micron technologies." Microelectronic Engineering 55, no. 1-4 (March 2001): 11–18. http://dx.doi.org/10.1016/s0167-9317(00)00423-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Gelpey, Jeffrey C., Steve McCoy, Dave Camm, and Wilfried Lerch. "An Overview of ms Annealing for Deep Sub-Micron Activation." Materials Science Forum 573-574 (March 2008): 257–67. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.257.

Full text

Abstract:

Millisecond annealing (MSA) has been developed over the last several years as a viable approach to achieve the high electrical activation, limited diffusion and high abruptness needed for junctions in the sub-65nm regime. This paper will provide an overview of the technology including the motivation, technology and some process results. Both main approaches for MSA, sub-melt laser and flash lamp annealing will be discussed as well as the potential challenges to bring these technologies into mainstream manufacturing.

APA, Harvard, Vancouver, ISO, and other styles

13

Armigliato, A., R. Balboni, G. P. Carnevale, P. Colpani, S. Frabboni, and G. Pavia. "Strain Field Distribution in Submicron Devices by TEM/CBED. A European Project." Microscopy and Microanalysis 6, S2 (August 2000): 1076–77. http://dx.doi.org/10.1017/s1431927600037879.

Full text

Abstract:

It is now widely accepted that one of the major issues for the future deep sub-micron integrated circuit (IC) technologies regarding yield, device performance and stability and device and product reliability, is the mechanical stress built up in the layers and substrate. It is therefore important to give a quantitative account of these stresses and this can only be achieved by disposing of reliable, performant (as to spatial resolution) and quantitative techniques for the local stress determination in the substrate, of adequate and dedicated process simulation tools and of sensitive methods to analyse the stress effects on device performance.The only experimental technique presently available which allows the strain field distribution in sub-micron CMOS devices is the convergent beam electron diffraction technique of the transmission electron microscopy. Its sensitivity is of the order of 10-4 and its spatial resolution is of 1 nm if a TEM/FEG is employed.

APA, Harvard, Vancouver, ISO, and other styles

14

Ludeke, Sascha, and Arto Javanainen. "Proton Direct Ionization in Sub-Micron Technologies: Numerical Method for RPP Parameter Extraction." IEEE Transactions on Nuclear Science 69, no. 3 (March 2022): 254–63. http://dx.doi.org/10.1109/tns.2022.3147592.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Chen, X. Y., J. A. Johansen, C. Salm, and A. D. van Rheenen. "On low-frequency noise of polycrystalline GexSi1−x for sub-micron CMOS technologies." Solid-State Electronics 45, no. 11 (November 2001): 1967–71. http://dx.doi.org/10.1016/s0038-1101(01)00242-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Balasubramanian, A., A. L. Sternberg, B. L. Bhuva, and L. W. Massengill. "Crosstalk Effects Caused by Single Event Hits in Deep Sub-Micron CMOS Technologies." IEEE Transactions on Nuclear Science 53, no. 6 (December 2006): 3306–11. http://dx.doi.org/10.1109/tns.2006.884675.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Pak, Murat, Zeliha Yilmaz, and Aylin Ersoy. "A Novel OPC Technique for 2D Critical Dimension Optimization of Sub-micron Patterns using an Experimental Methodology." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000702–9. http://dx.doi.org/10.4071/isom-2012-wa56.

Full text

Abstract:

As the development of the ULSI technique with respect to the decrease in the feature sizes, critical dimension has become a vital parameter for the IC manufacturing. For sub-micron technologies, there has always been a significant mismatch between the layout and post lithography patterns. Since most of the conventional optimization techniques are model based, it is quite hard to obtain a good accuracy for a real-world solution. Moreover, these methods can not easily be integrated to any fabrication environment. This paper presents a layout correction technique which uses a look-up table of measured patterns with 0.3um and 0.4um critical dimensions. An interpolation method that takes the design grids into account has been used to obtain the optimum layout for sub-micron ULSI circuits. This paper not only focuses on an experimental and accurate critical dimension optimization, but also draws attention how to implement this methodology for any fabrication environment.

APA, Harvard, Vancouver, ISO, and other styles

18

NGAN, A. H. W., P. C. WO, L. ZUO, H. LI, and N. AFRIN. "THE STRENGTH OF SUBMICRON-SIZED MATERIALS." International Journal of Modern Physics B 20, no. 25n27 (October 30, 2006): 3579–86. http://dx.doi.org/10.1142/s0217979206040027.

Full text

Abstract:

Recent rapid advancements in nano- and micro-machinery technologies call for an urgent need to understand the mechanical behaviour of materials of dimensions in the sub-micron regime. The initial yield strength of submicron crystals exhibits remarkable statistical scatter as well as dependence upon size and time under load. Submicron-sized materials are also found to creep many orders of magnitude faster than bulk counterparts. In this paper, the recent experimental evidence for these phenomena is reviewed. Theoretical explanation of these phenomena is also discussed. The statistical scatter and time dependence of the yield strength are interpreted by a scaling model derived from atomistic simulations. The results indicate that, within a certain load range, the strength of a sub-micron sized material is not deterministic and can only be described by a survival probability. The much faster creep in the submicron regime is interpreted in terms of the much shorter diffusion length compared to bulk creep.

APA, Harvard, Vancouver, ISO, and other styles

19

Nunes, A. M., S. A. Moshkalev, P. J. Tatsch, and A. M. Daltrini. "Plasma Etching of Polycrystalline Silicon using Thinning Technology for Application in CMOS and MEMS Technologies." Journal of Integrated Circuits and Systems 2, no. 2 (November 18, 2007): 74–80. http://dx.doi.org/10.29292/jics.v2i2.269.

Full text

Abstract:

This work presents results of the study of profile evolution for Si-poly structures during plasma etching using the thinning technology in SF6/CF4/CHF3 gas mixtures. Structures with an aspect ratio (height/width) up to 5, widths end in the range of 0.3 – 0.1 μm and 0.3μm thick, were produced. Sipoly structures with high anisotropy (anisotropy factor up to 0.92-0.98) after etching were demostrated. The method can be used for fabrication of sub-micron Si-poly gates in CMOS and in fabrication of MEMS devices.

APA, Harvard, Vancouver, ISO, and other styles

20

SHANG, Kefeng, Wudi CAO, Weiwei HUAN, Nan JIANG, Na LU, and Jie LI. "Effect of megapore particles packing on dielectric barrier discharge, O₃ generation and benzene degradation." Plasma Science and Technology 24, no. 1 (November 22, 2021): 015501. http://dx.doi.org/10.1088/2058-6272/ac3379.

Full text

Abstract:

Abstract Recently, packed-bed discharge plasma technologies have been widely studied for treatment of volatile organic compounds (VOCs), due to the good performance in improving the degradation and mineralization of VOCs. In this paper, a coaxial cylindrical dielectric barrier discharge reactor packed with porous material of micron-sized pores was used for degradation of benzene, and the discharge characteristics and ozone generation characteristics were studied. When the discharge length was 12 cm and the filling length was 5 cm, the packed particles in the discharge area significantly increased the number of micro-discharges, and the current amplitude and density increased with the pore size of packed particles, but the discharge power and ozone concentration showed a trend of first increasing and then decreasing. The discharge power and ozone production reached the maximum when the size of pore former was 75 μm, correspondingly, the degradation efficiency of benzene was the highest.

APA, Harvard, Vancouver, ISO, and other styles

21

Fossum, Jon Otto. "Clay nanolayer encapsulation, evolving from origins of life to future technologies." European Physical Journal Special Topics 229, no. 17-18 (November 2020): 2863–79. http://dx.doi.org/10.1140/epjst/e2020-000131-1.

Full text

Abstract:

AbstractClays are the siblings of graphite and graphene/graphene-oxide. There are two basic ways of using clays for encapsulation of sub-micron entities such as molecules, droplets, or nanoparticles, which is either by encapsulation in the interlayer space of clay nanolayered stacked particles (“the graphite way”), or by using exfoliated clay nanolayers to wrap entities in packages (“the graphene way”). Clays maybe the prerequisites for life on earth and can also be linked to the natural formation of other two-dimensional materials such as naturally occurring graphite and its allotropes. Here we discuss state-of-the-art in the area of clay-based encapsulation and point to some future scientific directions and technological possibilities that could emerge from research in this area.

APA, Harvard, Vancouver, ISO, and other styles

22

Krishna, R., and Punithavathi Duraiswamy. "Low leakage 10T SRAM cell with improved data stability in deep sub-micron technologies." Analog Integrated Circuits and Signal Processing 109, no. 1 (May 6, 2021): 153–63. http://dx.doi.org/10.1007/s10470-021-01870-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Fobelets, K., W. Jeamsaksiri, C. Papavasilliou, T. Vilches, V. Gaspari, J. E. Velazquez-Perez, K. Michelakis, T. Hackbarth, and U. König. "Comparison of sub-micron Si:SiGe heterojunction nFETs to Si nMOSFET in present-day technologies." Solid-State Electronics 48, no. 8 (August 2004): 1401–6. http://dx.doi.org/10.1016/j.sse.2004.01.017.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Ning, Zhenqiu, Yuri Sneyders, Wim Vanderbauwhede, Renaud Gillon, Marnix Tack, and Paul Raes. "A compact test structure for characterisation of leakage currents in sub-micron CMOS technologies." Microelectronics Reliability 41, no. 12 (December 2001): 1939–45. http://dx.doi.org/10.1016/s0026-2714(01)00100-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Jo, Seongmin, and Yong Ho Song. "Leakage-aware adaptive routing for pipelined on-chip networks in ultra-deep sub-micron technologies." IEICE Electronics Express 9, no. 24 (2012): 1887–92. http://dx.doi.org/10.1587/elex.9.1887.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Samanta, Smrutilekha, Bhawna Tiwari, Pydi Ganga Bahubalindruni, Pedro Barquinha, and Joao Goes. "Threshold voltage extraction techniques adaptable from sub-micron CMOS to large-area oxide TFT technologies." International Journal of Circuit Theory and Applications 45, no. 12 (April 5, 2017): 2201–10. http://dx.doi.org/10.1002/cta.2340.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Dishari, Shudipto K. "(Invited) Novel Nature-Inspired Concepts to Design Ionomeric Nanomaterials for Energy Conversion and Storage Devices." ECS Meeting Abstracts MA2022-01, no. 38 (July 7, 2022): 1707. http://dx.doi.org/10.1149/ma2022-01381707mtgabs.

Full text

Abstract:

Ion-conducting polymers (ionomers) are an integral part of renewable energy-driven technologies. Proton exchange membrane fuel cells (PEMFCs) have already been incorporated into low-duty vehicles and are now being adopted in heavy-duty vehicles. Therefore, we need more durable and efficient fuel cell materials than ever. A major technical challenge of PEMFCs is the ion transport limitation at the ionomer-catalyst interface which negatively impacts the efficiency of the cells. The current state-of-the-art fuel cell ionomers (both fluorocarbon- and hydrocarbon-based) conduct protons efficiently in bulk, several tens of micron thick, free-standing membranes, but poorly in sub-micron thick films. This needs attention as sub-micron thick ionomer layers are used as catalyst binders on electrodes of PEMFCs and other energy conversion and storage devices. However, the nanoscale behavior of these existing ionomers within complex hydration environment is not well-understood yet. More importantly, ionomers are rarely designed to improve the thin film ion conduction properties. To address and overcome these issues, we do not only design innovative nanoscale materials characterization techniques to explore the distribution of ion conduction environment across ionomer films/membrane, but also design novel classes of ionomers inspired by natural living systems to facilitate ion conduction in thin films. We experimentally measure the ion conductivity, morphology, and mechanical properties, and combine them with computational studies to elevate our understanding of ion conduction mechanism within 10-200 nm thick films of these newly designed ionomers. The results suggest the great promise of these new classes of ionomers as efficiently ion-transporting catalyst binders for fuel cells, electrolyzers, and batteries.

APA, Harvard, Vancouver, ISO, and other styles

28

Zhao, Gaoyang, Zhen Wei, Weilei Wang, Daohuan Feng, Aoxue Xu, Weili Liu, and Zhitang Song. "Review on modeling and application of chemical mechanical polishing." Nanotechnology Reviews 9, no. 1 (March 12, 2020): 182–89. http://dx.doi.org/10.1515/ntrev-2020-0016.

Full text

Abstract:

AbstractWith the development of integrated circuit technology, especially after entering the sub-micron process, the reduction of critical dimensions and the realization of high-density devices, the flatness between integrated circuit material layers is becoming more and more critical. Because conventional mechanical polishing methods inevitably produce scratches of the same size as the device in metal or even dielectric layers, resulting in depth of field and focus problems in lithography. The first planarization technique to achieve application is spin on glass (SOG) technology. However, this technology will not only introduce new material layers, but will also fail to achieve the global flattening required by VLSI and ULSI technologies. Moreover, the process instability and uniformity during spin coating do not meet the high flatness requirements of the wafer surface. Also, while some techniques such as reverse etching and glass reflow can achieve submicron level regional planarization. After the critical dimension reaches 0.35 microns (sub-micron process), the above methods cannot meet the requirements of lithography and interconnect fabrication. In the 1980s, IBM first introduced the chemical mechanical polishing (CMP) technology used to manufacture precision optical instruments into its DRAM manufacturing [1]. With the development of technology nodes and critical dimensions, CMP technology has been widely used in the Front End Of Line (FEOL) and Back End Of Line (BEOL) processes [2]. Since the invention of chemical mechanical polishing, scientists have not stopped studying its internal mechanism. From the earliest Preston Formula (1927) to today’s wafer scale, chip scale, polishing pad contact, polishing pad - abrasive - wafer contact and material removal models, there are five different scale models from macro to the micro [3]. Many research methods, such as contact mechanics, multiphase flow kinetics, chemical reaction kinetics, molecular dynamics, etc., have been applied to explain the principles of chemical mechanical polishing to establish models. This paper mainly introduces and summarizes the different models of chemical mechanical polishing technology. The various application scenarios and advantages and dis-advantages of the model are discussed, and the development of modeling technology is introduced.

APA, Harvard, Vancouver, ISO, and other styles

29

Hwang, T., G. W. Wang, Y. Chang, and C. L. Lau. "Comparison of Single and Tri‐Layer Technologies for Volume Production of Sub‐Half Micron Gate GaAs MESFETs." Journal of The Electrochemical Society 139, no. 2 (February 1, 1992): 625–28. http://dx.doi.org/10.1149/1.2069269.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Javaheri, Reza, and Reza Sedaghat. "Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies." Microelectronics Reliability 49, no. 2 (February 2009): 178–85. http://dx.doi.org/10.1016/j.microrel.2008.11.010.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Waghmare, Parag C., Samadhan B. Patil, Alka Kumbhar, R. O. Dusane, and V. Ramgopal Rao. "Ultra-thin silicon nitride by hot wire chemical vapor deposition (HWCVD) for deep sub-micron CMOS technologies." Microelectronic Engineering 61-62 (July 2002): 625–29. http://dx.doi.org/10.1016/s0167-9317(02)00575-0.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Millan, Alejandro, Manuel J. Bellido, Jorge Juan, David Guerrero, Paulino Ruiz-de-Clavijo, and Julian Viejo. "Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies." Journal of Low Power Electronics 6, no. 1 (April 1, 2010): 93–102. http://dx.doi.org/10.1166/jolpe.2010.1059.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

Full text

Abstract:

In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.

APA, Harvard, Vancouver, ISO, and other styles

34

Bashirpour, Mohammad, Wei Cui, Angela Gamouras, and Jean-Michel Ménard. "Scalable Fabrication of Nanogratings on GaP for Efficient Diffraction of Near-Infrared Pulses and Enhanced Terahertz Generation by Optical Rectification." Crystals 12, no. 5 (May 10, 2022): 684. http://dx.doi.org/10.3390/cryst12050684.

Full text

Abstract:

We present a process flow for wafer-scale fabrication of a surface phase grating with sub-micron feature sizes from a single semiconductor material. We demonstrate this technique using a 110-oriented GaP semiconductor wafer with second-order nonlinearity to obtain a nanostructured device (800 nm lateral feature size and a 245 nm height modulation) with applications relevant to near-infrared optical diffraction and time-resolved terahertz (THz) technologies. The fabrication process involves a plasma-enhanced chemical deposition of a SiO2 layer on the wafer followed by contact photolithography and inductively coupled plasma reactive ion etching (ICP-RIE). We discuss the required radiation dosage, exposure times, temperatures and other key parameters to achieve high-quality nanogratings in terms of filling ratio, edge profile, and overall shape. The phase-grating properties, such as the pitch, spatial homogeneity, and phase retardation, are characterized with an atomic force microscope, scanning electron microscope and a non-invasive optical evaluation of the optical diffraction efficiency into different orders. We demonstrate an application of this device in a time-domain THz spectroscopy scheme, where an enhanced THz spectral bandwidth is achieved by optical rectification of near-infrared laser pulses incident on the grating and efficiently diffracted into the first orders. Finally, the reported process flow has the potential to be applied to various materials by considering only slight adjustments to the ICP-RIE etching steps, paving the way to scalable fabrication of sub-micron patterns on a large range of substrates.

APA, Harvard, Vancouver, ISO, and other styles

35

Cox Jr, Kevin L., Sai Guna Ranjan Gurazada, Keith E. Duncan, Kirk J. Czymmek, Christopher N. Topp, and Blake C. Meyers. "Organizing your space: The potential for integrating spatial transcriptomics and 3D imaging data in plants." Plant Physiology 188, no. 2 (November 2, 2021): 703–12. http://dx.doi.org/10.1093/plphys/kiab508.

Full text

Abstract:

Abstract Plant cells communicate information for the regulation of development and responses to external stresses. A key form of this communication is transcriptional regulation, accomplished via complex gene networks operating both locally and systemically. To fully understand how genes are regulated across plant tissues and organs, high resolution, multi-dimensional spatial transcriptional data must be acquired and placed within a cellular and organismal context. Spatial transcriptomics (ST) typically provides a two-dimensional spatial analysis of gene expression of tissue sections that can be stacked to render three-dimensional data. For example, X-ray and light-sheet microscopy provide sub-micron scale volumetric imaging of cellular morphology of tissues, organs, or potentially entire organisms. Linking these technologies could substantially advance transcriptomics in plant biology and other fields. Here, we review advances in ST and 3D microscopy approaches and describe how these technologies could be combined to provide high resolution, spatially organized plant tissue transcript mapping.

APA, Harvard, Vancouver, ISO, and other styles

36

Pandey, Ayush, Yixin Xiao, Maddaka Reddeppa, Yakshita Malhotra, Jiangnan Liu, Jungwook Min, Yuanpeng Wu, and Zetian Mi. "A red-emitting micrometer scale LED with external quantum efficiency >8%." Applied Physics Letters 122, no. 15 (April 10, 2023): 151103. http://dx.doi.org/10.1063/5.0129234.

Full text

Abstract:

Significant efforts are being put into the development of efficient micrometer-scale light emitting diodes (LEDs) for future display technologies due to their marked benefits over existing displays. To date, however, the efficiency of microLED devices remains significantly lower than that of conventional broad-area devices. The deterioration in device performance with smaller device size has been linked to the plasma damage induced on mesa sidewalls during device fabrication. Here, we studied bottom-up red-emitting nanowire LEDs with different Mg doping levels in the p-GaN layer. The resulting sub-micron LED devices show a distinct improvement in efficiency with increasing Mg dopant incorporation. Through optimization of the doping, we measured an external quantum efficiency of ∼8.3% and a wall-plug efficiency of ∼4.6%, at a current density of ∼1 A/cm2, for a red-emitting sub-micrometer scale LED operating at >630 nm. This study highlights the importance of p-doping in microLEDs for attaining high efficiency performance in nanostructure-based devices.

APA, Harvard, Vancouver, ISO, and other styles

37

Chrzanowska-Jeske, Malgorzata, Yang Xu, and Marek Perkowski. "Logic Synthesis for a Regular Layout." VLSI Design 10, no. 1 (January 1, 1999): 35–55. http://dx.doi.org/10.1155/1999/85272.

Full text

Abstract:

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.

APA, Harvard, Vancouver, ISO, and other styles

38

Xu, Yux, Ping Xiang, and Xiaopeng Xie. "Comprehensive understanding of dark count mechanisms of single-photon avalanche diodes fabricated in deep sub-micron CMOS technologies." Solid-State Electronics 129 (March 2017): 168–74. http://dx.doi.org/10.1016/j.sse.2016.11.009.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Verhaege, Koen G., and Christian C. Russ. "Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies." Microelectronics Reliability 41, no. 11 (November 2001): 1739–49. http://dx.doi.org/10.1016/s0026-2714(01)00030-0.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Sexton, B. A., and R. J. Marnock. "Characterization of High Resolution Resists and Metal Shims by Scanning Probe Microscopy." Microscopy and Microanalysis 6, no. 2 (March 2000): 129–36. http://dx.doi.org/10.1007/s100059910012.

Full text

Abstract:

Technologies such as compact disc (CD) manufacturing, hologram embossing, and security printing rely on the reproduction of micro-patterns generated on surfaces by optical or electron-beam lithographic writing onto electron-beam or photoresists. The periodicity of such patterns varies from sub-micron to several microns, with depths up to 0.5 μm. The scanning probe microscope (SPM) is becoming a routine tool for analysis of these micro-patterns, to check on depths and lateral dimensions of features. Direct scanning of resist-covered plates is now possible, without damage, using resonant low-contact force SPM with etched silicon cantilevers. Metal shims produced from the master resist plates can also be scanned and checked for defects prior to production of embossed foils. The present article discusses examples of the use of a Digital Instruments 3100 microscope in analysis of production electron-beam lithography plates with a 0.5 μm resist thickness. We also examine features of nickel replicas (father and mother shims) produced by electroforming from the original plate. With SPM measurements of the development profile of a particular plate, corrections can be made to exposures and development times during production to correct errors. An example is given of such a feedback process.

APA, Harvard, Vancouver, ISO, and other styles

41

Maj, P. "Fast and precise algorithms for calculating offset correction in single photon counting ASICs built in deep sub-micron technologies." Journal of Instrumentation 9, no. 07 (July 9, 2014): C07009. http://dx.doi.org/10.1088/1748-0221/9/07/c07009.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

TANIGUCHI, Kazuhiro. "New Technologies for Scaled-down Cu Interconnection in Ultra-Large Scale Integrated Circuits. Copper Deposition System for Sub-micron Patterning." Journal of the Surface Finishing Society of Japan 49, no. 11 (1998): 1176–79. http://dx.doi.org/10.4139/sfj.49.1176.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Byeon, Kyeong Jae, Sung Hoon Hong, Ki Yeon Yang, Seung Hyun Ra, Jin Ho Ahn, and Heon Lee. "Embossing Lithography on Sticky Thermoset Polymer Using Ni Template." Solid State Phenomena 124-126 (June 2007): 147–51. http://dx.doi.org/10.4028/www.scientific.net/ssp.124-126.147.

Full text

Abstract:

Embossing lithography is one of the most promising technologies for mass production of nano-scale structures. To advance the industrialization of embossing lithography, fabrication of low cost, high mechanical strength embossing template is essential. Electroformed Ni template can be used as an embossing template if its poor anti-adhesive property is fixed by proper releasing layer treatment, especially, when it is used with sticky thermoset polymer. In this experiment, quartz master template with 200nm to 2um sized surface protrusions was fabricated and used to emboss the PMMA coated Si wafer. Then the embossed PMMA layer was coated with metal seed layer (Ni) and electroplating of Ni was followed to fabricate Ni template. To apply anti-stiction SAM layer, SiO2 and Si layer was coated on Ni template. With proper anti-stiction treatment of Ni template, sub-micron patterns were successfully transferred to sticky thermoset polymers such as epoxy resin using Ni template without any degradation of anti-adhesive property.

APA, Harvard, Vancouver, ISO, and other styles

44

Xiao, Tong, and Malgorzata Marek-Sadowska. "Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis." VLSI Design 15, no. 3 (January 1, 2002): 647–66. http://dx.doi.org/10.1080/1065514021000012264.

Full text

Abstract:

Crosstalk-induced delay in deep sub-micron digital circuits can be quite significant and difficult to determine because of dependency on neighboring signals. In this paper we study the problem of incorporating temporal and functional information to improve the accuracy of crosstalk aware static timing analysis. We propose an efficient method to compute a signal's earliest and latest arrival times when timing windows and slew rate ranges are known for its inputs and its coupling neighbors' inputs. We show that iteratively updating timing windows is necessary when signals on the same path are mutually coupled. The accuracy of static timing analysis can be further improved by our functional correlation analysis. The proposed techniques have been applied in crosstalk aware static timing analysis, which can guide timing-driven layout synthesis and quick timing verification in deep submicron technologies. Experimental results demonstrate that the proposed methods significantly reduce the pessimism in predicting circuit performance.

APA, Harvard, Vancouver, ISO, and other styles

45

Waghmare, Parag C., Samadhan B. Patil, Alka A. Kumbhar, Ramgopal Rao, and R. O. Dusane. "Nitrogen dilution effects on structural and electrical properties of hot-wire-deposited a-SiN:H films for deep-sub-micron CMOS technologies." Thin Solid Films 430, no. 1-2 (April 2003): 189–91. http://dx.doi.org/10.1016/s0040-6090(03)00108-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Chatterjee, Sayan. "Study and Analysis of Full Adder in Different Sub-Micron Technologies with an Area Efficient Layout of 4-Bit Ripple Carry Adder." International Journal of Innovative Research in Computer and Communication Engineering 03, no. 06 (June 10, 2015): 4979–84. http://dx.doi.org/10.15680/ijircce.2015.0306005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Nadeem, Irfan, Rehan Akhter, Shazeen Akhtar, and Anjum Tauqir. "Optimization of Pulsed Fiber Laser Texturing for Solid Lubricant Deposition on a Ti/TiN Coated Aerospace Alloy." Key Engineering Materials 875 (February 2021): 337–45. http://dx.doi.org/10.4028/www.scientific.net/kem.875.337.

Full text

Abstract:

AA2219 is a superior performance Al-base alloy which promises toughness, strength and creep resistance which allows the deposition of titanium nitride (TiN) coating at 200 °C. The present research addresses the issue of poor wear properties of the alloy, using state of the art technologies, to deposit hard and adherent thin TiN layer followed by laser surface texturing. The thickness of sub-micron size coating is determined by appropriate modification of the existing mathematical model and composite microhardness values. Laser energy density of 20.8 J/cm2 and 4 repeated pulses is optimized to produce regular size and shape of micro-holes on TiN-coated samples. Epoxy-based MoS2 lubricant is deposited on laser textured samples to produce ultra-low friction surfaces. The micro-holes act as a micro-reservoir of MoS2 solid lubricant. Field emission scanning electron microscope and optical profilometer were used to estimate the topology, shape, size, and depth of micro-holes. The cross-sectional view shows the successful impregnation of epoxy-based MoS2 due to the chemisorption of functional groups with an Al oxide surface.

APA, Harvard, Vancouver, ISO, and other styles

48

Faraji Rad, Zahra, Philip D. Prewett, and Graham J. Davies. "An overview of microneedle applications, materials, and fabrication methods." Beilstein Journal of Nanotechnology 12 (September 13, 2021): 1034–46. http://dx.doi.org/10.3762/bjnano.12.77.

Full text

Abstract:

Microneedle-based microdevices promise to expand the scope for delivery of vaccines and therapeutic agents through the skin and withdrawing biofluids for point-of-care diagnostics – so-called theranostics. Unskilled and painless applications of microneedle patches for blood collection or drug delivery are two of the advantages of microneedle arrays over hypodermic needles. Developing the necessary microneedle fabrication processes has the potential to dramatically impact the health care delivery system by changing the landscape of fluid sampling and subcutaneous drug delivery. Microneedle designs which range from sub-micron to millimetre feature sizes are fabricated using the tools of the microelectronics industry from metals, silicon, and polymers. Various types of subtractive and additive manufacturing processes have been used to manufacture microneedles, but the development of microneedle-based systems using conventional subtractive methods has been constrained by the limitations and high cost of microfabrication technology. Additive manufacturing processes such as 3D printing and two-photon polymerization fabrication are promising transformative technologies developed in recent years. The present article provides an overview of microneedle systems applications, designs, material selection, and manufacturing methods.

APA, Harvard, Vancouver, ISO, and other styles

49

Paradhasaradhi, Damarla, Kollu Jaya Lakshmi, Yadavalli Harika, Busa Ravi Teja Sai, and Golla Jayanth Krishna. "Comparative analysis of SRAM cell with leakage power reduction approaches." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 863. http://dx.doi.org/10.14419/ijet.v7i2.7.11083.

Full text

Abstract:

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

APA, Harvard, Vancouver, ISO, and other styles

50

Heimbrook, L. A. "Analytical solutions for complex problems using multiple diagnostic techniques." Proceedings, annual meeting, Electron Microscopy Society of America 53 (August 13, 1995): 686–87. http://dx.doi.org/10.1017/s0424820100139809.

Full text

Abstract:

The ability to apply multiple diagnostic techniques to complex material, biological, and device problems with the goal of obtaining analytical solutions is the daily objective of the typical analytical laboratory. This paper will describe the use of both microscopy and surface analysis diagnostic tools to evaluate routine and highly complex material and device problems often found in the semiconductor industry. The characterization requirements for silicon and III-V materials and devices cover a wide range of technology research and development programs. These programs involve the characterization of starting materials, doping and implant technologies, thin film technology, particle and contamination issues and final device inspection. Continued advances in ultra-shallow silicon devices and multi-quantum-well (MQW) lasers rely on the accurate introduction of doping elements, the ability to deposit high quality materials of specified layer thicknesses and on advances in fabrication and characterization tools.The complex analysis problems of evaluating ultra shallow junctions in sub-micron silicon devices and the measurement of grating depths and duty cycles in semiconductor lasers are the characterization challenges which will be addressed in this paper.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!