Dissertations / Theses on the topic 'SUB MICRON TECHNOLOGIES'

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 161).
In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.
by James Boe-Kian Oey.
M.Eng.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.

I microfoni sono sempre piu' diffusi nei dispositivi elettronici che utilizziamo quotidianamente. L'importanza di una interazione piu' naturale ed immediata ha spinto l'utilizzo del riconoscimento vocale anche in prodotti a basso costo e di larghissima diffusione. Di conseguenza e' aumentata la richiesta di microfoni sempre piu' performanti, con package miniaturizzati e costi ridotti. Questa tesi, svolta presso Infineon Technologies, illustra il processo di sviluppo di un microfono ad elevate prestazioni capace di ottenere un rapporto segnale/rumore (SNR) di 72dB(A) con un livello di saturazione acustica (AOP) di 130dB SPL. Il sistema si basa su un sensore MEMS di ultima generazione unito ad un circuito di interfaccia (ASIC) riprogettato per sfruttare le peculiarita' del trasduttore. L'ASIC e' caratterizzato da un amplificatore d'ingresso di tipo current-feedback che permette di minimizzare il rapporto segnale/rumore e da un convertirore analogico/digitale riconfigurabile per adattare il consumo di potenza alle prestazioni richieste dal sistema.
Microphone systems are extremely widespread in today's consumer electronics, the urge of a more natural interaction with our devices has heavily pushed voice recognition even in portable devices, forcing industry to create suitable products. This thesis describes the development of a new digital read-out ASIC that paired with Infineon Technologies latest sealed-dual membrane (SDM) MEMS transducer forms a prototype for a new high-end microphone product. State-of-the-art noise performance is achieved thanks to significant optimizations both on the MEMS as well as on the ASIC side. The ASIC features an unconventional read-out amplifier based on a power-scalable current-feedback architecture as well as a reconfigurable ΔΣ modulator allowing to trade-off signal-to-noise ratio (SNR) versus power consumption. The microphone system achieves an SNR of 72dB(A) supporting an acoustical overload point (AOP) of 130dB SPL. This represents a significant improvement to current state-of-the-art digital microphones.

Les interconnexions des circuits intégrés sub-0.25µm nécessitent l'intégration d'isolants «low-K» à plus faible permittivité diélectrique que SiO2 (~ 4.4) tel que le SiLK™ (~ 2.65), un matériau organique prometteur. Mais sa gravure plasma conduit à l'obtention de structures en forme de tonneau («bow»), alors que les profils gravés doivent rester anisotropes pour les étapes ultérieures d'intégration. Afin de réduire le bow, cette étude montre que la passivation des flancs des structures gravées est nécessaire, et fortement corrélée à la dégradation («graphitisation») du SiLK et à la présence de résidus carbonés peu volatils dans le plasma. La présence de sources carbonées autres que le SiLK™ permet aussi d'améliorer la passivation. L'étude du phénomène à l'origine du bow montre enfin que les charges électrostatiques jouent un rôle majoritaire dans la déflexion des ions sur les flancs. Ces résultats intéressent également tous les low-Ks à faible seuil de gravure ionique réactive.

Effective daylighting can substantially reduce the energy use and greenhouse gas emissions of commercial buildings. Daylight is also healthy for building occupants, and contributes to occupant satisfaction. When productivity improvements are considered, effective daylighting is also highly attractive financially. However, successful daylighting of sub-tropical buildings is a very difficult task, due to high direct irradiances and excessive solar shading. A device was created that combined effective solar shading and efficient daylight redirection. The micro-light guiding shade panel achieves all objectives of an optimal daylighting device placed on the façade of a sub-tropical, high rise office building. Its design is based on the principles of non-imaging optics. This provides highly efficient designs offering control over delivered illumination, within the constraints of the second law of thermodynamics. Micro-light guiding shade panels were constructed and installed on a test building. The tested devices delivered daylight deep into the building under all conditions. Some glare was experienced with a poorly chosen translucent material. Glare was eliminated by replacing this material. Construction of the panels could be improved by application of mass-manufacturing techniques including metal pressing. For the micro-light guiding shade panel to be utilised to its full potential, building designers must understand its impact on building performance early in the design process. Thus, the device must be modelled with lighting simulation software currently in use by building design firms. The device was successfully modelled by the RADIANCE lighting simulator. RADIANCE predictions compared well with measurements, providing bias generally less than 10%. Simulations greatly aided further development of the micro-light guiding shade panel. Several new RADIANCE algorithms were developed to improve daylight simulation in general.

Effective daylighting can substantially reduce the energy use and greenhouse gas emissions of commercial buildings. Daylight is also healthy for building occupants, and contributes to occupant satisfaction. When productivity improvements are considered, effective daylighting is also highly attractive financially. However, successful daylighting of sub-tropical buildings is a very difficult task, due to high direct irradiances and excessive solar shading. A device was created that combined effective solar shading and efficient daylight redirection. The micro-light guiding shade panel achieves all objectives of an optimal daylighting device placed on the façade of a sub-tropical, high rise office building. Its design is based on the principles of non-imaging optics. This provides highly efficient designs offering control over delivered illumination, within the constraints of the second law of thermodynamics. Micro-light guiding shade panels were constructed and installed on a test building. The tested devices delivered daylight deep into the building under all conditions. Some glare was experienced with a poorly chosen translucent material. Glare was eliminated by replacing this material. Construction of the panels could be improved by application of mass-manufacturing techniques including metal pressing. For the micro-light guiding shade panel to be utilised to its full potential, building designers must understand its impact on building performance early in the design process. Thus, the device must be modelled with lighting simulation software currently in use by building design firms. The device was successfully modelled by the RADIANCE lighting simulator. RADIANCE predictions compared well with measurements, providing bias generally less than 10%. Simulations greatly aided further development of the micro-light guiding shade panel. Several new RADIANCE algorithms were developed to improve daylight simulation in general.

Les décharges électrostatiques (ESD) constituent un problème majeur de fiabilité pour les entreprises de semi-conducteurs. Pour enrayer les défauts générés par les ESD sur les circuits intégrés (ICs), des éléments de protection sont implantés directement dans les puces. La constante poussée de l'intégration des circuits a pour conséquence la réduction des dimensions des cellules technologiques élémentaires ainsi que l'accroissement du nombre d'applications supportées par les ICs. Les conditions restrictives imposées par les procédés technologiques et par la complexité croissante des systèmes entraînent un défi considérablement accru pour le développement de produits robustes aux ESD. Dans ce travail de recherche, le problème émergeant des défaillances des couches d'oxydes minces d'épaisseur Tox = 8 à 1.1nm sous contraintes ESD est adressé dans les technologies CMOS les plus avancées, par une contribution à la compréhension des mécanismes de dégradation de la fiabilité du diélectrique et des dispositifs sous contraintes ESD. Une nouvelle approche de caractérisation des oxydes minces sous des stress à pulses ultra-courts (20 ns) est décrite jusqu'à la modélisation complète de la dépendance temporelle du claquage du diélectrique. Basé sur un ensemble cohérent de modélisations, une nouvelle méthodologie est proposée pour ajuster la détermination de la fenêtre ESD de façon mieux adaptée aux intervalles de tension et d'épaisseur d'oxyde de grille pour l'ingénierie des concepts de protection. Ceci a permis d'améliorer la prise en compte des problèmes ESD pour une meilleure fiabilité et robustesse des produits conçus en technologies CMOS fortement sub-microniques vis-à-vis des décharges électrostatiques.

La miniaturisation des composants électroniques qui permet aujourd'hui une intégration à grande échelle a été possible grâce aux innovations des procédés de fabrication. Ces modifications affectent profondément le comportement électrique des transistors MOS lorsque la longueur de grille devient inférieure à 100nm, altérant notre compréhension physique de ce dispositif. Ce travail de thèse se situe dans le domaine de l'étude des performances des transistors fabriqués dans les filières avancées (technologies sub-45nm) et l'analyse de leur réponse électrique. Il propose d'améliorer les méthodologies existantes et apporte de nouvelles techniques d'extraction qui permettent une analyse des paramètres électriques valide dans un environnement industriel, sur des transistors courts. L'utilisation des ces nouvelles techniques permet une compréhension physique plus juste, utile pour prédire les performances des technologies futures.

L'intégration de diélectriques High- k dans les empilements de grille des transistors a fait naître des problèmes de fiabilité complexes. A cela vient s'ajouter, en vue des technologies sub-32nm planaires, de nouvelles problématiques liées à l'utilisation de substrats silicium sur isolant complètement désertés FDSOI. En effet, l'intégration d'un oxyde enterré sous le film de silicium va modifier électrostatique de la structure et faire apparaître une nouvelle interface Si/SiO2 sujette à d'éventuelles dégradations. Ce manuscrit présente différentes méthodes de caractérisation électrique ainsi que différentes études de fiabilité des dispositifs FDSOI intégrants des empilements High- /grille métallique. Dans un premier temps, une étude complète du couplage électrostatique dans des structures FDSOI est réalisée, permettant de mieux appréhender l'effet d'une tension en face arrière sur les caractéristiques électriques des dispositifs. Différentes méthodes de caractérisation des pièges d'interface sont ensuite présentées et adaptées, lorsque possible, au cas spécifique du FDSOI, où les défauts entre le film de silicium et l'oxyde enterré doivent être pris en compte. Enfin, différentes études de fiabilité sont présentées, des phénomènes de PBTI et de NBTI sur des dispositifs à canaux longs aux phénomènes propres aux dispositifs de petite dimension, tels que l'impact des porteurs chauds dans des structures FDSOI à film ultra fins et les effets d'augmentation de tension de seuil lorsque les largeurs de grille diminuent.

Ce travail de thèse vise l'étude des interactions entre les plasmas utilisés en microélectronique et les résines à amplification chimique. Les procédés de fabrication employés en microélectronique nécessitent l'utilisation de matériaux polymères. Ces matériaux permettent dans un premier temps de définir des motifs représentant les différentes parties des composants électroniques, grâce à une étape de lithographie. Dans la suite du procédé de fabrication, ils jouent le rôle de masque afin de traiter les surfaces sous-jacentes aux endroits désirés. Une de ces étapes pour laquelle le polymère joue le rôle de masque est la gravure sèche par plasma, qui permet de transférer les motifs créés par lithographie dans le substrat et ainsi obtenir la structure du circuit intégré. Ainsi les résines employées doivent être suffisamment résistantes afin de remplir efficacement leur rôle de masque à la gravure. L'objectif principal de ce travail de thèse a donc été d'étudier la résistance à la gravure des résines à amplification chimique de dernière génération (193 nm) afin de mettre en évidence les dégradations de ces matériaux pendant les étapes de gravure, et de trouver des moyens d'améliorer leur résistance. Dans un premier temps le comportement des résines 193 nm a été comparé à une résine de référence plus résistante. Des analyses physico-chimiques (FTIR, XPS, DSC et TGA) ont permis de mettre en évidence les faiblesses des résines 193 nm liées à leur structure acrylique. La chimie des résines 193 nm étant complexe et devant répondre à de nombreux critères notamment pour l'étape de lithographie, il est préférable de les renforcer en tentant de contrôler les dégradations observées. Ainsi le deuxième objectif de la thèse a été d'étudier le renforcement des résines par des procédés plasma en utilisant des conditions particulières différentes des étapes de gravure. Les modifications spécifiques apportées par ces traitements sur les résines ont donc été mises en évidence, et le rôle prépondérant des émissions UV a notamment pu être prouvé. Enfin ces traitements plasma ont été appliqués sur des lignes de résines afin de montrer le fort potentiel applicatif de ces procédés pour améliorer deux points critiques : la vitesse de gravure et la rugosité des motifs.

Integrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions.
text

M.TECH
Control engineering deals with understanding of plant under operation, and obtaining a desired output response in presence of system constraints. There has been an ever increasing demand of controllers in process industry for improving manufacturing processes and energy efficiency. The evolution of submicron technologies has resulted in the requirement to use low power supply voltages which makes it difficult to design voltage mode circuits with high linearity and wide range. Also as signal processing extends to higher frequencies, the traditional design methods based on voltage operational amps are no longer adequate. However generally analog controllers are designed using operational amplifiers. To overcome these problems circuits operating in current mode, which have the inherent property of higher bandwidth, larger dynamic range and better linearity, are preferred. Various analog building blocks operating in the current mode such as various generations of current conveyor, CDBA, OTA, OTRA etc are available in literature. OTRA being a current mode device inherits all the advantages of current mode techniques, in addition it is free from parasitic input capacitances and resistances. In this thesis OTRA based controllers i.e. P, PD, PI and PID with independent tuning of proportional Kp, derivative Kd and integral Ki constants are presented. These configurations can be made fully integrated by implementing the resistors using matched transistors operating in linear region. To observe the effect of controller on second order system a second order low pass filter is designed and simulated. In order to verify the functionality of proposed controller circuits, a closed loop control system using the proposed controllers and second order LPF is designed and simulated using SPICE.

Tang, Xian.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.

Miniaturization of integrated circuits (ICs) due to the improvement in lithographic techniques in modem deep sub-micron (DSM) technologies allows several complex processing elements to coexist in one IC, which are called System-on-Chip. As a first contribution, this thesis quantitatively analyzes the severity of timing constraints associated with Clock Distribution Network (CDN) in modem DSM technologies and shows that different processing elements may work in different dock domains to alleviate these constraints. Such systems are known as Globally Asynchronous Locally Synchronous (GALS) systems. It is imperative that different processing elements of a GALS system need to communicate with each other through some interfacing technique, and these interfaces can be asynchronous or synchronous. Conventionally, the asynchronous interfaces are described at the Register Transfer Logic (RTL) or system level. Such designs are susceptible to certain design constraints that cannot be addressed at higher abstraction levels; crosstalk glitch is one such constraint. This thesis initially identifies, using an analytical model, the possibility of asynchronous interface malfunction due to crosstalk glitch propagation. Next, we characterize crosstalk glitch propagation under normal operating conditions for two different classes of asynchronous protocols, namely bundled data protocol based and delay insensitive asynchronous designs. Subsequently, we propose a logic abstraction level modeling technique, which provides a framework to the designer to verify the asynchronous protocols against crosstalk glitches. The utility of this modeling technique is demonstrated experimentally on a Xilinx Virtex-II Pro FPGA. Furthermore, a novel methodology is proposed to quench such crosstalk glitch propagation through gating the asynchronous interface from sending the signal during potential glitch vulnerable instances. This methodology is termed as crosstalk glitch gating. This technique is successfully applied to obtain crosstalk glitch quenching in the representative interfaces. This thesis also addresses the dock skew challenges faced by high-performance synchronous interfacing methodologies in modem DSM technologies. The proposed methodology allows communicating modules to run at a frequency that is independent of the dock skew. Leveraging a novel clock-scheduling algorithm, our technique permits a faster module to communicate safely with a slower module without slowing down. Safe data communications for mesochronous schemes and for the cases when communicating modules have dock frequency ratios of integer or coprime numbers are theoretically explained and experimentally demonstrated. A clock-scheduling technique to dynamically accommodate phase variations is also proposed. These methods are implemented to the Xilinx Virtex II Pro technology. Experiments prove that the proposed interfacing scheme allows modules to communicate data safely, for mesochronous schemes, at 350 MHz, which is the limit of the technology used, under a dock skew of more than twice the time period (i.e. a dock skew of 12 ns)

Avec la miniaturisation des composants CMOS, l'utilisation du polysilicium comme matériau de grille est aujourd'hui remise en cause. L'insertion d'une couche métallique entre le diélectrique de grille et le polysilicium est alors indispensable mais nécessite le développement de nouveaux procédés de gravure plasma. L'objectif de ce travail est de proposer un procédé de gravure plasma pour la gravure des métaux W et WN dans un empilement polysilicium/TiN/W(WN)/high-k (matériau à haute permittivité diélectrique).
La première étape a donc consisté à caractériser les matériaux de départ en distinguant la caractérisation avant et après intégration dans l'empilement de grille. Les différences révélées à travers cette première étude ont imposé deux stratégies de gravure différentes. Nous proposons une solution en gravant le WN en Cl2/O2 et le W en Cl2/O2/NF3. Cette solution permet une gravure verticale du métal sans dégrader l'intégralité de la grille et le diélectrique sous-jacent.
Le deuxième volet de ce travail a consisté à comprendre de manière approfondie les mécanismes de gravure du W et du WN dans les chimies à base de Cl2/O2. Les aspects étudiés sont les interactions plasma/surface, la composition des plasmas de type Cl2/O2, les couches de passivation qui se forment sur les flancs des motifs gravés et l'état de surface des parois du réacteur.