Journal articles: 'STT-MTJ'

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Jangra, Payal, and Manoj Duhan. "Design and analysis of Voltage-Gated Spin-Orbit Torque (VgSOT) Magnetic Tunnel Junction based Non-Volatile Flip Flop design for Low Energy Applications." Journal of Integrated Circuits and Systems 19, no. 1 (March 15, 2024): 1–12. http://dx.doi.org/10.29292/jics.v19i1.743.

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In this paper, a Voltage-gated Spin-Orbit Torque based non-volatile flip-flop design has been discussed. Theflip-flop consists of a conventional CMOS master latch used in normal operations, and a VgSOT-MTJ basedslave latch has been considered for interim data saving during power-gating. The current circuit uses the samewrite current to write data into two magnetic tunnel junctions, saving 50% of storing energy. The proposedNVFF circuit has been simulated using Cadence Virtuoso 45nm. The performance parameters like energyconsumption and delay during restore and store operations of VgSOT-MTJ based NVFF circuit have beenanalyzed in this paper and compared with SOT-MTJ based and STT-MTJ based NVFF circuits. Simulationresults show that for the switching delay, VgSOT-MTJ based NVFF performs 40% and 58% better than SOT-MTJ NVFF and STT-MTJ based NVFFs, respectively during storing mode and 83% and 88% better than SOT-MTJ and STT-MTJ based NVFFs during restoring mode. In terms of energy consumption, during storingmode, VgSOT-MTJ based NVFF consumes 84% less energy than SOT-MTJ NVFF and 90 % less energy thanSTT-MTJ based NVFFs. During restoring mode, VgSOT-MTJ based NVFF consumes 70% and 80% lessenergy than SOT-MTJ NVFF and STT-MTJ, respectively.

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Bu, Kai, Hai Jun Liu, Hui Xu, and Zhao Lin Sun. "Large Capacity Cache Design Based on Emerging Non-Volatile Memory." Applied Mechanics and Materials 513-517 (February 2014): 918–21. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.918.

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A triple-level-cell (TLC) STT-RAM architecture was proposed basing on parallel MLC MTJ and serial MLC MTJ. A TLC STT-RAM cell can store three bit which will offer higher capacity density compared with SLC STT-RAM. The write process is also analyzed that it contains three types of basic states transitions. Through mapping soft, medium and hard domains to three individual cache lines, the access to soft lines can perform as accessing SLC STT-RAM-based cache. The amount of three-step operations is also much reduced. .

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Rao, Dr G. Anantha, and Gopi Kommuju. "A NOVEL LOW POWER ALU DESIGNED BY USING HYBRID STT-MTJ/CMOS CIRCUIT." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (December 21, 2023): 1–13. http://dx.doi.org/10.55041/ijsrem27641.

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The rise in power dissipation when the technology descends into the deep submicron zone is one of the main issues for CMOS technology due to its non-volatility, high speed, high endurance, CMOS compatibility, and primarily the low power dissipation. magnetic tunnel junction (MTJ) working on Spin transfer torque (STT). Switching mechanism is recognized as one of the most promising spintronic devices for post-CMOS era. This device can provide solutions for the issues posed by existing CMOS technology. We have put out a brand-new hybrid STT- MTJ/CMOS circuit-based logic-in-memory (LIM) P- magnetic arithmetic logic unit (P-MALU) design.. The behavior of P-MALU designs in terms of power dissipation is then studied using Monte-Carlo(MC) simulation, which incorporates process and mismatch variations for CMOS and extracted parameters of MTJ . The P-MALU circuit has also been expanded to provide 4-bit arithmetic operations. Electrical simulations are run to ensure the design's operation. Keywords— MTJ , Spintronics , non-volatility, Switching mechanism ,STT-MTJ, logic in memory, p-magnetic arithematic unit, monte- carlo simulation

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Tankwal, Piyush, Vikas Nehra, Sanjay Prajapati, and Brajesh Kumar Kaushik. "Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates." Circuit World 45, no. 4 (November 4, 2019): 300–310. http://dx.doi.org/10.1108/cw-04-2019-0036.

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Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

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Vatajelu, Elena Ioana, and Giorgio Di Natale. "High-Entropy STT-MTJ-Based TRNG." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 2 (February 2019): 491–95. http://dx.doi.org/10.1109/tvlsi.2018.2879439.

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Xu, Zihan, Chengen Yang, Manqing Mao, Ketul B. Sutaria, Chaitali Chakrabarti, and Yu Cao. "Compact modeling of STT-MTJ devices." Solid-State Electronics 102 (December 2014): 76–81. http://dx.doi.org/10.1016/j.sse.2014.06.003.

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Chiou, Kuan-Ru, Jenq-Wei Chen, and Son-Hsien Chen. "Spin-Transfer Torques in One-Dimensional Magnetic Tunneling Junctions of Lateral Structures." SPIN 09, no. 01 (March 2019): 1950003. http://dx.doi.org/10.1142/s2010324719500036.

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Recent study in [C. C. Lin, Y. F. Gao, A. V. Penumatcha, V. Q. Diep, J. Appenzeller and Z. H. Chen, Acs Nano 8, 3807 (2014)], showed that the spin-transfer torque (STT) is enhanced by the asymmetry in a graphene lateral spin-valve structure. This lateral structure or geometry can be modeled by a four-terminal magnetic tunneling junction (MTJ) as opposite to the conventional two-terminal MTJ. In this paper, using the nonequilibrium Green’s function formalism (NEGF), we compare the anti-damping components of the STT in a similar nonconventional lateral one-dimensional MTJ with that in the conventional MTJ. We find that the lateral geometry renders enhanced anti-damping torques compared with the conventional one, provided that the barrier energy, the scattering length and the magnetization angle are in a certain parameter region. We also identify this parameter region in the presence of dephasing. The enhancement of the anti-damping torques declines when the scattering region is longer. For the four-terminal MTJ of larger scattering length, the dephasing can expedite the anti-damping torque.

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Barla, Prashanth, Hemalatha Shivarama, Ganesan Deepa, and Ujjwal Ujjwal. "Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation." Journal of Low Power Electronics and Applications 14, no. 1 (January 6, 2024): 3. http://dx.doi.org/10.3390/jlpea14010003.

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Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively.

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Pushp, Aakash, Timothy Phung, Charles Rettner, Brian P. Hughes, See-Hun Yang, and Stuart S. P. Parkin. "Giant thermal spin-torque–assisted magnetic tunnel junction switching." Proceedings of the National Academy of Sciences 112, no. 21 (May 13, 2015): 6585–90. http://dx.doi.org/10.1073/pnas.1507084112.

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Spin-polarized charge currents induce magnetic tunnel junction (MTJ) switching by virtue of spin-transfer torque (STT). Recently, by taking advantage of the spin-dependent thermoelectric properties of magnetic materials, novel means of generating spin currents from temperature gradients, and their associated thermal-spin torques (TSTs), have been proposed, but so far these TSTs have not been large enough to influence MTJ switching. Here we demonstrate significant TSTs in MTJs by generating large temperature gradients across ultrathin MgO tunnel barriers that considerably affect the switching fields of the MTJ. We attribute the origin of the TST to an asymmetry of the tunneling conductance across the zero-bias voltage of the MTJ. Remarkably, we estimate through magneto-Seebeck voltage measurements that the charge currents that would be generated due to the temperature gradient would give rise to STT that is a thousand times too small to account for the changes in switching fields that we observe.

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10

Sugii, Toshihiro, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Kouji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, and Chikako Yoshida. "Integration of STT-MRAMs for Embedded Cache Memories." Advances in Science and Technology 95 (October 2014): 146–49. http://dx.doi.org/10.4028/www.scientific.net/ast.95.146.

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We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration with the back-end-of-line (BEOL) process to replace conventional embedded SRAM cache memories. Our MRAM technology features a top-pinned, perpendicular magnetic tunnel junction (MTJ) and a highly reliable MTJ for a cache memory. We could obtain a higher density cache memory than that with conventional SRAMs with our STT-MRAMs, and leakage free characteristics, as well as unlimited write and read cycling times and 10-year time-dependent dielectric breakdown (TDDB) characteristics. They were integrated into Cu interconnects with 300 mm facilities. We also discuss variations in MTJ pattern sizes that are very important for memory applications from the viewpoint of high density embedded cache memories.

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ZHANG, YAOJUN, WUJIE WEN, and YIRAN CHEN. "STT-RAM CELL DESIGN CONSIDERING MTJ ASYMMETRIC SWITCHING." SPIN 02, no. 03 (September 2012): 1240007. http://dx.doi.org/10.1142/s2010324712400073.

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As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, nonvolatility, and good CMOS process compatibility. In this paper, we address the asymmetry in the write operations of STT-RAM cells: the mean and the deviation of the write latency for the switching from low- to high-resistance state is much longer or larger than that of the opposite direction. Some special design concerns, e.g., the data-dependent write reliability, are raised by this observation. We systematically analyze the root reasons for the asymmetric switching of MTJs, including the thermal-induced statistical MTJ magnetization process, the asymmetric biasing condition of NMOS transistors, and the device variations of both NMOS and MTJ. Their impacts on STT-RAM write operations were also investigated. At last, we explore the design spaces of different STT-RAM cell structures by considering the asymmetry of write operations.

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12

Zhang, Shubin, Peifang Dai, Ning Li, and Yanbo Chen. "A Radiation-hardened Triple Modular Redundancy Design Based on Spin-Transfer Torque Magnetic Tunnel Junction Devices." Applied Sciences 14, no. 3 (February 1, 2024): 1229. http://dx.doi.org/10.3390/app14031229.

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Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation.

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13

Lim, Hyein, Seungjun Lee, and Hyungsoon Shin. "A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation." Active and Passive Electronic Components 2016 (2016): 1–12. http://dx.doi.org/10.1155/2016/3858621.

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Spin-transfer torque-based magnetoresistive random access memory (STT-MRAM) is a promising candidate for universal memory that may replace traditional memory forms. It is expected to provide high-speed operation, scalability, low-power dissipation, and high endurance. MRAM switching technology has evolved from the field-induced magnetic switching (FIMS) technique to the spin-transfer torque (STT) switching technique. Additionally, material technology that induces perpendicular magnetic anisotropy (PMA) facilitates low-power operation through the reduction of the switching current density. In this paper, the modeling of magnetic tunnel junctions (MTJs) is reviewed. Modeling methods and models of MTJ characteristics are classified into two groups, macromodels and behavioral models, and the most important characteristics of MTJs, the voltage-dependent MTJ resistance and the switching behavior, are compared. To represent the voltage dependency of MTJ resistance, some models are based on physical mechanisms, such as Landau-Lifshitz-Gilbert (LLG) equation or voltage-dependent conductance. Some behavioral models are constructed by adding fitting parameters or introducing new physical parameters to represent the complex switching behavior of an MTJ over a wide range of input current conditions. Other models that are not based on physical mechanisms are implemented by simply fitting to experimental data.

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14

Sun, Zhenyu, Xiuyuan Bi, Hai Li, Weng-Fai Wong, and Xiaochun Zhu. "STT-RAM Cache Hierarchy With Multiretention MTJ Designs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 6 (June 2014): 1281–93. http://dx.doi.org/10.1109/tvlsi.2013.2267754.

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Monga, Kanika, Nitin Chaturvedi, and S. Gurunarayanan. "Energy-efficient data retention in D flip-flops using STT-MTJ." Circuit World 46, no. 4 (June 20, 2020): 229–41. http://dx.doi.org/10.1108/cw-09-2018-0073.

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Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

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Useinov, Niazbeck. "Tunnel magnetoresistance and spin transfer torque in magnetic tunnel junction with embedded nanoparticles." EPJ Web of Conferences 185 (2018): 01015. http://dx.doi.org/10.1051/epjconf/201818501015.

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The theoretical model of spin-dependent transport in magnetic tunnel junctions (MTJ) containing magnetic or non-magnetic nanoparticle is developed. The dependences of tunnel magnetoresistance (TMR) and in-plane component of spin transfer torque (STT) on the applied voltage for various sizes of nanoparticles of the order of the mean free path of the conduction electron are calculated. The calculation is performed in the approximation of the ballistic transport of conduction electrons through the insulating layers of the MTJ and the nanoparticles.

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Long, Jingwei, Qi Hu, Zhengping Yuan, Yunsen Zhang, Yue Xin, Jie Ren, Bowen Dong, et al. "Comparative Study of Temperature Impact in Spin-Torque Switched Perpendicular and Easy-Cone MTJs." Nanomaterials 13, no. 2 (January 13, 2023): 337. http://dx.doi.org/10.3390/nano13020337.

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The writing performance of the easy-cone magnetic tunnel junction (MTJ) and perpendicularly magnetized MTJ (pMTJ) under various temperatures was investigated based on the macrospin model. When the temperature is changed from 273 K to 373 K, the switching current density of the pMTJ changes by 56%, whereas this value is only 8% in the easy-cone MTJ. Similarly, the temperature-induced variation of the switching delay is more significant in the pMTJ. This indicates that the easy-cone MTJ has a more stable writing performance under temperature variations, resulting in a wider operating temperature range. In addition, these two types of MTJs exhibit opposite temperature dependence in the current overdrive and write error rate. In the easy cone MTJ, these two performance metrics will reduce as temperature is increased. The results shown in this work demonstrate that the easy-cone MTJ is more suitable to work at high temperatures compared with the pMTJ. Our work provides a guidance for the design of STT-MRAM that is required to operate at high temperatures.

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Bromberg, David M., Daniel H. Morris, Larry Pileggi, and Jian-Gang Zhu. "Novel STT-MTJ Device Enabling All-Metallic Logic Circuits." IEEE Transactions on Magnetics 48, no. 11 (November 2012): 3215–18. http://dx.doi.org/10.1109/tmag.2012.2197186.

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Zhang, Yaojun, Xiaobin Wang, Hai Li, and Yiran Chen. "STT-RAM Cell Optimization Considering MTJ and CMOS Variations." IEEE Transactions on Magnetics 47, no. 10 (October 2011): 2962–65. http://dx.doi.org/10.1109/tmag.2011.2158810.

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Wei, Jiaqi, Kaihua Cao, Hushan Cui, Kewen Shi, Wenlong Cai, Huisong Li, Yang Jing, Chao Zhao, and Weisheng Zhao. "All Perpendicular Spin Nano-Oscillators with Composite Free Layer." SPIN 09, no. 03 (May 8, 2019): 1940010. http://dx.doi.org/10.1142/s2010324719400101.

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Owing to improved thermal stability and scalability, materials with perpendicular magnetic anisotropy (PMA) are extremely attractive. The all perpendicular magnetic tunnel junction ([Formula: see text]-MTJ) devices are primarily devoted to spin transfer torque (STT)-induced switching and few works report their microwave emission. Here, we demonstrate the basic results of RF function in nanoscale [Formula: see text]-MTJ which has two different thickness free layers separated by atom-thick tungsten insertion. The ultrathin W spacer layer not only enables the two CoFeB free layers precess as a single layer but also greatly enhances the PMA which further induces high-emission frequency. The all perpendicular spin transfer torque nano-oscillator (STNO) exhibited high frequency (7.6[Formula: see text]GHz) and large current modulation capability of [Formula: see text] at moderate external magnetic field. Along with our previous work on STT switching utilizing the similar stack, such a multifunctional structure could bring low cost solutions to Internet of Things (IoT) network applications.

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Prakash, D. Venkata, Anjaiah Talamala, Mahesh K. Singh, and Y. Kuntam Yamini Devi. "Non-Volatile Logic Design Considerations for Energy Efficient Tolerant Variation." International Journal of Electrical and Electronics Research 10, no. 4 (December 30, 2022): 868–71. http://dx.doi.org/10.37391/ijeer.100419.

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Systems design for the non-volatile application must work on less energy or power. The spin-transfer torque-magnetic tunnel junction (STT-MTJ) devices added to the flip-flops which are regarded as non-volatile storage devices. Those are addresses to save the energy of that system stated by the nonvolatile logic. The changes during the production of STT-MTJ and CMOS transistors decrease the yield, which leads to overdesign as well as more energy consumption. The total processes of driver circuitry design for the tradeoffs for backup and restore performance. A new method called the novel method is introduced for flawless energy drivers for given results. The design for the backup time determination and to reduce the energy wastage are mentioned. To get an efficient output of 98% this approach needs to dissipate 5 times more energy than initially required. This method can dissipate the energy up to 26%. It also contains the nonvolatile flip-flop (NVFF) which has energy consumption more when it is used in the functional blocks.

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Nisar, Arshid, Seema Dhull, Brajesh Kumar Kaushik, and Sparsh Mittal. "High-performance voltage controlled multilevel MRAM cell." Semiconductor Science and Technology 36, no. 12 (November 10, 2021): 125013. http://dx.doi.org/10.1088/1361-6641/ac3187.

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Abstract In the recent past, spin-transfer torque (STT) and spin-orbit torque (SOT) based magnetic random access memories (MRAMs) have been studied for future energy efficient and non-volatile memory applications. Multilevel cell (MLC) design has emerged as one of the promising solutions to enhance the storage density of these MRAMs. However, the conventional MLC design adds a larger magnetic tunnel junction (MTJ) stack that makes it difficult to maintain low switching current and high speed. Moreover, it becomes very difficult to reduce the driver transistor size. This paper describes the application of voltage controlled magnetic anisotropy effect to design energy efficient and fast MLC MRAM cell. So far, this approach has been reported only in single-bit MTJ devices. In the proposed MLC the voltage control is able to reduce both SOT and STT switching currents. The results show that the voltage control in MLC enhances energy efficiency and switching speed by more than 80 times and 3 times, respectively, in comparison to conventional SOT based MLCs. The reduction in switching currents also achieves smaller transistor size and enhances area efficiency by 3.5% as compared to conventional SOT-MLC. The effect of different channel materials on SOT switching current has also been explored. Furthermore, the system level evaluation shows that voltage controlled MLC outperforms STT-MRAM and SOT-MRAM for designing cache memory.

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Garzón, Esteban, Marco Lanuzza, Ramiro Taco, and Sebastiano Strangio. "Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications." Electronics 10, no. 15 (July 22, 2021): 1756. http://dx.doi.org/10.3390/electronics10151756.

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Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%.

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Wang, Manman, and Yanfeng Jiang. "Compact model of nanometer STT-MTJ device with scale effect." AIP Advances 11, no. 2 (February 1, 2021): 025201. http://dx.doi.org/10.1063/9.0000049.

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Bi, Xiuyuan, Hai Li, and Xiaobin Wang. "STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence." IEEE Transactions on Magnetics 48, no. 11 (November 2012): 3821–24. http://dx.doi.org/10.1109/tmag.2012.2200469.

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Park, Jaeyoung. "Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications." Electronics 9, no. 9 (September 1, 2020): 1406. http://dx.doi.org/10.3390/electronics9091406.

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This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard CMOS flip-flop infrastructure for storing and restoring data onto MTJs for reducing the area. Furthermore, the proposed NVFFs re-use a write current, which is used for storing an MTJ, to write the other MTJ at a time, resulting in 50% storing energy reduction. To reduce the area further, the number of external terminals of an MTJ is reduced by shorting the shorting physical terminals. Removing a terminal using the proposed STT-Like SOT configuration results in fewer transistors to control. The proposed NVFF circuits are evaluated using a compact MTJ model targeting implementation in a 14-nm technology node. Analysis indicates that area overheads are only 10.3% and 6.9% compared to the conventional D flip-flop because three or two minimum-sized NMOS transistors are added for accessing MTJs. Compared to the best previously known NVFFs, the proposed NVFF has an improvement by a factor of 2–8 in terms of the area overhead.

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Liang, Yu-Pei, Shuo-Han Chen, Yuan-Hao Chang, Yun-Fei Liu, Hsin-Wen Wei, and Wei-Kuan Shih. "A cache consolidation design of MLC STT-RAM for energy efficiency enhancement on cyber-physical systems." ACM SIGAPP Applied Computing Review 21, no. 1 (March 2021): 37–49. http://dx.doi.org/10.1145/3477133.3477136.

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Owing to the energy-constraint nature of cyber-physical systems (CPS), energy efficiency has become a primary design consideration for CPS. On CPS, owing to the high leakage power issue of SRAM, the major portion of its energy consumption comes from static random-access memory (SRAM)-based processors. Recently, with the emerging and rapidly evolving nonvolatile Spin-Transfer Torque RAM (STT-RAM), STT-RAM is expected to replace SRAM within processors for enhancing the energy efficiency with its near-zero leakage power features. The advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to pack more cells with the same die area for achieving the memory density. However, the write disturbance issue of MLC STT-RAM prevents STT-RAM from properly resolving the energy efficiency of CPS. Although studies have been proposed to alleviate this issue, previous strategies could induce additional management overhead due to the use of counters or lead to frequent swap operations. Such an observation motivates us to propose an effective and simple strategy to combine direct and split cache mapping designs to enhance the energy efficiency of MLC STT-RAM. A series of experiments have been conducted on an open-source emulator with encouraging results.

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Hong, Yunshu, Yiyu Pan, and Zhongfu Xu. "Based on the comparison with other kinds of storage devices to predict the future development of STT-MRAM." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 197–204. http://dx.doi.org/10.54097/hset.v46i.7704.

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Now day with the development of technology, our electronic device is upgraded. Which will bring more data to storage. This causes the development of memory device. Now we already have SRAM flash memory are being widely used. But as the we use it for long time, the disadvantage of these memory device is shown, therefore, a new memory device --STT-MRAM are been created, which is we are going to introduce, we will show you how it basic structure which is MRAM work and the mechanism of the magnetic tunnel junction (the part it storage messages) and how spin electron influence the MTJ to make it more effective. Follow that we will list and make a comparison of the advantage of STT-MRAM and the disadvantage of flash memory, SRAM and DRAM to show the potential of the STT-MRAM. After mentioned about the benefit of STT-MRAM, we will mention about the disadvantages of it such as hard to maintain high thermal stability barrier. We will give the possible solutions follow that. This text intended to introduce this new type of memory device-STT-MRAM and show the potential of it in the future.

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Sanchez Hazen, D., B. M. S. Teixeira, D. Salomoni, S. Auffret, L. Vila, R. C. Sousa, I. L. Prejbeanu, L. D. Buda-Prejbeanu, and B. Dieny. "Real time investigation of double magnetic tunnel junction with a switchable assistance layer for high efficiency STT-MRAM." APL Materials 10, no. 3 (March 1, 2022): 031104. http://dx.doi.org/10.1063/5.0080335.

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This work reports experimental confirmation of the working principles of a double magnetic tunnel junction (DMTJ) to achieve highly efficient spin-transfer-torque (STT) switching. This concept uses a magnetically switchable assistance layer (ASL) acting as a top perpendicular spin polarizer. The STT-induced switching dynamics were described by macrospin simulations, while the magnetic and electrical properties of the devices were investigated in switching experiments. The reversal dynamics of the storage layer/ASL coupled system were validated by time-resolved measurements of the device resistance during write operation, confirming that the storage layer is subjected to additive STT contributions both from the reference layer and the ASL throughout its parallel-to-antiparallel and antiparallel-to-parallel transitions. The STT efficiency of the ASL-DMTJ was compared to that of single MTJ stacks comprising the same storage layer and no assistance layer. The figure of merit ∆/Ic (stability/critical current) was found to nearly double in devices of 80 and 100 nm diameter, with a smaller 30% increase obtained for 50 nm diameter cells.

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Deng, Erya, Wang Kang, Yue Zhang, Jacques-Olivier Klein, Claude Chappert, and Weisheng Zhao. "Design Optimization and Analysis of Multicontext STT-MTJ/CMOS Logic Circuits." IEEE Transactions on Nanotechnology 14, no. 1 (January 2015): 169–77. http://dx.doi.org/10.1109/tnano.2014.2375205.

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Wang, Manman, Yuhai Yuan, and Yanfeng Jiang. "Realization of Artificial Neurons and Synapses Based on STDP Designed by an MTJ Device." Micromachines 14, no. 10 (September 23, 2023): 1820. http://dx.doi.org/10.3390/mi14101820.

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As the third-generation neural network, the spiking neural network (SNN) has become one of the most promising neuromorphic computing paradigms to mimic brain neural networks over the past decade. The SNN shows many advantages in performing classification and recognition tasks in the artificial intelligence field. In the SNN, the communication between the pre-synapse neuron (PRE) and the post-synapse neuron (POST) is conducted by the synapse. The corresponding synaptic weights are dependent on both the spiking patterns of the PRE and the POST, which are updated by spike-timing-dependent plasticity (STDP) rules. The emergence and growing maturity of spintronic devices present a new approach for constructing the SNN. In the paper, a novel SNN is proposed, in which both the synapse and the neuron are mimicked with the spin transfer torque magnetic tunnel junction (STT-MTJ) device. The synaptic weight is presented by the conductance of the MTJ device. The mapping of the probabilistic spiking nature of the neuron to the stochastic switching behavior of the MTJ with thermal noise is presented based on the stochastic Landau–Lifshitz–Gilbert (LLG) equation. In this way, a simplified SNN is mimicked with the MTJ device. The function of the mimicked SNN is verified by a handwritten digit recognition task based on the MINIST database.

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32

Lim, Hyein, Sora Ahn, Miryeon Kim, Seungjun Lee, and Hyungsoon Shin. "A New Circuit Model for Spin-Torque Oscillator Including Perpendicular Torque of Magnetic Tunnel Junction." Advances in Condensed Matter Physics 2013 (2013): 1–6. http://dx.doi.org/10.1155/2013/169312.

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Spin-torque oscillator (STO) is a promising new technology for the future RF oscillators, which is based on the spin-transfer torque (STT) effect in magnetic multilayered nanostructure. It is expected to provide a larger tunability, smaller size, lower power consumption, and higher level of integration than the semiconductor-based oscillators. In our previous work, a circuit-level model of the giant magnetoresistance (GMR) STO was proposed. In this paper, we present a physics-based circuit-level model of the magnetic tunnel junction (MTJ)-based STO. MTJ-STO model includes the effect of perpendicular torque that has been ignored in the GMR-STO model. The variations of three major characteristics, generation frequency, mean oscillation power, and generation linewidth of an MTJ-STO with respect to the amount of perpendicular torque, are investigated, and the results are applied to our model. The operation of the model was verified by HSPICE simulation, and the results show an excellent agreement with the experimental data. The results also prove that a full circuit-level simulation with MJT-STO devices can be made with our proposed model.

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Choi, Gwang Hui, and Taehui Na. "Analysis of State-of-the-Art Spin-Transfer-Torque Nonvolatile Flip-Flops Considering Restore Yield in the Near/Sub-Threshold Voltage Region." Electronics 9, no. 12 (December 11, 2020): 2118. http://dx.doi.org/10.3390/electronics9122118.

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Recently, the leakage power consumption of Internet of Things (IoT) devices has become a main issue to be tackled, due to the fact that the scaling of process technology increases the leakage current in the IoT devices having limited battery capacity, resulting in the reduction of battery lifetime. The most effective method to extend the battery lifetime is to shut-off the device during standby mode. For this reason, spin-transfer-torque magnetic-tunnel-junction (STT-MTJ) based nonvolatile flip-flop (NVFF) is being considered as a strong candidate to store the computing data. Since there is a risk that the MTJ resistance may change during the read operation (i.e., the read disturbance problem), NVFF should consider the read disturbance problem to satisfy reliable data restoration. To date, several NVFFs have been proposed. Even though they satisfy the target restore yield of 4σ, most of them do not take the read disturbance into account. Furthermore, several recently proposed NVFFs which focus on the offset-cancellation technique to improve the restore yield have obvious limitation with decreasing the supply voltage (VDD), because the offset-cancellation technique uses switch operation in the critical path that can exacerbate the restore yield in the near/sub-threshold region. In this regard, this paper analyzes state-of-the-art STT-MTJ based NVFFs with respect to the voltage region and provides insight that a simple circuit having no offset-cancellation technique could achieve a better restore yield in the near/sub-threshold voltage region. Monte–Carlo HSPICE simulation results, using industry-compatible 28 nm model parameters, show that in case of VDD of 0.6 V, complex NVFF circuits having offset tolerance characteristic have a better restore yield, whereas in case of VDD of 0.4 V with sizing up strategy, a simple NVFF circuit having no offset tolerance characteristic has a better restore yield.

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De Rose, Raffaele, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, and Marco Lanuzza. "STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing." Solid-State Electronics 184 (October 2021): 108065. http://dx.doi.org/10.1016/j.sse.2021.108065.

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Tripathi, Sandeep, Sudhanshu Choudhary, and Prasanna Kumar Misra. "A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications." IEEE Transactions on Electron Devices 69, no. 3 (March 2022): 1058–64. http://dx.doi.org/10.1109/ted.2022.3140407.

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Perach, Ben, and shahar kvatinsky. "An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 11 (November 2019): 2473–84. http://dx.doi.org/10.1109/tvlsi.2019.2927816.

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Pathak, Sachin, Jongin Cha, Kangwook Jo, Hongil Yoon, and Jongill Hong. "Fast and efficient STT switching in MTJ using additional transient pulse current." Applied Physics Letters 110, no. 23 (June 5, 2017): 232401. http://dx.doi.org/10.1063/1.4985129.

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Garg, Jyoti, and Subodh Wariya. "Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ." International Journal of Computing and Digital Systems 14, no. 1 (July 1, 2023): 107–15. http://dx.doi.org/10.12785/ijcds/140110.

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Wasef, Shaik, and Hossein Fariborzi. "Theoretical Study of Field-Free Switching in PMA-MTJ Using Combined Injection of STT and SOT Currents." Micromachines 12, no. 11 (October 31, 2021): 1345. http://dx.doi.org/10.3390/mi12111345.

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Field-free switching in perpendicular magnetic tunnel junctions (P-MTJs) can be achieved by combined injection of spin-transfer torque (STT) and spin-orbit torque (SOT) currents. In this paper, we derived the relationship between the STT and SOT critical current densities under combined injection. We included the damping–like torque (DLT) and field-like torque (FLT) components of both the STT and SOT. The results were derived when the ratio of the FLT to the DLT component of the SOT was positive. We observed that the relationship between the critical SOT and STT current densities depended on the damping constant and the magnitude of the FLT component of the STT and the SOT current. We also noted that, unlike the FLT component of SOT, the magnitude and sign of the FLT component of STT did not have a significant effect on the STT and SOT current densities required for switching. The derived results agreed well with micromagnetic simulations. The results of this work can serve as a guideline to model and develop spintronic devices using a combined injection of STT and SOT currents.

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Polley, Debanjan, Akshay Pattabi, Jyotirmoy Chatterjee, Sucheta Mondal, Kaushalya Jhuria, Hanuman Singh, Jon Gorchon, and Jeffrey Bokor. "Progress toward picosecond on-chip magnetic memory." Applied Physics Letters 120, no. 14 (April 4, 2022): 140501. http://dx.doi.org/10.1063/5.0083897.

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We offer a perspective on the prospects of ultrafast spintronics and opto-magnetism as a pathway to high-performance, energy-efficient, and non-volatile embedded memory in digital integrated circuit applications. Conventional spintronic devices, such as spin-transfer-torque magnetic-resistive random-access memory (STT-MRAM) and spin–orbit torque MRAM, are promising due to their non-volatility, energy-efficiency, and high endurance. STT-MRAMs are now entering into the commercial market; however, they are limited in write speed to the nanosecond timescale. Improvement in the write speed of spintronic devices can significantly increase their usefulness as viable alternatives to the existing CMOS-based devices. In this article, we discuss recent studies that advance the field of ultrafast spintronics and opto-magnetism. An optimized ferromagnet–ferrimagnet exchange-coupled magnetic stack, which can serve as the free layer of a magnetic tunnel junction (MTJ), can be optically switched in as fast as ∼3 ps. Integration of ultrafast magnetic switching of a similar stack into an MTJ device has enabled electrical readout of the switched state using a relatively larger tunneling magnetoresistance ratio. Purely electronic ultrafast spin–orbit torque induced switching of a ferromagnet has been demonstrated using ∼6 ps long charge current pulses. We conclude our Perspective by discussing some of the challenges that remain to be addressed to accelerate ultrafast spintronics technologies toward practical implementation in high-performance digital information processing systems.

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DAS, JAYITA, SYED M. ALAM, and SANJUKTA BHANJA. "RECENT TRENDS IN SPINTRONICS-BASED NANOMAGNETIC LOGIC." SPIN 04, no. 03 (September 2014): 1450004. http://dx.doi.org/10.1142/s2010324714500040.

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With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy ( Ni 80 Fe 14 Mo 5 X 1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.

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Barla, Prashanth, Vinod Kumar Joshi, and Somashekara Bhat. "A Novel Auto-Write-Stopping Circuit for SHE + STT-MTJ/CMOS Hybrid ALU." IEEE Transactions on Electron Devices 69, no. 4 (April 2022): 1683–90. http://dx.doi.org/10.1109/ted.2022.3145331.

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Pan, Guangchen, Ali Karymy, Pingping Yu, and Yanfeng Jiang. "Novel Low Noise Amplifier for Neural Signals Based on STT-MTJ Spintronic Device." IEEE Access 7 (2019): 145641–50. http://dx.doi.org/10.1109/access.2019.2945036.

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Zhang, Li, Hualian Tang, Beilei Xu, Yiqi Zhuang, and Junlin Bao. "A High Reliability Sense Amplifier for Computing In-Memory with STT-MRAM." SPIN 10, no. 02 (January 31, 2020): 2040001. http://dx.doi.org/10.1142/s2010324720400019.

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In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40[Formula: see text]nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.

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45

Harnsoongnoen, Supakorn, N. Phaengpha, S. Ritjaroenwattu, U. Charoen-In, and Apirat Siritaratiwat. "Joule Heating and Peltier Effects in Thermoelectric Spin-Transfer Torque Mram Devices Using Finite Element Modeling." Advanced Materials Research 931-932 (May 2014): 989–93. http://dx.doi.org/10.4028/www.scientific.net/amr.931-932.989.

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This paper reports the Joule heating and Peltier effects in thermoelectric spin-transfer torque MRAMs (TSTT-MRAMs). The simulation was undertaken based on the current-induced magnetization switching at the MgO/CoFe magnetic tunnel junction. Thermal and heat flux distributions of the TSTT-MRAM cells were simulated and analyzed using finite-element modeling. The Joule heating and Peltier effects lead to the increases in the temperature and heat flux distributions at the magnetic tunnel junction (MTJ) as well as the thermoelectric module. The maximum temperature of Peltier effect is higher than Joule heating effect when voltage amplitude below 0.77V. Some practical data for the STT-MRAM were also reported.

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Garzón, Esteban, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, and Marco Lanuzza. "Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs." Solid-State Electronics 194 (August 2022): 108315. http://dx.doi.org/10.1016/j.sse.2022.108315.

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Sun, Hongbin, Chuanyin Liu, Tai Min, Nanning Zheng, and Tong Zhang. "Architectural Exploration to Enable Sufficient MTJ Device Write Margin for STT-RAM Based Cache." IEEE Transactions on Magnetics 48, no. 8 (August 2012): 2346–51. http://dx.doi.org/10.1109/tmag.2012.2193589.

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Lv, Hua, Joao Fidalgo, Thomas Kampfe, Juergen Langer, Jerzy Wrona, Berthold Ocker, Paulo P. Freitas, and Susana Cardoso. "Seebeck effect and Joule heating in CoFeB/MgO/CoFeB-based perpendicular magnetic tunnel junctions with low resistance area product." Journal of Physics D: Applied Physics 55, no. 26 (April 8, 2022): 265302. http://dx.doi.org/10.1088/1361-6463/ac5e8a.

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Abstract Perpendicular magnetic tunnel junctions (p-MTJs) have attracted great interest due to their excellent performance in spin-transfer-torque magnetic random access memories (STT-MRAMs). Here, the resistance states can be manipulated by an applied current in the order of 109–1010 A m−2, yet the appearance of a heating influence must be understood. In this work, we systematically study the Seebeck effect in nano scale p-MTJs induced due to Joule heating by the tunneling current. The CoFeB/MgO/CoFeB-based p-MTJs were nanofabricated and the current-induced switching was characterized. We find a sign change of the thermovoltage (ΔV) between AP (positive) and P (negative) states, indicating a significant dependence of the Seebeck effect on the magnetic state of the p-MTJ. The temperature distribution in the stack was simulated, by which the Seebeck coefficient (S) and the tunnel magneto-Seebeck ratio were calculated. Our further study indicates that the thermal STT can reduce the switching currents, showing the possibility to re-use this dissipative heating energy. To improve the efficiency of the energy re-use, a method is proposed through the materials optimization of the non-magnetic layers but still retaining high tunneling magnetoresistance effect. Our study shows that the magneto-Seebeck effect plays an important role in the p-MTJs, which can be crucial and must be considered in the design of the high performance p-STT-MRAMs and thermal-assisted MRAMs.

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Pak, Murat, Wesley Zanders, Patrick Wong, and Sandip Halder. "Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars." Micro and Nano Engineering 10 (April 2021): 100082. http://dx.doi.org/10.1016/j.mne.2021.100082.

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Barla, Prashanth, Vinod Kumar Joshi, and Somashekara Bhat. "Design and evaluation of hybrid SHE+STT-MTJ/CMOS full adder based on LIM architecture." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (September 1, 2021): 012015. http://dx.doi.org/10.1088/1757-899x/1187/1/012015.

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Abstract This work aimed at developing a full adder using hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) based on the logic-in-memory architecture (LIM). LIM has emerged as the most promising alternative to the standard von-Neumann architecture in the impeding post-CMOS era. Performance of the hybrid full adder is evaluated in terms of power, delay, power delay product (PDP), and device count. These results are compared with the existing double pass transistor logic-based clocked CMOS (DPTL-C2MOS) full adder. Further, Monte-Carlo simulations on both variants of full adders were conducted to study their performance. Simulation results reveal that the hybrid full adder is superior to the DPTL-C2MOS full adder and can be used in low power and high throughput computing systems in the near future.

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Journal articles on the topic 'STT-MTJ'

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