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Journal articles on the topic 'Stencil printing'

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Published: 4 June 2021
Last updated: 6 February 2022

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1

Lee, Yong‐Won, Keun‐Soo Kim, and Katsuaki Suganuma. "The behaviour of solder pastes in stencil printing with electropolishing process." Soldering & Surface Mount Technology 25, no. 3 (June 21, 2013): 164–74. http://dx.doi.org/10.1108/ssmt-12-2012-0027.

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PurposeThe purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.Design/methodology/approachDuring the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.FindingsThe results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.Originality/valueDue to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.
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2

Vallabhajosyula, Phani. "Stencil Print solutions for Advance Packaging Applications." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000646–51. http://dx.doi.org/10.4071/isom-2017-poster1_124.

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Abstract This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging. As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high-performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um–40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package. Cavity technology can be an effective solution in reducing the total assembled PCB thickness (Z-height), most importantly, on designs utilizing taller - stacked devices. Traditionally, dipping process or dispensing process was used to deposit solder paste, flux, or glue on uneven surfaces. However, this takes a longer time when compared to printing using a stencil printer. Reservoir printing using a stencil printer has greater potential in such application. Extensive work has been done in the past to print glue, solder paste and/or flux into cavities using reservoir printing. This paper focuses on printing solder paste into multiple cavities (stencil pockets) with depths ranging from 355 microns to 450 microns, and with varying cavity size, wall angles and various stencil thicknesses ranging from 100 microns to 150 microns. Apertures varying in area ratio were placed in these cavities and experiments were conducted to analyze the print performance of the stencils. As the size of the components and boards/substrates gets smaller - closer placement of components to the cavity (stencil pocket) walls needed to be assessed as well. These applications, the associated stencil design and print results were discussed in detail in this paper.
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3

Wickström, Henrika, Rajesh Koppolu, Ermei Mäkilä, Martti Toivakka, and Niklas Sandler. "Stencil Printing—A Novel Manufacturing Platform for Orodispersible Discs." Pharmaceutics 12, no. 1 (January 1, 2020): 33. http://dx.doi.org/10.3390/pharmaceutics12010033.

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Stencil printing is a commonly used printing method, but it has not previously been used for production of pharmaceuticals. The aim of this study was to explore whether stencil printing of drug containing polymer inks could be used to manufacture flexible dosage forms with acceptable mass and content uniformity. Formulation development was supported by physicochemical characterization of the inks and final dosage forms. The printing of haloperidol (HAL) discs was performed using a prototype stencil printer. Ink development comprised of investigations of ink rheology in combination with printability assessment. The results show that stencil printing can be used to manufacture HAL doses in the therapeutic treatment range for 6–17 year-old children. The therapeutic HAL dose was achieved for the discs consisting of 16% of hydroxypropyl methylcellulose (HPMC) and 1% of lactic acid (LA). The formulation pH remained above pH 4 and the results imply that the drug was amorphous. Linear dose escalation was achieved by an increase in aperture area of the print pattern, while keeping the stencil thickness fixed. Disintegration times of the orodispersible discs printed with 250 and 500 µm thick stencils were below 30 s. In conclusion, stencil printing shows potential as a manufacturing method of pharmaceuticals.
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4

YAMADA, Hiromichi. "Stencil Printing Ink." Journal of the Japan Society of Colour Material 70, no. 11 (1997): 751–56. http://dx.doi.org/10.4011/shikizai1937.70.751.

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5

Yu, JiangYou, Le Cao, Hao Fu, and Jun Guo. "A method for optimizing stencil cleaning time in solder paste printing process." Soldering & Surface Mount Technology 31, no. 4 (September 2, 2019): 233–39. http://dx.doi.org/10.1108/ssmt-10-2018-0037.

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PurposeStencil cleaning is an important operation in solder paste printing process. Frequent cleaning may interrupt printing process and increase idle time, as well as loss for performing cleaning. This paper aims to propose a method to optimize the stencil cleaning time and reduce unnecessary cleaning operations and losses.Design/methodology/approachThis paper uses a discrete-time, discrete-state homogeneous Markov chain to model the stencil printing performance degradation process, and the quality loss during the stencil printing process is estimated based on this degradation model. A stencil cleaning decision model based on renewal reward theorem is established, and the optimal cleaning time is obtained through a balance between quality loss and the loss on idle time.FindingsA stencil cleaning decision model for solder paste printing is established, and numerical simulation results show that there exists an optimal stencil cleaning time which minimizes the long-term loss.Originality/valueStencil cleaning control is very important for solder paste printing. However, there are very few studies focusing on stencil cleaning control. This research contributes to developing a model to optimize the stencil cleaning time in solder paste printing process.
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6

Pei-Lim, Sze, Kenneth Thum, and Andy Mackie. "Challenges in Fine Feature Solder Paste Printing for SiP Applications." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000245–49. http://dx.doi.org/10.4071/isom-2016-wp12.

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Abstract The rapid development in the Internet of Things (IoT) has seen a surge in demand for System-in-Package (SiP), which is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller components and greater density. 01005 passive components are being used in most of the current SiP technology and the industry is looking at utilizing 008004 passive components for the next generation SiP. The stencil aperture design for 008004 will likely be about half of 01005, and a finer powder size solder paste will be used. The stencil design, stencil thickness, and the types of stencils being used, are crucial in achieving good solder paste printing performance. Due to the need of squeezing more components into a SiP, the gap between neighboring pads can be as close as 50μm; hence, it is crucial to avoid solder bridging for such applications. This paper will discuss the challenges in achieving consistent solder paste printing performance for fine feature applications using Type 6 (5–15μm) powder size solder paste. Test results with different stencil designs, printing parameters, and different solder pastes will be discussed in detail.
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7

Sriperumbudur, Sai Srinivas, Michael Meilunas, and Martin Anselm. "Solder paste volume effects on assembly yield and reliability for bottom terminated components." Soldering & Surface Mount Technology 29, no. 2 (April 3, 2017): 99–109. http://dx.doi.org/10.1108/ssmt-05-2016-0010.

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Purpose Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations. Design/methodology/approach Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations. Findings Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling. Originality/value Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.
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8

W. Kay, Robert, Gerard Cummins, Thomas Krebs, Richard Lathrop, Eitan Abraham, and Marc Desmulliez. "Statistical analysis of stencil technology for wafer-level bumping." Soldering & Surface Mount Technology 26, no. 2 (April 1, 2014): 71–78. http://dx.doi.org/10.1108/ssmt-07-2013-0017.

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Purpose – Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues. Design/methodology/approach – In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types. Findings – Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5. Originality/value – Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.
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9

Whitmore, Mark, and Clive Ashmore. "Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000502–8. http://dx.doi.org/10.4071/isom-2011-wa2-paper2.

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As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.
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10

Vallabhajosyula, Phani. "Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–18. http://dx.doi.org/10.4071/2017dpc-poster_vallabhajosyula.

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Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.
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11

Kenny, Stephen, Sven Lamprecht, Kai Matejat, and Bernd Roelfs. "Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 000671–707. http://dx.doi.org/10.4071/2010dpc-ta31.

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Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.
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Whitmore, Mark, and Jeff Schake. "The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000667–74. http://dx.doi.org/10.4071/isom-2016-thp55.

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Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components. In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.
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Huang, Chien-Yi. "Applying the Taguchi parametric design to optimize the solder paste printing process and the quality loss function to define the specifications." Soldering & Surface Mount Technology 30, no. 4 (September 3, 2018): 217–26. http://dx.doi.org/10.1108/ssmt-03-2017-0010.

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Purpose This research aims to study the stencil printing process of the quad flat package (QFP) component with a pin pitch of 0.4 mm. After the optimization of the printing process, the desired inspection specification is determined to reduce the expected total process loss. Design/methodology/approach Static Taguchi parametric design is applied while considering the noise factors possibly affecting the printing quality in the production environment. The Taguchi quality loss function model is then proposed to evaluate the two types of inspection strategies. Findings The optimal parameter-level treatment for the solder paste printing process includes a squeegee pressure of 11 kg, a stencil snap-off of 0.14 mm, a cleaning frequency of the stencil once per printing and using an air gun after stencil wiping. The optimal upper and lower specification limits are 119.8 µm and 110.3 µm, respectively. Originality/value Noise factors in the production environment are considered to determine the optimal printing process. For specific components, the specification is established as a basis for subsequent processes or reworks.
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Chunxian Zou, Ling, Milos Dusek, Martin Wickham, and Christopher Hunt. "Fine pitch stencil printing using enclosed printing systems." Soldering & Surface Mount Technology 15, no. 1 (April 2003): 43–49. http://dx.doi.org/10.1108/09540910310455725.

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15

Krammer, Oliver, László Jakab, Balazs Illes, David Bušek, and Ivana Beshajová Pelikánová. "Investigating the attack angle of squeegees with different geometries." Soldering & Surface Mount Technology 30, no. 2 (April 3, 2018): 112–17. http://dx.doi.org/10.1108/ssmt-09-2017-0023.

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Purpose The attack angle of stencil printing squeegees with different geometries was analysed using finite element modelling. Design/methodology/approach A finite element model (FEM) was developed to determine the attack angle during the stencil printing. The material properties of the squeegee were included in the model according to the parameters of steel AISI 4340, and the model was validated by experimental measurements. Two geometric parameters were investigated; two different unloaded angles (45° and 60°) and four overhang sizes of the squeegee (6, 15, 20 and 25 mm). Findings It was found that the deflection of the blade is nearly homogenous along the length of the squeegee. This implies that the attack angle does not change significantly along the squeegee length. The results showed significant differences between the initial and the attack angle. For example, the angle of the squeegee with 15 mm overhang size and with 60° initial angle decreased by more than 5° for a specific squeegee force of 0.3 N/mm; resulting in an attack angle of 53.4°. Originality/value The attack angle during the printing is considerably lower than the initial angle as a result of the printing force. The papers, which were dealing with the numerical modelling of the stencil printing presumed that the squeegees were having their initial angle. This could have led to invalid numerical results. Therefore, we decided to investigate the attack angle during stencil printing for squeegees with different initial geometries to enhance the numerical modelling of stencil printing.
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Whitmore, Mark, Jeff Schake, and Clive Ashmore. "Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000569–73. http://dx.doi.org/10.4071/isom-2013-wa54.

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With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage. In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.
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Asghar, Rafiq, Faisal Rehman, Ali Aman, Kashif Iqbal, and Agha Ali Nawaz. "Defect minimization and process improvement in SMT lead-free solder paste printing: a comparative study." Soldering & Surface Mount Technology 32, no. 1 (September 19, 2019): 1–9. http://dx.doi.org/10.1108/ssmt-05-2019-0019.

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Purpose The purpose of this paper is to investigate and minimize the printing-related defects in the surface mount assembly (SMA) process. Design/methodology/approach This paper uses an experimental approach to explore process parameter and printing defects during the SMA process. Increasing printing performance, various practices of solder paste (Ag3.0/Cu0.5/Sn) storage and handling are suggested. Lopsided paste problem is studied by varying squeegee pressure and the results are presented. Unfilled pads problems are observed for ball grid array (BGA) and quad flat package (QFP) which is mitigated by proper force tuning. In this paper, a comparative study is conducted which evaluates the manifestation of printing offset due to low-grade stencil. The input/output (I/O) boards were oxidized when the relative humidity was maintained beyond 70 per cent for more than 8 h. This pad oxidation problem is overcome by proper printed circuit board (PCB) handling procedures. When the unoptimized line is used, the paste wedged in the stencil and influences the performance of the screen printer, for this reason, an optimized line is proposed that minimize the printing defects. Findings The key findings are as follows: in the SMA process, printing quality is directly associated with solder paste quality. Experimentally, it is observed that a considerable variance in solder deposition occurred when the front and rear squeegee have different configurations. High-grade and unsoiled stencil results in superior paste deposition and less distinction. Insufficient solder paste and bridge problems also occur in printing when PCB pads are oxidized. Optimized line resolves solder paste clog issues, associated with stencil’s aperture. The cooling arrangement on the conveyor, after reflow, explicates hot jig problem. Control environmental conditions minimized static charges and printing defects. Originality/value The preceding studies emphasis mostly on the squeegee pressure, while other important parameters are not completely investigated. Moreover, it is very imperative to concurrently measure all parameters while varying the environmental conditions. This study highlights and provides an experimental approach to various PCB printing defects, and a comparative study has been conducted that concurrently measure all process parameters.
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Aravamudhan, Srinivasa, Daryl Santos, Gerald Pham-Van-Diep, and Frank Andres. "Characterization of the Solder Paste Release From Small Stencil Apertures in the Stencil Printing Process." Journal of Electronic Packaging 127, no. 3 (December 10, 2004): 340–52. http://dx.doi.org/10.1115/1.1938208.

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Stencil printing is a critical first step in surface mount assembly. However, its robustness can be called into question because of the fact that about 50% or more of the defects found in the assembly of printed circuit boards (PCBs) are attributed to stencil printing 1. Manufacturing techniques for the assembly of certain flip chips, chip scale packages, 0201s, and fine pitch ball grid arrays are testing the limits of current stencil printing capabilities. This paper focuses on understanding the release of solder paste from the stencil, based on experimental and modeling approaches. The primary goal of the study is to characterize the performance of various aperture sizes and geometries based on release efficiencies and to compare them to predictions. The resulting model validation helps us better understand the print process for small features and offers options for increasing print yields. The study is divided into two phases. The first phase examines the release performance of various solder pastes from a variety of aperture sizes and geometries. The focus of this study is a comparison of square versus circular apertures when the nominal volume of paste to be deposited is kept constant. The second phase consists of developing a model that predicts paste-release efficiencies from small apertures and validating the model with experimental results.
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Weise, Thomas, and Raymond Chiong. "A Novel Extremal Optimization Approach for the Template Design Problem." International Journal of Organizational and Collective Intelligence 2, no. 2 (April 2011): 1–16. http://dx.doi.org/10.4018/joci.2011040101.

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This paper presents a novel algorithm based on extremal dynamics for tackling the template design problem, a constrained optimization problem that originated in the printing industry. The template design problem involves printing several variations of a design onto one or more stencil sheets, where the aims are to minimize the number of stencils as well as the overproduction of prints of a particular design. In this paper, the authors introduce several search operators to be used in conjunction with the proposed algorithm. Different combinations of these search operators are tested via extensive numerical experiments. The solutions indicate that the algorithm is a feasible approach for template design optimization. In particular, hybridizing it with a deterministic local search has proven to be very effective.
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Krammer, Oliver, Benjámin Gyarmati, András Szilágyi, Richárd Storcz, László Jakab, Balázs Illés, Attila Géczy, and Karel Dušek. "Investigating the thixotropic behaviour of Type 4 solder paste during stencil printing." Soldering & Surface Mount Technology 29, no. 1 (February 6, 2017): 10–14. http://dx.doi.org/10.1108/ssmt-10-2016-0022.

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Purpose A measurement method has been developed to reveal the viscosity change of solder pastes during stencil printing. This paper aimed to investigate thixotropic behaviour, the viscosity change of a lead-free solder paste (Type 4). Design/methodology/approach The viscosity change of the solder paste during stencil printing cycles was characterised in such a way that the time-gap between the printing cycles was modelled with a rest period between every rheological measurement. This period was set as 15, 30 and 60 s during the research. The Cross model was fitted to the measurement results, and the η0 parameter was used to characterise the viscosity change. The number of printing cycles necessary for reaching a stationary state in viscosity was determined for various rest periods. Findings It was found that the decrease in zero-shear viscosity is significant (25 per cent) in the first cycles, and it starts to become stationary at the sixth-seventh cycles. This means a printing process can provide the appropriate deposits only after the 7th cycle with the investigated Type 4 solder paste. Originality/value Time-dependent rheological behaviour of solder pastes was studied in the literature, but only the viscosity change over continuous time at constant shear rates was examined. The time-gap between stencil printing cycles was not considered, and thixotropic behaviour of solder pastes was also neglected. Therefore, the authors developed a measurement set which is able to model the effect of time-gap between printing cycles on the viscosity change of solder pastes.
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Kenny, Stephen, Kai Matejat, Sven Lamprecht, and Olivier Mann. "Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000729–34. http://dx.doi.org/10.4071/isom-2012-wa63.

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Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications. This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow. Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues. The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump. Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.
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Briggs, Ed. "Optimal SMT Electronics Assembly Guidelines for Stencil Printing." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000126–34. http://dx.doi.org/10.4071/isom-2015-tp46.

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The continuing miniaturization of personal electronics devices, such as mobile phones, personal music devices, and personal computing devices has driven the need for increasingly smaller active and passive electrical components. Not too long ago, 0402 (40 × 20mils) passives were seen as the ultimate in miniaturization, but recently 0201 and now 01005 passives have arrived, with predictions of even smaller sizes to come. For active components, the 30mil CSP (a chip-scale package with the solder balls on 30mil/0.75mm centers) has virtually become a requirement for enabling the many features required in modern portable electronics devices. This miniaturization trend, occurring simultaneously with the conversion to RoHS-compliant lead-free assembly, has put a considerable strain on the electronics assembly industry. This paper will discuss guidelines to optimize the electronics assembly process focusing primarily on stencil printing. With a smaller process window, each variable in the process contributes to the overall success of the assembly. Simple contributions such as storage and handling of solder paste can make or break a printing process. Many solder defects (some say 60–70%) can be attributed to the printing process. Therefore, stencil printing set-up is discussed, as well as solder paste measurement metrics, to determine the potential for success and assure a reliable solder joint.
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Sahay, C., L. M. Head, R. Shereen, P. Dujari, J. H. Constable, and G. Westby. "Study of Print Release Process in Solder Paste Printing." Journal of Electronic Packaging 117, no. 3 (September 1, 1995): 230–34. http://dx.doi.org/10.1115/1.2792097.

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Solder paste printing is central to the mass reflow soldering process for surface mount technology. The miniaturization of components has put an increased demand on the printing process and requires it to successfully print 75 μm-100 μm(3 to 4 mil) wide apertures. The amount of solder paste deposited is a matter of concern. This study presents results from experiments on printing with apertures having circular, rectangular, square and triangular geometries. The ratio of the printed volume to the aperture volume has been used as a definition of print quality. It was observed that acceptable prints were obtained when the ratio of aperture area to the aperture wall area was more than 0.8. A simple analytical model is also presented for the release of solder paste as the stencil separates from the substrate board assuming that the apertures were filled. The solder is currently treated as a single phase material with Newtonian behavior. The motion of solder paste in the stencil aperture is modelled as the developing viscous flow with velocity boundary layers developing along the walls. The shear strength of the paste is used to determine the area sticking to the wall, thus making it possible to get an estimate of the print quality. The model incorporates the effect of paste properties like viscosity, density, tack and shear strength, and other process variables like aperture dimensions and separation (lift off) velocities between the stencil and the board in predicting the print quality. The model predicts the effect of shear to tack strength of the paste, stencil thickness, and the ratio of aperture to wall area ratio on print quality.
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24

Shorina, O., and J. Müller. "Improvement of ampacity of LTCC conductors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (September 1, 2012): 000385–87. http://dx.doi.org/10.4071/cicmt-2012-wa47.

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Improvement of the current load-carrying capacity can be achieved by combining different technologies in Low Temperature Cofired Ceramics (LTCC). Screen and stencil printing, full tape thickness features (FTTF) and embossing in LTCC were investigated. Silver paste conductors with 80 – 200 μm line width are included in the study. The structures on the test substrates are fed with an increasing current until the surface reaches an equilibrium temperature of 100°C measured by an infrared camera. 200 μm lines created by screen printing and stencil printing are able to bear 4.3 A and 14 A, respectively. For the FTTF conductor with a thickness of 190 μm the estimated maximum current is about 30 A and for the embossed conductor (thickness approx. 125μm) about 20 A. FTTF allowed the highest current without strong LTCC heating. However, such conductors are relatively difficult to process by laser and to fill with paste. Therefore the line resolution cannot be much smaller than 200 μm. Furthermore, spiral structures are not compatible to this technology. Hot embossing supports both structural resolution and a high current load-carrying capacity but requires additional tooling. Embossing can be used for the production of curved conductors and coils. With the laser cut stencil, structures with small line width and considerable line thickness can be achieved. Screen printing gives a good possibility to produce small conductors, complex structures and coils.
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Krammer, Olivér, László Milán Molnár, László Jakab, and András Szabó. "Modelling the effect of uneven PWB surface on stencil bending during stencil printing process." Microelectronics Reliability 52, no. 1 (January 2012): 235–40. http://dx.doi.org/10.1016/j.microrel.2011.08.012.

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Lazarus, Nathan, Sarah S. Bedair, and Iain M. Kierzewski. "Ultrafine Pitch Stencil Printing of Liquid Metal Alloys." ACS Applied Materials & Interfaces 9, no. 2 (January 9, 2017): 1178–82. http://dx.doi.org/10.1021/acsami.6b13088.

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Clements, David J., Marc P. Y. Desmulliez, and Eitan Abraham. "The evolution of paste pressure during stencil printing." Soldering & Surface Mount Technology 19, no. 3 (July 3, 2007): 9–14. http://dx.doi.org/10.1108/09540910710843720.

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Kay, Robert, and Marc Desmulliez. "A review of stencil printing for microelectronic packaging." Soldering & Surface Mount Technology 24, no. 1 (February 3, 2012): 38–50. http://dx.doi.org/10.1108/09540911211198540.

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Li, Y., R. L. Mahajan, and N. Nikmanesh. "Fine Pitch Stencil Printing Process Modeling and Optimization." Journal of Electronic Packaging 118, no. 1 (March 1, 1996): 1–6. http://dx.doi.org/10.1115/1.2792121.

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In this paper, we present a statistical-neural network modeling approach to process optimization of fine pitch stencil printing for solder paste deposition on pads of printed circuit boards (PCB). The overall objective was to determine the optimum settings of the design parameters that would result in minimum solder paste height variation for the new board designs with 20-mil, 25-mil, and 50-mil pitch pad patterns. As a first step, a Taguchi orthogonal array, L27, was designed to capture the main effects of the six important printing machinery parameters and the PCBs pad conditions. Some of their interactions were also included. Fifty-four experimental runs (two per setting) were conducted. These data were then used to construct neural network models relating the desired quality characteristics to the input design parameters. Our modular approach was used to select the appropriate architecture for these models. These models in conjunction with the gradient descent algorithm enabled us to determine the optimum settings for minimum solder paste height variation. Confirming experiments on the production line validated the optimum settings predicted by the model. In addition to the combination of all the three pad patterns, i.e., 20, 25, and 50 mil pitch pads, we also built neural network models for individual and dual combinations of the three pad patterns. The simulations indicate different optimum settings for different pad pattern combinations.
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HASLEHURST, L., and N. N. EKERE. "PARAMETER INTERACTIONS IN STENCIL PRINTING OF SOLDER PASTE." Journal of Electronics Manufacturing 06, no. 04 (December 1996): 307–16. http://dx.doi.org/10.1142/s0960313196000251.

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STACEY, H. J. "Improvements in or connected with Stencil Printing Apparatus." Journal of the Society of Dyers and Colourists 23, no. 10 (October 22, 2008): 255. http://dx.doi.org/10.1111/j.1478-4408.1907.tb00389.x.

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32

Li, L., and P. Thompson. "Stencil printing process development for flip chip interconnect." IEEE Transactions on Electronics Packaging Manufacturing 23, no. 3 (July 2000): 165–70. http://dx.doi.org/10.1109/6104.873243.

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33

Seong, Kwang-dong, Jae-Yeong Jung, Jeongmin Kang, Da-Seul Kim, Lulu Lyu, Soonmin Seo, Ju-Hyung Kim, and Yuanzhe Piao. "Direct printing of high-performance micro-supercapacitors on flexible substrates using polymeric stencil masks with highly precise interdigitated patterns." Journal of Materials Chemistry A 8, no. 48 (2020): 25986–94. http://dx.doi.org/10.1039/d0ta09811f.

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A direct printing method for micro-supercapacitors, based on metal–organic deposition inks and polymeric stencil masks, is presented, facilitating simultaneous fabrication of multiple devices with outstanding electrochemical properties.
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34

Kaneko, Tsukasa, Kazuki Iwata, and Makiko Kobayashi. "Piezoelectric sol-gel composite film fabrication by stencil printing." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 62, no. 9 (September 2015): 1686–95. http://dx.doi.org/10.1109/tuffc.2014.006870.

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35

Lin, Jhih-Fong, Melinda Mohl, Mikko Nelo, Geza Toth, Ákos Kukovecz, Zoltán Kónya, Srividya Sridhar, et al. "Facile synthesis of nanostructured carbon materials over RANEY® nickel catalyst films printed on Al2O3 and SiO2 substrates." Journal of Materials Chemistry C 3, no. 8 (2015): 1823–29. http://dx.doi.org/10.1039/c4tc02442g.

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Films of porous RANEY® Ni catalyst particles deposited on substrates by stencil printing offer a facile platform for synthesizing nanostructured carbon/nickel composites for direct use as electrodes in electrochemical and field emitter devices.
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36

Li, Y., R. L. Mahajan, and G. Subbarayan. "The Effect of Stencil Printing Optimization on Reliability of CBGA and PBGA Solder Joints." Journal of Electronic Packaging 120, no. 1 (March 1, 1998): 54–60. http://dx.doi.org/10.1115/1.2792286.

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As a follow-up and conclusion to previous work in stencil printing process modeling and optimization (Li et al., 1996), we investigate the effect of stencil printing optimization on the reliability of the ceramic and plastic ball grid arrays. For ceramic ball grid arrays, the eutectic solder fillet shape is calculated using a series of simple mathematical equations. The thermal strain distributions within the solder joints after two cycles of accelerated thermal cycling test are estimated using three-dimensional finite element models. The modified Coffin-Manson relationship is applied to calculate the mean fatigue lives of the solder joints. The results reveal that an optimized stencil printing process significantly reduces variation in the fatigue life of ceramic ball grid arrays. The results also show that the fatigue life of ceramic ball grid arrays is very sensitive to the card-side solder volume. The maximum strain region shifts from the card-side eutectic solder to the module side as the card-side eutectic solder volume increases. This shift in maximum strain suggests that there exists an optimum ratio between the card-side solder volume and the module-side solder volume for the reliability of a given ceramic ball grid array design. The implications of this for the package developers and users are discussed. The calculations indicate that the fatigue life of plastic ball grid arrays is almost insensitive to the card-side solder volume.
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37

Krammer, Oliver, Tareq I. Al-Ma’aiteh, Balazs Illes, David Bušek, and Karel Dušek. "Numerical investigation on the effect of solder paste rheological behaviour and printing speed on stencil printing." Soldering & Surface Mount Technology 32, no. 4 (June 23, 2020): 219–23. http://dx.doi.org/10.1108/ssmt-11-2019-0037.

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Purpose The purpose of this paper is to investigate the effect of different viscosity models (Cross and Al-Ma’aiteh) and different printing speeds on the numerical results (e.g. pressure over stencil) of a numerical model regarding stencil printing. Design/methodology/approach A finite volume model was established for describing the printing process. Two types of viscosity models for non-Newtonian fluid properties were compared. The Cross model was fitted to the measurement results in the initial state of a lead-free solder paste, and the parameters of a Al-Ma’aiteh material model were fitted in the stabilised state of the same paste. Four different printing speeds were also investigated from 20 to 200 mm/s. Findings Noteworthy differences were found in the pressure between utilising the Cross model and the Al-Ma’aiteh viscosity model. The difference in pressure reached 33-34% for both printing speeds of 20 and 70 mm/s and reached 31% and 27% for the printing speed of 120 and 200 mm/s. The variation in the difference was explained by the increase in the rates of shear by increasing printing speeds. Originality/value Parameters of viscosity model should be determined for the stabilised state of the solder paste. Neglecting the thixotropic paste nature in the modelling of printing can cause a calculation error of even approximately 30%. By using the Al-Ma’aiteh viscosity model over the stabilised state of solder pastes can provide more accurate results in the modelling of printing, which is necessary for the effective optimisation of this process, and for eliminating soldering failures in highly integrated electronic devices.
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38

Zhang, Teng, Xiaoqing Mu, Ming Jiang, Leping Huang, and Jinchao Zhao. "Use of electrospun fiber membrane as the screen printing stencil for high definition printing." Materials Research Express 6, no. 11 (November 8, 2019): 1150h7. http://dx.doi.org/10.1088/2053-1591/ab51d2.

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39

Rodriguez, G., and D. F. Baldwin. "Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes." Journal of Electronic Packaging 121, no. 3 (September 1, 1999): 169–78. http://dx.doi.org/10.1115/1.2792680.

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Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.
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40

Ezawa, Hirokazu, Masaharu Seto, Masahiro Miyata, and Hiroshi Tazawa. "Polymer film deposition with fine pitch openings by stencil printing." Microelectronics Reliability 43, no. 3 (March 2003): 473–79. http://dx.doi.org/10.1016/s0026-2714(02)00327-x.

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41

Khader, Nourma, and Sang Won Yoon. "Online control of stencil printing parameters using reinforcement learning approach." Procedia Manufacturing 17 (2018): 94–101. http://dx.doi.org/10.1016/j.promfg.2018.10.018.

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42

Khader, Nourma, Jaehwan Lee, Duk Lee, Sang Won Yoon, and Haeyong Yang. "Multi-objective optimization approach to enhance the stencil printing quality." Procedia Manufacturing 38 (2019): 163–70. http://dx.doi.org/10.1016/j.promfg.2020.01.022.

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43

Partridge, S. A. "The Rôle of the Stencil in High Definition Screen Printing." Circuit World 13, no. 2 (January 1987): 4–13. http://dx.doi.org/10.1108/eb043860.

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44

Barajas, Leandro G., Magnus B. Egerstedt, Edward W. Kamen, and Alex Goldstein. "Stencil Printing Process Modeling and Control Using Statistical Neural Networks." IEEE Transactions on Electronics Packaging Manufacturing 31, no. 1 (January 2008): 9–18. http://dx.doi.org/10.1109/tepm.2007.914236.

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45

Mannan, S. H., N. N. Ekere, I. Ismail, and E. K. Lo. "Squeegee deformation study in the stencil printing of solder pastes." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A 17, no. 3 (1994): 470–76. http://dx.doi.org/10.1109/95.311758.

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46

Lau, J. H., and C. Chang. "Taguchi design of experiment for wafer bumping by stencil printing." IEEE Transactions on Electronics Packaging Manufacturing 23, no. 3 (July 2000): 219–25. http://dx.doi.org/10.1109/6104.873251.

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47

Ishak, M. H. H., M. S. Abdul Aziz, M. H. S. Abdul Samad, Farzad Ismail, and M. A. A. Mohd Salleh. "Influence of squeegee impact on stencil printing process: CFD approach." IOP Conference Series: Materials Science and Engineering 957 (November 25, 2020): 012065. http://dx.doi.org/10.1088/1757-899x/957/1/012065.

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48

Tsai, Tsung-Nan. "Modeling and optimization of stencil printing operations: A comparison study." Computers & Industrial Engineering 54, no. 3 (April 2008): 374–89. http://dx.doi.org/10.1016/j.cie.2007.08.001.

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49

Rangelow, I. W., F. Shi, P. Hudek, I. Kostic, E. Hammel, H. Löschner, G. Stengl, and E. Cekan. "Silicon stencil masks for masked ion beam lithography proximity printing." Microelectronic Engineering 30, no. 1-4 (January 1996): 257–60. http://dx.doi.org/10.1016/0167-9317(95)00240-5.

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50

Khader, Nourma, and Sang Won Yoon. "Adaptive optimal control of stencil printing process using reinforcement learning." Robotics and Computer-Integrated Manufacturing 71 (October 2021): 102132. http://dx.doi.org/10.1016/j.rcim.2021.102132.

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