Dissertations / Theses on the topic 'Stencil printing'

To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis explores the use of n-type Cz silicon with printed metallisation and diffusion from printed sources in creating industrially applicable solar cell structures. The thesis begins with an overview of existing n-type solar cell structures, previous printed thick film metallisation research and previous research into printed dopant sources. A study of printed thick-film metallisation for n-type solar cells is then presented, which details the fabrication of boron doped p-type emitters followed by a survey of thick film Ag, Al, and Ag/Al inks for making contact to a p-emitter layer. Drawbacks of the various inks include high contact resistance, low metal conductivity or both. A cofire regime for front and rear contacts is established and an optimal emitter selected. A study of printed dopant pastes is presented, with an objective to achieve selective, heavily doped regions under metal contacts without significantly compromising minority carrier lifetime in solar cells. It is found that heavily doped regions are achievable with both boron and phosphorus, but that only phosphorus paste was capable of post-processing lifetime compatible with good efficiencies. The effect of belt furnace processing on n-type silicon wafers is explored, with large losses in implied voltage observed due to contamination of Si wafers from transition metals present in the belt furnace. Due to exposure to chromium in the belt furnace, no significant advantage in using n-type wafers instead of p-type is observed during the belt furnace processing step. Finally, working solar cells with efficiencies up to 16.1% are fabricated utilising knowledge acquired in the earlier chapters. The solar cells are characterised using several new photoluminescence techniques, including photoluminescence with current extraction to measure the quality of metal contacts. The work in this thesis indicates that n-type printed silicon solar cell technology shows potential for good performance at low cost.

Solder pastes are complex materials whose properties are governed by many factors. Variations exhibited in solder paste characteristics make it increasingly difficult to understand the correlations between solder paste properties and their printing process performance. The recent EU directives on RoHS (Restriction of Hazardous Substances – enacted by UK regulations) and WEEE (Waste from Electrical and Electronic Equipment) has led to the use of lead-free soldering in the SMA (surface mount assembly) process, and an urgent need for better understanding of the characteristics and printing performance of new solder paste formulations. Equally, as the miniaturisation of hand-held and consumer electronic products continues apace, the solder paste printing process remains a real challenge to the electronics assembly industry. This is because the successful assembly of electronic devices at the ultra-fine pitch and flip-chip geometry requires the deposition of small and consistent paste deposits from pad to pad and from board to board. The paste printing process at this chip-scale geometry depends on conditions such as good paste roll, complete aperture filling and paste release from the apertures onto the substrate pads. This means that the paste flow and deformation behaviour, i.e. the paste rheology, is very important in defining the printing performance of any solder paste. Rheological measurements can be used as a tool to study the deformation or flow experienced by the pastes during the stencil printing process. In addition, the rheological measurements can also be used as a quality control tool in the paste production process for identifying batch-to-batch variation, and to reduce the associated printing defects in the paste printing process. The work reported here on the characterisation of lead-free solder pastes and their correlation with the stencil printing process is divided into five main parts. The first part concerns the study of the effect of variations in flux and particle size distribution (PSD) on the creep recovery performance of lead-free solder pastes used for flip-chip assembly. For this study, a novel technique was calculating the extent of paste recovery and hence characterising the slumping tendency in solder pastes. The second part of the study concerns the influence of long-term ageing on the rheology and print quality of lead-free solder pastes used for flip-chip assembly, and the main focus of the work was to develop methodologies for benchmarking new formulations in terms of shelf life, rheological deterioration and print performance. The third part of the work deals with a rheological simulation study of the effect of variation in applied temperature on the slumping behaviour of lead-free solder pastes, and the fourth part considers the rheological correlation between print performance and abandon time for lead-free solder paste used for flip-chip assembly. The final part of the study concerns the influence of applied stress, application time and recurrence on the rheological creep recovery behaviour of lead-free solder pastes. The research work was funded through the PRIME Faraday EPSRC CASE Studentship grant, and was carried out in collaboration with Henkel Technologies, Hemel Hempstead, UK. The extensive set of results from the experimental programme, in particular relating to the aspect of key paste performance indicators, has been adapted by the industrial partner for implementation as part of a quality assurance (QA) tool in its production plant, and the results have also been disseminated widely through journal publications and presentations at international conferences.

One of the main challenges facing the electronics manufacturing industry in solder paste printing for ultra-fine pitch surface mount and flip-chip assembly is the difficulty in achieving consistent paste deposit volumes from pad-to-pad. At the very small aperture geometries required for ultra-fine pitch and flip chip assembly, flow properties of the paste becomes one of the dominant factors in the printing process. It is widely accepted that over 60% of assembly defects originate from the solder paste printing stage, and hence the urgent need for a better understanding of solder paste rheology, its behaviour during printing, and its impact on defect generation. This understanding is essential for achieving proper control of the printing process. This thesis presents the result of work on the modelling and computer simulation of solder paste behaviour during printing, and consists of three main parts. The first part concerns the modelling of paste behaviour in stencil printing using a vibrating squeegee. The performance of the vibrating squeegee is analysed and process models developed for predicting the ideal printing conditions. In the second part, the random packing of solder powder and the microstructure of solder paste are numerically simulated by applying Monte Carlo method. The effect particle size distributions on the paste microstructure is studied in this part. Based on the simulation results of the second part, the third part concerns the study of the effect of particle size distribution on the paste viscosity and the hydrodynamic interaction between adjacent particles during paste flow. A theoretical enhanced model for predicting the viscosity of dense suspensions such as solder pastes has been developed. This correlates relative viscosity with particle size distribution and with solid volume fraction of dense suspensions. The results of the work have wide applicability: firstly for solder paste manufacturers in optimising paste printing performance at the development stage and for stencil printing equipment manufacturers in specifying the ideal conditions for defect free printing. The simulation algorithm and the viscosity model are also applicable for a wide range of industrial processing applications; in particular metal or ceramic powder compaction, material surface coating, chemical or food material transportation.

L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électrique et mécanique avec le niveau de packaging suivant. La technique de dépôt par sérigraphie de pâte à braser est récemment devenue pratique en raison de son adaptation aux alliages sans plomb. Cette méthode présente l'avantage d'un faible coût et d'une possible production à grande échelle. Nous avons donc choisi de développer cette technique afin d’obtenir des matrices de connexions électriques de dimensions comprises entre 50 μm et 100 μm, pour une pâte à braser de type Sn3.0Ag0.5Cu. Nous avons déterminé les paramètres de sérigraphie afin d’obtenir un minimum d’étalement de pâte pour un remplissage maximum des ouvertures du masque choisi en Ni-électroformé d’épaisseur 50μm : une vitesse de racle de 20mm/s et une vitesse de démoulage de 4mm/s sont par exemple à retenir pour une pâte de type 5. L’étude du masque de sérigraphie a conduit au choix d’ouvertures circulaires. Des formes de billes circulaires ont été obtenues pour des UBM (Under Bump Metallurgy) également circulaires, de diamètre ¼ et ½ le diamètre de l’ouverture du masque. L’optimisation du profil de refusion a permis de déterminer qu’un palier à 180°C, un TAL de 90s ou plus et une température maximale à 250°C favorisaient l’obtention de billes circulaires avec absence de vides. Pour une pâte de type 6, des billes de 60à 70μm de diamètre ont été obtenues pour des ouvertures de masque de 100μm. Une étude de fiabilité de ces billes à partir de tests de cisaillement et de l’analyse des IMC (composés intermétalliques) formés après refusion a permis de montrer que des UBM en Cr-Cu-Au, de diamètre égal à la moitié de l’ouverture du masque, permettaient d’assurer un meilleur maintien mécanique des billes
The semiconductor industry has continuously improved its products by increasing the density of integration resulting in an increasing of the I/Os, always with a low cost requirement. To obtain high-density and high-speed packaging, the Flip-Chip interconnection technology was introduced by IBM also called C4 (Control Collapse Chip Connection). Solder bumps have been widely used in electronic industry and were generally based on the Sn-Pb alloy, for its low melting point and good wetting property. Containing highly toxic element (Pb), Pb-Sn solder alloy has been banned. The ternary alloy Sn-Ag-Cu seems to be the best compromise, in fact it as physical and chemical characteristics equivalent to that of Sn-Pb.In this study we are interested to optimize stencil printing process and adjust it with the flip-chip technology, in order to obtain solder bumps which height is between 50µm and 100µm associated to pitches less than or equal to 200µm, using Sn-3.0Ag-0.5Cu solder paste. We have optimized the stencil printing parameters machine, the stencil apertures shape and size (circular shape and 50µm height, for a Ni-electroformed stencil). Spherical solder balls have been achieved with circular UBM (Under Bump Metallurgy), which diameter is ¼ and ½ the diameter of the stencil aperture. The reflow thermal profile is the key to the formation of a reliable solder bump. It must allow a homogeneous reflow for all particles of the metallic solder paste. We define a thermal profile with a Time above liquidus (TAL) of 90s, a temperature in soaking zone (Ts) of 180°C and a maximum temperature (Tmax) of 250°C. For type 6 solder pastes, balls of 60-70µm diameter have been obtained for 100µm stencil apertures.The quality of a solder joint is directly related to the adhesion of the solder ball to the substrate. Among the various methods of mechanical testing, shear testing is the most widely used to assess the strength of the attachment of beads to the substrate and determine the fragility of the ball at the interface caused by the intermetallic layer compounds (IMC) formed after the reflow step. We have shown that Cr-Cu-Au UBM, with a diameter equal to the half of the stencil aperture, ensure the mechanical adhesion of the balls

This master´s thesis deals with QFN packages soldering and technology procedures optimization. The aim of theoretical part is description of QFN packages, their assembly and reflow soldering on PCB in HONEYWELL. The aim of the practical part is to propose a method of measuring temperature and optimizing the thermal profiles of selected PCB with QFN packages by using convection (HONEYWELL) and infrared (BUT) reflow ovens. Comparison and evaluation of thermal profiles for 3 production PCBś with QFN packages using solder paste AIM NC257-2 were realised. The main part of master´s thesis are appearance evaluation of solder joints, preparing microsection and measuring intermetallic layers thickness by using the optical and the scanning electron microscopes, analysation and study of QFN defects created during soldering proces. These tests were performed with 2 production PCB´s. Optimization of SPI and soldering technology procedures where were analyzed QFN packages were processed on one type of PCB. Interesting part of this diplomma thesis is creating of the 3D heat transfer model of QFN package during the reflow soldering in SolidWorks.

The topic of this dissertation is the derivation, development, and evaluation of novel hybrid algorithms for process control that use a limited number of measurements and that are suitable to operate in the presence of large amounts of process noise. As an initial step, affine and neural network statistical process models are developed in order to simulate the steady-state system behavior. Such models are vitally important in the evaluation, testing, and improvement of all other process controllers referred to in this work. Afterwards, fuzzy logic controller rules are assimilated into a mathematical characterization of a model that includes the modes and mode transition rules that define a hybrid hierarchical process control. The main processing entity in such framework is a closed-loop control algorithm that performs global and then local optimizations in order to asymptotically reach minimum bias error; this is done while requiring a minimum number of iterations in order to promptly reach a desired operational window. The results of this research are applied to surface mount technology manufacturing-lines yield optimization. This work achieves a practical degree of control over the solder-paste volume deposition in the Stencil Printing Process (SPP). Results show that it is possible to change the operating point of the process by modifying certain machine parameters and even compensate for the difference in height due to change in print direction.

碩士
樹德科技大學
經營管理研究所
98
台灣經濟的增長已經嚴重依賴於高科技廠商在製造集成電路和3C產品。計算機和電信產品的主要類別，通過建立電子裝配過程。表面貼裝技術（SMT ）是一個主要手段，生產各種電子產品。提升整體素質和能力的SMT組裝線為主體，以降低生產成本，提高質量保證水平，並成為台灣主要的挑戰保持住在競爭edge.SMT製成品的主要方法是產生各種電子產品。噴花是一個最重要的SMT裝配過程。根據行業報告，平均60 ％的焊接缺陷是由於噴花進程。 在本研究中，數據挖掘方法挖掘潛在的印刷缺陷模式。通過實驗設計（ DOE）的結構進行了數據收集利用決策樹算法（ C5.0 ） ，方差分析（方差）算法。此外，根據分類的缺陷，開發預測缺陷印刷parameters.The根據調查結果，可進一步提供電子製造商能夠加快行安裝程序，提高焊接質量。

碩士
樹德科技大學
經營管理研究所
93
Following scientific and technological progress, the requirements of electronic products become increasingly thinner, lighter, smaller and functionally more powerful models, such as cell phones, laptop computers, PDAs, digital cameras and other gadgets are sought after. In view of this perspective, electronics manufacturers have been developing more stable production methods that assure greater stability, which in turn promotes the development of better technologies for printed circuits board assembly (PCBA). Of the latter, the key lies in the development of the Surface Mount Technology (SMT) assembly process. Stencil printing is one of the most important processes in SMT assembly. An average 60% of soldering defects are attributed to inadequate stencil printing parameter settings. Today, there are no standard parameter sets for stencil printing in the electronic industry. The manufacturing process of new products always requires trial printing before production launch, through which the printing parameters were obtained by trial and error approach. In this study, two optimization models of stencil printing parameters were developed. A fractional factorial experiment design was conducted for collecting structured data to closely investigate the relationships of inputs and outputs and followed by using Response Surface Method (RSM) and Genetics algorithms (GAs) to optimize the given process. Finally, two optimized parameter sets obtained and compared with the empirical SPC data for performance assessments. Results show that the parameter combinations optimized by GAs is superior to RSM. The findings can further provide electronic manufacturers to speed up line setup procedure and improve soldering quality.

碩士
國立高雄科技大學
工業工程與管理系
108
Surface mount technology (SMT) is the main process to produce many types of modern electronics products in electronics assembly industry. SMT consists of three sub-processes: (1) solder paste stencil printing, (2) component placement, and (3) solder reflow. Based on literatures and industrial reports, a poor solder paste printing performance can lead to an averaged 60% of soldering defect, which increases manufacturing costs and jeopardizes product quality. Generally, engineers integrate their working experience with a variety of trial-and-error approaches to resolve stencil printing problems. However, this process troubleshooting approach also induces a lot of nonproductive production time and costs. The thin quad plat package (TQFP) is with the highest stencil printing defect rate in SMT process. In this research, three solder paste volume prediction models include multiple regression, regression tree, and neural network were developed using the experimental data, the parameter settings of stencil printer, and solder paste inspection data, to quickly predict the solder paste volume of a TQFP package. These three prediction models were validated and evaluated using empirical data collected from production line. The evaluation result shows that regression tree model exhibits a superior prediction accuracy and dynamic changes of printing parameters. This research results can be used as the basis of smart manufacturing and as a reference and application in the electronics assembly industry.

碩士
明新科技大學
工業工程與管理研究所
97
Due to the trend of miniature of electronic products been evolved, the application of surface mount technology (SMT) to the printed circuit boards (PCBs) assemblies is more and more popular, matured and versatile.The process is still not well understood as indicated by the fact that industry reports 52–71% (SMT) defects are related to the solder paste stencil printing process (SPP). This research presents a neural network model for the stencil printing process in surface mount technology manufacturing of printed circuit boards. A Design of Experiment (DOE) was conducted for collecting structured data to closely investigate the relationships of inputs and outputs and followed by using Artificial Neural Network (ANN) to optimize the given process.The optimization is performed by minimizing the weighted mean squared error with respect to the desired solder brick area; furthermore, in the case when multiple solutions exist, the set point that yields the lowest variance is used.

碩士
明新科技大學
工程管理研究所
96
Following by the highly development of the consuming electronic products and the trend toward the miniatureel size and user-friendly interfaces, the well-implementation of Surface Mount Technology (SMT) in today’s printed circuit board (PCB) assemblies is becoming more crucial during the processes. With the increasing difficulties and complexity of surface mounted techniques due to the miniature of electronic devices, the process yield descends and the extra cost increases. Therefore the improvement of the producing process is becoming more and more urgent now. According to the related research, 52%~71% of the SMT process’ defects come from stencil printing process; so, if we can effectively eliminate the printing process defects, we can largely improve the yield of the SMT. DOE and Regression techniques are applied in this research to explore the relations between geometric features of stencil aperture and amount of solder paste deposition. With the experiment analysis conducted the solder paste deposition models were derived. First, we consider the significant factors that impact the process of stencil printing. Then, we use ANOVA to find out the factors that influence the solder paste deposition. Next, we use RSM to build up the models and optimize the parameters. The result of this research is to develop the regression models of the round and square aperture in the paste deposition, find out the optimal solutions of stable paste deposition and develop the quality control chart of the paste. The goal is to offer the performance evaluation of solder paste deposition for the process engineers when they attempt to design the appropriate stencil at the very first beginning of process development.

碩士
華梵大學
工業工程與經營資訊學系碩士班
95
The demands of electronic products towards thinner, lighter, smaller and more powerful functionally. Electronics manufacturers are devoted to more stable process in the Surface Mount Technology (SMT) assembly domain. One of the key process in SMT assembly is stencil printing for solder paste deposition. Literature indicates that nearly 60% of soldering defects related to stencil printing process. Currently, there is no standard parameter setting for stencil printing in the electronic industry. The determination of printing parameters for new product is based on trial and error. This study employs an Intelligent Parameter Design Method to determine optimal parameters used in the stencil printing process. This helps reduce the cost and time required. First, the Taguchi based experimental design is used to determine the desired printing parameters and the influences of solder paste deposited during printing. The concept of Artificial Neural Networks (ANNs) with the best search strategy, implemented through ANNDOE software, is then employed to identify the optimal parameters. Finally, comparison is made between the performance of suggested parameters through Taguchi Method and Intelligent Parameter Design. Result indicates that the Intelligent Parameter Design Method performed superior than Taguchi Method, in respect to the consistency of solder paste deposition and the target paste volume. The improvement rates is improved from 40.88% to 74.56%.

碩士
國立成功大學
製造工程研究所碩博士班
90
Surface Mount Technology (SMT) assembly is the placement and attachment of electronic components to the surface of a printed circuit board, and it has become the key technology to transform manufacturing in the electronics industry to continuously respond to the needs of the global market. The relationship between the input/output variables in SMT acts nonlinearly and severely. The stencil printing is one of the most critical stages and accounts for 52~71% of overall soldering defects. This research will help in understanding the solder paste stencil printing process and identifying the critical variables that influence the volume of deposited solder paste. Through design of experiment and neural networks, a quality control system of stencil printing is established that helps engineers in troubleshooting the malfunctioned process and to improve solderability.

碩士
國立成功大學
工業與資訊管理學系專班
96
Solder paste printing is the first assembly process of surface mount technology (SMT). Researches had been shown that 52%-71% of the assembly defects were caused by the improper setup of the printing process. The former setup of process parameter and material choice are most proceeding by design of experiment (DOE). This will be not only waste time also high cost. It is an important issue for using current process data and how to deal with it that becomes the meaning predict model. This research applies model tree and use stencil open hole shape to be the control variable. The five measure points, solder paste brand (include metal ingredient, stickiness and micro-particle size), snapoff, stencil thickness, squeegee material, squeegee angle, squeegee pressure, print speed, relative print direction and relative pad size, amount to ten attributes, will be the input variables. The checkout solder paste quantity will be the output variable. We construct the quality control forecast system model for proceeding SMT solder paste printing process. Finally, we use the snapoff, stencil thickness and squeegee material for the attribute partition point, and find both solder paste brand and relative pad size are two statistical insignificance attributes. This research also makes the comparison with forecasting ability to use Classification and Regression Tree (CART). Finally, it indeed actually has better forecasting effect.

碩士
國立成功大學
材料科學及工程學系碩博士班
91
The objective of this research was to investigate the mechanical and electrical properties of solder bumps produced with solder paste by printing. The shear strength of solder bumps and the interfacial reaction behavior between solder and UBM was investigated after reliability tests. Besides, it was also to measure the electrical resistance of flip chip bonded solder joints and to investigate the correlation between the change of the electrical resistance and the reaction behavior of the materials after different environmental tests. The interfacial investigation of solder bump indicated that Ni3Sn4 was formed. It was also observed that the (AuXNi1-X)Sn4 was formed between the Ni3Sn4 layer and solder after aging. A raise in aging temperature enhances the growth of (AuXNi1-X)Sn4 and inhibits the growth of Ni3Sn4. The average shear strength of solder bumps after reflow was about 50g, and the fracture occurred at the solder. It was also found that the shear strength of solder bumps was decreased with reflow times and aging time. But the fracture still occurred at the solder after reliability tests. The experimental results revealed that the lowering in shear strength was not induced by intermetallic compounds. The intermetallics exhibit a good adhesion between solder and UBM after reliability tests. The electrical test results showed that the increase of electrical resistance of solder joints after the multiple reflow test and high temperature storage test was ascribed to the growth of intermetallic compounds. In addition, the oxidation of solder and elimination of defects also affect the electrical resistance of the annealed solder joints. Furthermore, it was found that the electrical resistance of the solder joints greatly increases after the humidity-temperature test and thermal cycling test. The humidity-temperature test affect the electrical resistance of solder joints through the circuit corrosion and oxidation of solder. The thermal cycling test resulted in the formation of crack which caused the solder joint failure.

碩士
國立中山大學
機械與機電工程學系研究所
102
This work developed a novel micro-structured stencil for high precision printings. Printing technology are the major techniques for producing printing circuit board in electronic industry. Because, printing process are usually in low-cost and mass production for producing products. However, it is difficult to produce small patterns using conventional printing technique due to the limitation of the woven mesh or stencil’s thickness. Therefore, the critical dimension for typical printing process is limited between 50 µm to 100 µm. The electronic products are tending to smaller, thinner and light for the consumer market. In other words, the printing methods are tending to smaller line width, thinner printing layer and higher printing resolution. This study developed a double layer structure stencil for printing ultra-fine line and thin film on three kind substrate. Each substrate has different surface energies. The printing test result compare the printed paste width and thickness from different printing condition. To understand the influence of surface energy for printed paste. This work successfully developed a novel process for fabricating ultra-thin stencil with a buffer reservoir utilizing the combination of AZ4620 positive photoresist (PR) and SU-8 negative PR as the electroplating molds. The fabrication process include multi- photolithography and electroplating process. A low-cost microscope glass slide was used as the substrate for producing the stencil. In order to meet the requirement for metal electroplating and structure releasing, the Ti/Au layers of 50 nm in thickness were coated on the substrate by sputtering. The injection hole is defined by the AZ4620 PR since AZ4620 can well sustain the nickel plating bath in a short electroplating time. On the contrary, the SU-8 PR can sustain long electroplating time of the nickel plating bath then prevented the first metal layer damage in second electroplating process. The high transparency of SU-8 PR also makes it easy to align the two PR plating molds. Prior to the nickel plating process, the patterned substrate was activated with CCP to enhance the surface wettability. The plasma treatment in order to further enhance the adhesion and the roughness for nickel layer. The metal structure was then released from the glass substrate using a diluted HF solution. The buffer reservoir was used to provide the necessary strength and uniform paste extrusion. Moreover, the buffer reservoir also reduced printing pressure from the injection hole. And the bridge structure to avoid the microstructure in stiction. Improved the stencil printing lifetime. Results showed that the developed stencil successfully printed silver paste with the pattern of around 15 μm in width and 1 μm in thickness. And the printing pitch also down to 20 μm. The complete right angle patterns confirmed that the developed stencil was capable for printing patterns with desired orientations. The blocking issued was excluded for the stencil and the printed pattern. The method develop in the present study will give substantial impact on the modern printing technology.