Relevant bibliographies by topics / Stencil printing

Academic literature on the topic 'Stencil printing'

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Published: 4 June 2021
Last updated: 6 February 2022

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Journal articles on the topic "Stencil printing"

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Lee, Yong‐Won, Keun‐Soo Kim, and Katsuaki Suganuma. "The behaviour of solder pastes in stencil printing with electropolishing process." Soldering & Surface Mount Technology 25, no. 3 (June 21, 2013): 164–74. http://dx.doi.org/10.1108/ssmt-12-2012-0027.

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PurposeThe purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.Design/methodology/approachDuring the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.FindingsThe results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.Originality/valueDue to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.
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Vallabhajosyula, Phani. "Stencil Print solutions for Advance Packaging Applications." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000646–51. http://dx.doi.org/10.4071/isom-2017-poster1_124.

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Abstract This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging. As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high-performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um–40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package. Cavity technology can be an effective solution in reducing the total assembled PCB thickness (Z-height), most importantly, on designs utilizing taller - stacked devices. Traditionally, dipping process or dispensing process was used to deposit solder paste, flux, or glue on uneven surfaces. However, this takes a longer time when compared to printing using a stencil printer. Reservoir printing using a stencil printer has greater potential in such application. Extensive work has been done in the past to print glue, solder paste and/or flux into cavities using reservoir printing. This paper focuses on printing solder paste into multiple cavities (stencil pockets) with depths ranging from 355 microns to 450 microns, and with varying cavity size, wall angles and various stencil thicknesses ranging from 100 microns to 150 microns. Apertures varying in area ratio were placed in these cavities and experiments were conducted to analyze the print performance of the stencils. As the size of the components and boards/substrates gets smaller - closer placement of components to the cavity (stencil pocket) walls needed to be assessed as well. These applications, the associated stencil design and print results were discussed in detail in this paper.
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Wickström, Henrika, Rajesh Koppolu, Ermei Mäkilä, Martti Toivakka, and Niklas Sandler. "Stencil Printing—A Novel Manufacturing Platform for Orodispersible Discs." Pharmaceutics 12, no. 1 (January 1, 2020): 33. http://dx.doi.org/10.3390/pharmaceutics12010033.

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Stencil printing is a commonly used printing method, but it has not previously been used for production of pharmaceuticals. The aim of this study was to explore whether stencil printing of drug containing polymer inks could be used to manufacture flexible dosage forms with acceptable mass and content uniformity. Formulation development was supported by physicochemical characterization of the inks and final dosage forms. The printing of haloperidol (HAL) discs was performed using a prototype stencil printer. Ink development comprised of investigations of ink rheology in combination with printability assessment. The results show that stencil printing can be used to manufacture HAL doses in the therapeutic treatment range for 6–17 year-old children. The therapeutic HAL dose was achieved for the discs consisting of 16% of hydroxypropyl methylcellulose (HPMC) and 1% of lactic acid (LA). The formulation pH remained above pH 4 and the results imply that the drug was amorphous. Linear dose escalation was achieved by an increase in aperture area of the print pattern, while keeping the stencil thickness fixed. Disintegration times of the orodispersible discs printed with 250 and 500 µm thick stencils were below 30 s. In conclusion, stencil printing shows potential as a manufacturing method of pharmaceuticals.
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YAMADA, Hiromichi. "Stencil Printing Ink." Journal of the Japan Society of Colour Material 70, no. 11 (1997): 751–56. http://dx.doi.org/10.4011/shikizai1937.70.751.

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Yu, JiangYou, Le Cao, Hao Fu, and Jun Guo. "A method for optimizing stencil cleaning time in solder paste printing process." Soldering & Surface Mount Technology 31, no. 4 (September 2, 2019): 233–39. http://dx.doi.org/10.1108/ssmt-10-2018-0037.

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PurposeStencil cleaning is an important operation in solder paste printing process. Frequent cleaning may interrupt printing process and increase idle time, as well as loss for performing cleaning. This paper aims to propose a method to optimize the stencil cleaning time and reduce unnecessary cleaning operations and losses.Design/methodology/approachThis paper uses a discrete-time, discrete-state homogeneous Markov chain to model the stencil printing performance degradation process, and the quality loss during the stencil printing process is estimated based on this degradation model. A stencil cleaning decision model based on renewal reward theorem is established, and the optimal cleaning time is obtained through a balance between quality loss and the loss on idle time.FindingsA stencil cleaning decision model for solder paste printing is established, and numerical simulation results show that there exists an optimal stencil cleaning time which minimizes the long-term loss.Originality/valueStencil cleaning control is very important for solder paste printing. However, there are very few studies focusing on stencil cleaning control. This research contributes to developing a model to optimize the stencil cleaning time in solder paste printing process.
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Pei-Lim, Sze, Kenneth Thum, and Andy Mackie. "Challenges in Fine Feature Solder Paste Printing for SiP Applications." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000245–49. http://dx.doi.org/10.4071/isom-2016-wp12.

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Abstract The rapid development in the Internet of Things (IoT) has seen a surge in demand for System-in-Package (SiP), which is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller components and greater density. 01005 passive components are being used in most of the current SiP technology and the industry is looking at utilizing 008004 passive components for the next generation SiP. The stencil aperture design for 008004 will likely be about half of 01005, and a finer powder size solder paste will be used. The stencil design, stencil thickness, and the types of stencils being used, are crucial in achieving good solder paste printing performance. Due to the need of squeezing more components into a SiP, the gap between neighboring pads can be as close as 50μm; hence, it is crucial to avoid solder bridging for such applications. This paper will discuss the challenges in achieving consistent solder paste printing performance for fine feature applications using Type 6 (5–15μm) powder size solder paste. Test results with different stencil designs, printing parameters, and different solder pastes will be discussed in detail.
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Sriperumbudur, Sai Srinivas, Michael Meilunas, and Martin Anselm. "Solder paste volume effects on assembly yield and reliability for bottom terminated components." Soldering & Surface Mount Technology 29, no. 2 (April 3, 2017): 99–109. http://dx.doi.org/10.1108/ssmt-05-2016-0010.

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Purpose Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations. Design/methodology/approach Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations. Findings Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling. Originality/value Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.
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W. Kay, Robert, Gerard Cummins, Thomas Krebs, Richard Lathrop, Eitan Abraham, and Marc Desmulliez. "Statistical analysis of stencil technology for wafer-level bumping." Soldering & Surface Mount Technology 26, no. 2 (April 1, 2014): 71–78. http://dx.doi.org/10.1108/ssmt-07-2013-0017.

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Purpose – Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues. Design/methodology/approach – In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types. Findings – Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5. Originality/value – Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.
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Whitmore, Mark, and Clive Ashmore. "Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000502–8. http://dx.doi.org/10.4071/isom-2011-wa2-paper2.

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As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.
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Vallabhajosyula, Phani. "Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–18. http://dx.doi.org/10.4071/2017dpc-poster_vallabhajosyula.

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Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.
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Dissertations / Theses on the topic "Stencil printing"

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Braunstein, Daniel J. (Daniel Judah). "Real time process monitoring of solder paste stencil printing." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35374.

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Rodriguez, German Dario. "Analysis of the solder paste release in fine pitch stencil printing processes." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/18867.

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Ismail, Ismarani. "Stencil printing of solder paste for reflow soldering of surface mount technology assembly." Thesis, University of Salford, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.426875.

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Edwards, Matthew Bruce ARC Centre of Excellence in Advanced Silicon Photovoltaics &amp Photonics Faculty of Engineering UNSW. "Screen and stencil print technologies for industrial N-type silicon solar cells." Publisher:University of New South Wales. ARC Centre of Excellence in Advanced Silicon Photovoltaics & Photonics, 2008. http://handle.unsw.edu.au/1959.4/41372.

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To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis explores the use of n-type Cz silicon with printed metallisation and diffusion from printed sources in creating industrially applicable solar cell structures. The thesis begins with an overview of existing n-type solar cell structures, previous printed thick film metallisation research and previous research into printed dopant sources. A study of printed thick-film metallisation for n-type solar cells is then presented, which details the fabrication of boron doped p-type emitters followed by a survey of thick film Ag, Al, and Ag/Al inks for making contact to a p-emitter layer. Drawbacks of the various inks include high contact resistance, low metal conductivity or both. A cofire regime for front and rear contacts is established and an optimal emitter selected. A study of printed dopant pastes is presented, with an objective to achieve selective, heavily doped regions under metal contacts without significantly compromising minority carrier lifetime in solar cells. It is found that heavily doped regions are achievable with both boron and phosphorus, but that only phosphorus paste was capable of post-processing lifetime compatible with good efficiencies. The effect of belt furnace processing on n-type silicon wafers is explored, with large losses in implied voltage observed due to contamination of Si wafers from transition metals present in the belt furnace. Due to exposure to chromium in the belt furnace, no significant advantage in using n-type wafers instead of p-type is observed during the belt furnace processing step. Finally, working solar cells with efficiencies up to 16.1% are fabricated utilising knowledge acquired in the earlier chapters. The solar cells are characterised using several new photoluminescence techniques, including photoluminescence with current extraction to measure the quality of metal contacts. The work in this thesis indicates that n-type printed silicon solar cell technology shows potential for good performance at low cost.
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Marks, Antony Edward. "Characterisation of lead-free solder pastes and their correlation with the stencil printing process performance." Thesis, University of Greenwich, 2012. http://gala.gre.ac.uk/9456/.

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Solder pastes are complex materials whose properties are governed by many factors. Variations exhibited in solder paste characteristics make it increasingly difficult to understand the correlations between solder paste properties and their printing process performance. The recent EU directives on RoHS (Restriction of Hazardous Substances – enacted by UK regulations) and WEEE (Waste from Electrical and Electronic Equipment) has led to the use of lead-free soldering in the SMA (surface mount assembly) process, and an urgent need for better understanding of the characteristics and printing performance of new solder paste formulations. Equally, as the miniaturisation of hand-held and consumer electronic products continues apace, the solder paste printing process remains a real challenge to the electronics assembly industry. This is because the successful assembly of electronic devices at the ultra-fine pitch and flip-chip geometry requires the deposition of small and consistent paste deposits from pad to pad and from board to board. The paste printing process at this chip-scale geometry depends on conditions such as good paste roll, complete aperture filling and paste release from the apertures onto the substrate pads. This means that the paste flow and deformation behaviour, i.e. the paste rheology, is very important in defining the printing performance of any solder paste. Rheological measurements can be used as a tool to study the deformation or flow experienced by the pastes during the stencil printing process. In addition, the rheological measurements can also be used as a quality control tool in the paste production process for identifying batch-to-batch variation, and to reduce the associated printing defects in the paste printing process. The work reported here on the characterisation of lead-free solder pastes and their correlation with the stencil printing process is divided into five main parts. The first part concerns the study of the effect of variations in flux and particle size distribution (PSD) on the creep recovery performance of lead-free solder pastes used for flip-chip assembly. For this study, a novel technique was calculating the extent of paste recovery and hence characterising the slumping tendency in solder pastes. The second part of the study concerns the influence of long-term ageing on the rheology and print quality of lead-free solder pastes used for flip-chip assembly, and the main focus of the work was to develop methodologies for benchmarking new formulations in terms of shelf life, rheological deterioration and print performance. The third part of the work deals with a rheological simulation study of the effect of variation in applied temperature on the slumping behaviour of lead-free solder pastes, and the fourth part considers the rheological correlation between print performance and abandon time for lead-free solder paste used for flip-chip assembly. The final part of the study concerns the influence of applied stress, application time and recurrence on the rheological creep recovery behaviour of lead-free solder pastes. The research work was funded through the PRIME Faraday EPSRC CASE Studentship grant, and was carried out in collaboration with Henkel Technologies, Hemel Hempstead, UK. The extensive set of results from the experimental programme, in particular relating to the aspect of key paste performance indicators, has been adapted by the industrial partner for implementation as part of a quality assurance (QA) tool in its production plant, and the results have also been disseminated widely through journal publications and presentations at international conferences.
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He, D. "Modelling and computer simulation of the behaviour of solder paste in stencil printing for surface mount assembly." Thesis, University of Salford, 1998. http://usir.salford.ac.uk/14676/.

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One of the main challenges facing the electronics manufacturing industry in solder paste printing for ultra-fine pitch surface mount and flip-chip assembly is the difficulty in achieving consistent paste deposit volumes from pad-to-pad. At the very small aperture geometries required for ultra-fine pitch and flip chip assembly, flow properties of the paste becomes one of the dominant factors in the printing process. It is widely accepted that over 60% of assembly defects originate from the solder paste printing stage, and hence the urgent need for a better understanding of solder paste rheology, its behaviour during printing, and its impact on defect generation. This understanding is essential for achieving proper control of the printing process. This thesis presents the result of work on the modelling and computer simulation of solder paste behaviour during printing, and consists of three main parts. The first part concerns the modelling of paste behaviour in stencil printing using a vibrating squeegee. The performance of the vibrating squeegee is analysed and process models developed for predicting the ideal printing conditions. In the second part, the random packing of solder powder and the microstructure of solder paste are numerically simulated by applying Monte Carlo method. The effect particle size distributions on the paste microstructure is studied in this part. Based on the simulation results of the second part, the third part concerns the study of the effect of particle size distribution on the paste viscosity and the hydrodynamic interaction between adjacent particles during paste flow. A theoretical enhanced model for predicting the viscosity of dense suspensions such as solder pastes has been developed. This correlates relative viscosity with particle size distribution and with solid volume fraction of dense suspensions. The results of the work have wide applicability: firstly for solder paste manufacturers in optimising paste printing performance at the development stage and for stencil printing equipment manufacturers in specifying the ideal conditions for defect free printing. The simulation algorithm and the viscosity model are also applicable for a wide range of industrial processing applications; in particular metal or ceramic powder compaction, material surface coating, chemical or food material transportation.
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Jemai, Norchene. "Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité." Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0010/document.

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L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électrique et mécanique avec le niveau de packaging suivant. La technique de dépôt par sérigraphie de pâte à braser est récemment devenue pratique en raison de son adaptation aux alliages sans plomb. Cette méthode présente l'avantage d'un faible coût et d'une possible production à grande échelle. Nous avons donc choisi de développer cette technique afin d’obtenir des matrices de connexions électriques de dimensions comprises entre 50 μm et 100 μm, pour une pâte à braser de type Sn3.0Ag0.5Cu. Nous avons déterminé les paramètres de sérigraphie afin d’obtenir un minimum d’étalement de pâte pour un remplissage maximum des ouvertures du masque choisi en Ni-électroformé d’épaisseur 50μm : une vitesse de racle de 20mm/s et une vitesse de démoulage de 4mm/s sont par exemple à retenir pour une pâte de type 5. L’étude du masque de sérigraphie a conduit au choix d’ouvertures circulaires. Des formes de billes circulaires ont été obtenues pour des UBM (Under Bump Metallurgy) également circulaires, de diamètre ¼ et ½ le diamètre de l’ouverture du masque. L’optimisation du profil de refusion a permis de déterminer qu’un palier à 180°C, un TAL de 90s ou plus et une température maximale à 250°C favorisaient l’obtention de billes circulaires avec absence de vides. Pour une pâte de type 6, des billes de 60à 70μm de diamètre ont été obtenues pour des ouvertures de masque de 100μm. Une étude de fiabilité de ces billes à partir de tests de cisaillement et de l’analyse des IMC (composés intermétalliques) formés après refusion a permis de montrer que des UBM en Cr-Cu-Au, de diamètre égal à la moitié de l’ouverture du masque, permettaient d’assurer un meilleur maintien mécanique des billes
The semiconductor industry has continuously improved its products by increasing the density of integration resulting in an increasing of the I/Os, always with a low cost requirement. To obtain high-density and high-speed packaging, the Flip-Chip interconnection technology was introduced by IBM also called C4 (Control Collapse Chip Connection). Solder bumps have been widely used in electronic industry and were generally based on the Sn-Pb alloy, for its low melting point and good wetting property. Containing highly toxic element (Pb), Pb-Sn solder alloy has been banned. The ternary alloy Sn-Ag-Cu seems to be the best compromise, in fact it as physical and chemical characteristics equivalent to that of Sn-Pb.In this study we are interested to optimize stencil printing process and adjust it with the flip-chip technology, in order to obtain solder bumps which height is between 50µm and 100µm associated to pitches less than or equal to 200µm, using Sn-3.0Ag-0.5Cu solder paste. We have optimized the stencil printing parameters machine, the stencil apertures shape and size (circular shape and 50µm height, for a Ni-electroformed stencil). Spherical solder balls have been achieved with circular UBM (Under Bump Metallurgy), which diameter is ¼ and ½ the diameter of the stencil aperture. The reflow thermal profile is the key to the formation of a reliable solder bump. It must allow a homogeneous reflow for all particles of the metallic solder paste. We define a thermal profile with a Time above liquidus (TAL) of 90s, a temperature in soaking zone (Ts) of 180°C and a maximum temperature (Tmax) of 250°C. For type 6 solder pastes, balls of 60-70µm diameter have been obtained for 100µm stencil apertures.The quality of a solder joint is directly related to the adhesion of the solder ball to the substrate. Among the various methods of mechanical testing, shear testing is the most widely used to assess the strength of the attachment of beads to the substrate and determine the fragility of the ball at the interface caused by the intermetallic layer compounds (IMC) formed after the reflow step. We have shown that Cr-Cu-Au UBM, with a diameter equal to the half of the stencil aperture, ensure the mechanical adhesion of the balls
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Jakub, Miroslav. "Technologické postupy pájení pouzder QFN." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221072.

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This master´s thesis deals with QFN packages soldering and technology procedures optimization. The aim of theoretical part is description of QFN packages, their assembly and reflow soldering on PCB in HONEYWELL. The aim of the practical part is to propose a method of measuring temperature and optimizing the thermal profiles of selected PCB with QFN packages by using convection (HONEYWELL) and infrared (BUT) reflow ovens. Comparison and evaluation of thermal profiles for 3 production PCBś with QFN packages using solder paste AIM NC257-2 were realised. The main part of master´s thesis are appearance evaluation of solder joints, preparing microsection and measuring intermetallic layers thickness by using the optical and the scanning electron microscopes, analysation and study of QFN defects created during soldering proces. These tests were performed with 2 production PCB´s. Optimization of SPI and soldering technology procedures where were analyzed QFN packages were processed on one type of PCB. Interesting part of this diplomma thesis is creating of the 3D heat transfer model of QFN package during the reflow soldering in SolidWorks.
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Barajas, Leandro G. "Process Control in High-Noise Environments Using A Limited Number Of Measurements." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/7741.

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The topic of this dissertation is the derivation, development, and evaluation of novel hybrid algorithms for process control that use a limited number of measurements and that are suitable to operate in the presence of large amounts of process noise. As an initial step, affine and neural network statistical process models are developed in order to simulate the steady-state system behavior. Such models are vitally important in the evaluation, testing, and improvement of all other process controllers referred to in this work. Afterwards, fuzzy logic controller rules are assimilated into a mathematical characterization of a model that includes the modes and mode transition rules that define a hybrid hierarchical process control. The main processing entity in such framework is a closed-loop control algorithm that performs global and then local optimizations in order to asymptotically reach minimum bias error; this is done while requiring a minimum number of iterations in order to promptly reach a desired operational window. The results of this research are applied to surface mount technology manufacturing-lines yield optimization. This work achieves a practical degree of control over the solder-paste volume deposition in the Stencil Printing Process (SPP). Results show that it is possible to change the operating point of the process by modifying certain machine parameters and even compensate for the difference in height due to change in print direction.
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Lin, Chen-Yu, and 林珍猷. "Discovering Stencil Printing Quality Defects." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/16229399228224883494.

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碩士
樹德科技大學
經營管理研究所
98
台灣經濟的增長已經嚴重依賴於高科技廠商在製造集成電路和3C產品。計算機和電信產品的主要類別，通過建立電子裝配過程。表面貼裝技術（SMT ）是一個主要手段，生產各種電子產品。提升整體素質和能力的SMT組裝線為主體，以降低生產成本，提高質量保證水平，並成為台灣主要的挑戰保持住在競爭edge.SMT製成品的主要方法是產生各種電子產品。噴花是一個最重要的SMT裝配過程。根據行業報告，平均60 ％的焊接缺陷是由於噴花進程。 在本研究中，數據挖掘方法挖掘潛在的印刷缺陷模式。通過實驗設計（ DOE）的結構進行了數據收集利用決策樹算法（ C5.0 ） ，方差分析（方差）算法。此外，根據分類的缺陷，開發預測缺陷印刷parameters.The根據調查結果，可進一步提供電子製造商能夠加快行安裝程序，提高焊接質量。
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Books on the topic "Stencil printing"

1

Kelly, Jo'Anne. Terrific stencils & stamps. New York: Sterling Pub. Co., 1996.

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Hambleton, Laura. Pop out stencil art: Bugs. London: QED Publishing, 2015.

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Pop-out stencil art: Safari animals. London: QED Publishing, 2015.

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Stencil craft: Techniques for fashion, art & home. Cincinnati, Ohio: North Light Books, 2015.

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Stencils, prints and special effects. New York: Mondo Pub., 2007.

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Robins, Deri. Stencils, prints and special effects. London: QED, 2007.

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Printing by hand: A modern guide to printing with handmade stamps, stencils, and silk screens. New York: Stewart, Tabori & Chang, 2008.

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Bijutsukan, Tōkyō Kokuritsu Kindai. Gendai no katazome, kurikaesu patān: Contemporary stencil dyeing and printing, the repetition of patterns. [Tokyo]: Tōkyō Kokuritsu Kindai Bijutsukan Kōgeikan, 1994.

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ill, Mukhida Zul, ed. Stencils and screens. New York: Thomson Learning, 1993.

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Terrific stencils & stamps. New York: Sterling, 1996.

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Book chapters on the topic "Stencil printing"

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Chen, Fang, Kaikai Han, Kangwei Chang, Shixun Luan, Wenbo Dou, Li Ma, and Yingjie Ding. "Brief Design Requirements of Screen Printing Stencil." In Advances in Intelligent Systems and Computing, 13–19. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1843-7_2.

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Morris, John R., and Thaddeus Wojcik. "Screen and Stencil Printing Technology for Fine-Pitch Assembly." In Handbook of Fine Pitch Surface Mount Technology, 194–232. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4684-1437-0_6.

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Niu, Shilin, Zhengjun Bo, Le Cao, Lieqiang Li, Piao Wan, Hao Fu, and Jiangyou Yu. "Decision-Making of Stencil Cleaning for Solder Paste Printing Machine Based on Variable Threshold Sequence." In Communications in Computer and Information Science, 325–31. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2396-6_31.

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"EFFECT OF STENCIL APERTURE WALL FINISH AND SHAPE ON SOLDER PASTE PRINTING IN SMT." In Advances In Manufacturing Technology VIII, 784–89. CRC Press, 1994. http://dx.doi.org/10.1201/9781482272604-122.

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Conference papers on the topic "Stencil printing"

1

Krammer, Oliver, Laszlo-Milan Molnar, Laszlo Jakab, and Christian Klein. "Stencil deformation during stencil printing." In 2009 15th International Symposium for Design and Technology of Electronics Packages (SIITME 2009). IEEE, 2009. http://dx.doi.org/10.1109/siitme.2009.5407378.

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Cabahug, Elsie A., and Marlon D. Bartolo. "Solder Stencil Printing On Deep Cavity." In 2008 10th Electronics Packaging Technology Conference (EPTC). IEEE, 2008. http://dx.doi.org/10.1109/eptc.2008.4763512.

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Krammer, Oliver. "Finite volume modelling of stencil printing process." In 2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME). IEEE, 2014. http://dx.doi.org/10.1109/siitme.2014.6966998.

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Oliveira, Ricardo F., Nelson Rodrigues, José Carlos Teixeira, Duarte Santos, Delfim Soares, Maria F. Cerqueira, and Senhorinha F. C. F. Teixeira. "A Numerical Study of Solder Paste Rolling Process for PCB Printing." In ASME 2018 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/imece2018-88035.

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The increasing demand for electronic devices associated with the increasing competitiveness between enterprises, pushes towards process automation to decrease production costs. The reflow soldering has proven to be effective in this regard. This is composed by a series of steps or processes, such as: (a) stencil printing, (b) component placement and (c) reflow oven soldering. Each process has its specific traits that contribute to the overall process efficiency. The present study is directed towards process (a), which includes the rolling of the solder paste over the stencil surface, followed by the subsequent filling of the stencil apertures. Several parameters influence the solder paste behaviour and thus the effectiveness of the rolling process. This work focuses on the solder paste non-Newtonian viscosity properties, with the solder paste presenting a thixotropic behaviour, necessary for the filling of the stencil apertures. Although the increase in the squeegee velocity causes extra shear in the solder paste and consequently lower viscosity, the excess of velocity may cause defects in the aperture filling process. In addition, during the rolling process, air may become entrapped in the solder paste. The complexity of this process is addressed by numerical simulation, in particular, using the work-package ANSYS to study the solder paste progress, during the rolling process, as well as the parameters influencing it. The fluid flow simulation is solved using the solver FLUENT®, a simplified 2D domain with real case dimensions, a transient prediction of the viscosity, which is a function of the solder paste solicitation, and finally by using the Volume of Fluid (VOF) method to track the solder-air interface boundary. Dynamic meshing methods are also employed to replicate the movement of the squeegee wall, in its task to push the solder paste tumble over the stencil. This study enlightens the role played by the printing velocity in the stencil aperture filling, a logarithm correlation can be found between them. It was found that lower print velocities provide better results than higher speeds. It was observed that the back tip of the squeegee blade causes a partial removal of the solder paste from the aperture, which is higher for faster print processes. An analysis of the filling process over time concluded that, independently of the printing velocity, 90% of the filling occurs in the first quarter of the process.
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Whitmore, Mark, and Jeff Schake. "Screen and stencil printing processes for wafer backside coating." In 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT). IEEE, 2008. http://dx.doi.org/10.1109/iemt.2008.5507863.

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Kaneko, Tsukasa, Kazuki Iwata, and Makiko Kobayashi. "Sol-gel composite film fabrication by paint stencil printing." In 2014 IEEE International Ultrasonics Symposium (IUS). IEEE, 2014. http://dx.doi.org/10.1109/ultsym.2014.0239.

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Zhao, Fei, and Yuan-Lan Dang. "A study of screen/stencil printing on LTCC substrate." In 2015 International Workshop on Materials, Manufacturing Technology, Electronics and Information Science. WORLD SCIENTIFIC, 2016. http://dx.doi.org/10.1142/9789813109384_0002.

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He, Xi, Ziyu Liu, Jian Cai, Yu Chen, Lin Tan, and Qian Wang. "Characterization of stencil printing parameters for fine pitch wafer bumping." In 2014 15th International Conference on Electronic Packaging Technology (ICEPT). IEEE, 2014. http://dx.doi.org/10.1109/icept.2014.6922601.

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Yang, Jimmy, Jay Cy Huang, Vincent Lee, Jojo Tsai, J. L. Ku, K. C. Li, Ander Hsieh, and Cheng Yu Chen. "Stencil evaluation of ultra fine pitch solder paste printing process." In 2010 5th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2010. http://dx.doi.org/10.1109/impact.2010.5699642.

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Mu-Chun Wang, Zhen-Ying Hsieh, Kuo-Shu Huang, Chiao-Hao Tu, Shuang-Yuan Chen, and Heng-Sheng Huang. "A study to stencil printing technology for solder bump assembly." In 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2009. http://dx.doi.org/10.1109/impact.2009.5382134.

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Reports on the topic "Stencil printing"

1

Martens, Niles. The paper stencil method of silk screen printing. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.701.

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