Academic literature on the topic 'Splitgate'
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Journal articles on the topic "Splitgate"
Li Manni, Giovanni, Dongxia Ma, Francesco Aquilante, Jeppe Olsen, and Laura Gagliardi. "SplitGAS Method for Strong Correlation and the Challenging Case of Cr2." Journal of Chemical Theory and Computation 9, no. 8 (July 5, 2013): 3375–84. http://dx.doi.org/10.1021/ct400046n.
Full textVogiatzis, Konstantinos D., Giovanni Li Manni, Samuel J. Stoneburner, Dongxia Ma, and Laura Gagliardi. "Systematic Expansion of Active Spaces beyond the CASSCF Limit: A GASSCF/SplitGAS Benchmark Study." Journal of Chemical Theory and Computation 11, no. 7 (June 5, 2015): 3010–21. http://dx.doi.org/10.1021/acs.jctc.5b00191.
Full textMacdonald, Stuart J., Tomi Pastinen, and Anthony D. Long. "The Effect of Polymorphisms in theEnhancer of splitGene Complex on Bristle Number Variation in a Large Wild-Caught Cohort ofDrosophila melanogaster." Genetics 171, no. 4 (September 2, 2005): 1741–56. http://dx.doi.org/10.1534/genetics.105.045344.
Full textWu, Fengming, Bowen Deng, Na Xiao, Tao Wang, Yining Li, Rencong Wang, Kai Shi, Dong-Gen Luo, Yi Rao, and Chuan Zhou. "A neuropeptide regulates fighting behavior in Drosophila melanogaster." eLife 9 (April 21, 2020). http://dx.doi.org/10.7554/elife.54229.
Full textDissertations / Theses on the topic "Splitgate"
Melul, Franck. "Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.
Full textThe objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications