Dissertations / Theses on the topic 'Speculative Architecture'
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Xekalakis, Polychronis. "Mixed speculative multithreaded execution models." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/3282.
Full textLindskog, Ellen. "Danvikens Hospital - A speculative investigation." Thesis, KTH, Arkitektur, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-298799.
Full textWeate, Jeremy. "Phenomenology and difference : the body, architecture and race." Thesis, University of Warwick, 1998. http://wrap.warwick.ac.uk/2472/.
Full textLi, Wentong. "High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware." Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc5150/.
Full textLi, Wentong Kavi Krishna M. "High performance architecture using speculative threads and dynamic memory management hardware." [Denton, Tex.] : University of North Texas, 2007. http://digital.library.unt.edu/permalink/meta-dc-5150.
Full textWeingarten, Lauren Ariel. "Building on the edge of reason : the Institute for Speculative Science, M.I.T." Thesis, Massachusetts Institute of Technology, 1989. http://hdl.handle.net/1721.1/79003.
Full textThis thesis sprang from a fascination with and respect for speculative thought in science. One need walk no further than down the "infinite corridor" to feel the pulse of experimentation that has earned M.I.T. the reputation of being one of the principal research institutes of the world. But, even with the commitment to research found at M.I.T. market demands point toward specialization. This creates an environment where speculative science in its classic sense cannot occur. It is the aim of this project to reconnect contemporary higher science with ancient ideas of a unified world view. To do this, the scientists at M.I.T. will be provided with a physically different environment from the everyday scientific workplace, with its gadgetry and budgetary constraints, if even for a short time. The site I propose to locate the Institute for Speculative Science is removed from Boston but is close enough to remain in the scientists' frame of reference. Located between Quincy and Thompson Island in the Boston Harbor, the institute for Speculative Science builds on the tension between built and natural states: urban to exurban; mainland to island; rock to water. This project will occupy the space between the mainland (Quincy) and surrounding islands, currently treated as an orphan of the big city. From the vantage point of the Institute for Speculative Science, you can see the Boston skyline but Boston cannot see you. You walk on a natural and wild beach, but this beach is littered with debris, relics of Boston's industrial recent past. The models and drawings in this book are scaled representations of the proposed project, they are how ever drawn and made as worlds in their own right which the participant in this book can experience. To communicate the idea of a building on the edge of reason, I've looked to bring to light a project that you feel before you understand.
by Lauren Ariel Weingarten.
M.Arch.
ESTILL, ALEXANDER CLAYTON. "VITRUVIAN DELIGHT: CUSTOMIZATION WITHIN THE SPECULATIVE MODEL." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129233879.
Full textKhan, Salman. "Putting checkpoints to work in thread level speculative execution." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4676.
Full textIoannou, Nikolas. "Complementing user-level coarse-grain parallelism with implicit speculative parallelism." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/7900.
Full textDuan, Kewei. "Resource-oriented architecture based scientific workflow modelling." Thesis, University of Bath, 2016. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.698986.
Full textJimborean, Alexandra. "Adapting the polytope model for dynamic and speculative parallelization." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00733850.
Full textHarmon, Justin L. "The Normative Architecture of Reality: Towards an Object-Oriented Ethics." UKnowledge, 2016. http://uknowledge.uky.edu/philosophy_etds/9.
Full textAltringer, Beth. "The intended and actual impacts of mega-events : an international comparative study on mega-event hosting and a speculative review of South Africa's preparations for the 2010 Football World Cup." Master's thesis, University of Cape Town, 2006. http://hdl.handle.net/11427/5602.
Full textMadriles, Gimeno Carles. "Mitosis based speculative multithreaded architectures." Doctoral thesis, Universitat Politècnica de Catalunya, 2012. http://hdl.handle.net/10803/124709.
Full textAbeydeera, Maleen Hasanka (Weeraratna Patabendige Maleen Hasanka). "Optimizing throughput architectures for speculative parallelism." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111930.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (pages 57-62).
Throughput-oriented architectures, like GPUs, use a large number of simple cores and rely on application-level parallelism, using multithreading to keep the cores busy. These architectures work well when parallelism is plentiful but work poorly when its not. Therefore, it is important to combine these techniques with other hardware support for parallelizing challenging applications. Recent work has shown that speculative parallelism is plentiful for a large class of applications that have traditionally been hard to parallelize. However, adding hardware support for speculative parallelism to a throughput-oriented system leads to a severe pathology: aborted work consumes scarce resources and hurts the throughput of useful work. This thesis develops a technique to optimize throughput-oriented architectures for speculative parallelism: tasks should be prioritized according to how speculative they are. This focuses resources on work that is more likely to commit, reducing aborts and using speculation resources more efficiently. We identify two on-chip resources where this prioritization is most likely to help, the core pipeline and the memory controller. First, this thesis presents speculation-aware multithreading (SAM), a simple policy that modifies a multithreaded processor pipeline to prioritize instructions from less speculative tasks. Second, we modify the on-chip memory controller to prioritize requests issued by tasks that are earlier in the conflict resolution order. We evaluate SAM on systems with up to 64 SMT cores. With SAM, 8-threaded in-order cores outperform single-threaded cores by 2.41 x on average, while a speculation-oblivious policy yields a 1.91 x speedup. SAM also reduces wasted work by 43%. Unlike at the core, we find little performance benefit from prioritizing requests at the memory controller. The reason is that speculative execution works as a very effective prefetching mechanism, and most requests, even those from tasks that are ultimately aborted, do end up being useful.
by Weeraratna Patabendige Maleen Hasanka Abeydeera.
S.M.
Runberger, Jonas. "Architectural Prototypes II : Reformations, Speculations and Strategies in the Digital Design Field." Doctoral thesis, KTH, Projektkommunikation, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-95188.
Full textQC 20120528
Wamhoff, Jons-Tobias. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-163250.
Full textBlack, Michael David. "Applying perceptrons to speculation in computer architecture." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/6725.
Full textThesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
Subramanian, Suvinay. "Architectural techniques to unlock ordered and nested speculative parallelism." Thesis, Massachusetts Institute of Technology, 2018. https://hdl.handle.net/1721.1/121729.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (pages 129-144).
Current multicores suffer from two major limitations: they can only exploit a fraction of the parallelism available in applications and they are very hard to program. This is because they are limited to programs with coarse-grained tasks that synchronize infrequently. However, many applications have abundant parallelism when divided into small tasks (of a few tens to hundreds of instructions each). Current systems cannot exploit this fine-grained parallelism because synchronization and task management overheads overwhelm the benefits of parallelism. This thesis presents novel techniques that tackle the scalability and programmability issues of current multicores. First, Swarm is a parallel architecture that makes fine-grained parallelism practical by leveraging order as a general synchronization primitive. Swarm programs consist of tasks with programmer-specified order constraints. Swarm hardware provides support for fine-grained task management, and executes tasks speculatively and out of order to scale. Second, Fractal extends Swarm to harness nested speculative parallelism, which is crucial to scale large, complex applications and to compose parallel speculative algorithms. Third, Amalgam makes more efficient use of speculation resources by splitting and merging address set signatures to create fixed-size units of speculative work. Amalgam can improve performance and reduce implementation costs. Together, these techniques unlock abundant fine-grained parallelism in applications from a broad set of domains, including graph analytics, databases, machine learning, and discrete-event simulation. At 256 cores, our system is 40x -512x faster than a single core system and outperforms state-of-the-art software-only parallel algorithms by one to two orders of magnitude. Besides achieving near-linear scalability, the resulting programs are almost as simple as their sequential counterparts, as they do not use explicit synchronization.
by Suvinay Subramanian.
Ph. D.
Ph.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Dou, Jialin. "A compiler cost model for speculative multithreading chip-multiprocessor architectures." Thesis, University of Edinburgh, 2006. http://hdl.handle.net/1842/24532.
Full textYiapanis, Paraskevas. "High performance optimizations in runtime speculative parallelization for multicore architectures." Thesis, University of Manchester, 2013. https://www.research.manchester.ac.uk/portal/en/theses/high-performance-optimizations-in-runtime-speculative-parallelization-for-multicore-architectures(1d980957-a08d-49f0-8f7f-d5c35bae38b8).html.
Full textPerais, Arthur. "Increasing the performance of superscalar processors through value prediction." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S070/document.
Full textAlthough currently available general purpose microprocessors feature more than 10 cores, many programs remain mostly sequential. This can either be due to an inherent property of the algorithm used by the program, to the program being old and written during the uni-processor era, or simply to time to market constraints, as writing and validating parallel code is known to be hard. Moreover, even for parallel programs, the performance of the sequential part quickly becomes the limiting improvement factor as more cores are made available to the application, as expressed by Amdahl's Law. Consequently, increasing sequential performance remains a valid approach in the multi-core era. Unfortunately, conventional means to do so - increasing the out-of-order window size and issue width - are major contributors to the complexity and power consumption of the chip. In this thesis, we revisit a previously proposed technique that aimed to improve performance in an orthogonal fashion: Value Prediction (VP). Instead of increasing the execution engine aggressiveness, VP improves the utilization of existing resources by increasing the available Instruction Level Parallelism. In particular, we address the three main issues preventing VP from being implemented. First, we propose to remove validation and recovery from the execution engine, and do it in-order at Commit. Second, we propose a new execution model that executes some instructions in-order either before or after the out-of-order engine. This reduces pressure on said engine and allows to reduce its aggressiveness. As a result, port requirement on the Physical Register File and overall complexity decrease. Third, we propose a prediction scheme that mimics the instruction fetch scheme: Block Based Prediction. This allows predicting several instructions per cycle with a single read, hence a single port on the predictor array. This three propositions form a possible implementation of Value Prediction that is both realistic and efficient
McKellar, Elizabeth. "Architectural practice for speculative building in late seventeenth century London." Thesis, Royal College of Art, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.281699.
Full textChiu, Virginia. "Architectural support for commutativity in hardware speculation." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106029.
Full textThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 57-60).
Hardware speculative execution schemes (e.g., hardware transactional memory (HTM)) enjoy low run-time overheads but suffer from limited concurrency because they detect conflicts at the level of reads and writes. By contrast, software speculation schemes can reduce conflicts by exploiting that many operations on shared data are semantically commutative: they produce semantically equivalent results when reordered. However, software techniques often incur unacceptable run-time overheads. To bridge this dichotomy, this thesis presents CommTM, an HTM that exploits semantic commutativity. CommTM extends the coherence protocol and conflict detection scheme to allow multiple cores to perform user-defined commutative operations to shared data concurrently and without conflicts. CommTM preserves transactional guarantees and can be applied to arbitrary HTMs. This thesis details CommTM's implementation and presents its evaluation. The evaluation uses a series of micro-benchmarks that covers commonly used operations and a suite of full transactional memory applications. We see that CommTM scales many operations that serialize on conventional HTMs, such as counter increments, priority updates, and top-K set insertions. As a result, at 128 cores on full applications, CommTM outperforms a conventional eager-lazy HTM by up to 3.4x and reduces or eliminates aborts.
by Virginia Chiu.
M. Eng.
Abou, Dib Marwan Joseph. "Design for speculation : volatile, temporal, in-transit." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/103455.
Full textThesis: S.M. in Real Estate Development, Massachusetts Institute of Technology, Program in Real Estate Development in conjunction with the Center for Real Estate, 2016.
Cataloged from PDF version of thesis.
Includes bibliographical references (page 97).
The thesis project is a reaction to the alarming rate of building and development depreciation caused by foreign investment in the Middle Eastern city of Dubai. The intervention looks at how architects, developers, and planners can counteract this phenomenon by designing for speculation in order to mitigate future crises or successes. Understanding the economic terms of "creative destruction" and "planning obsolescence" are imperative to help structure such a proposal Though such terms were attributed to industrial products such as cars and electronics, they are today applicable in the context of Dubai and similar cities worldwide. Architecture and real estate products have become victim to this capitalist phenomenon. The project is framed as an architectural reaction to the world's increasing capability to make and accumulate in conjunction with a growing desire to be transient and global. Has architecture become a mere toy product which can be changed around as it become obsolete? Rather than be destroyed, how can architecture morph and be updated into something new? Architects are not in complete control of consumer wants and needs; these, too, continue to change at a dynamic pace. I argue that a synchronized system that can reflect flexibility is integral in order to maintain equilibrium in the urban economic model today The project design is an infrastructure capable of harnessing capital inflow and outflow while withstanding volatility, temporality and a population in-transit Dubai is the core case-study and the thesis explores how such a generic system can adapt to cities such as Miami, New York City and Juba.
by Marwan Joseph Abou Dib.
M. Arch. in Real Estate Development
S.M. in Real Estate Development
Powers, Aaron. "Stimulation, speculation, simulation : the architecture of the captured city that the corporation gave us." Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/129933.
Full textCataloged from student-submitted thesis.
Includes bibliographical references (pages 114-115).
For thousands of years, architecture built itself from a history of its own understanding of itself. A retracing over time, architecture was inherited from its past. Over time, sets of ideals were built collectively, with the city as its manifesto. It could be argued that the architecture built was in response to an architecture that already existed. the production of making architecture made cities, and further, showcased architecture as a way of thinking. Diagrammatic thinking produces diagrammatic architecture. Orthographic thinking produced orthographic architecture [1]. Machines have learned to compound a retracing of time through creating systems of algorithms that recursively produce patterns of understanding through their recordings of human behavior. The model is based on recording the past to predict the future. Increasingly, our cities have been non-stop recorded through various and ubiquitous sensing devices. The city is then re-represented afterward, through the eyes and interpretation of the machine. Or rather, by the eyes of the machine by the men who made the machine see the way they want the machine to see, building a proxy city, a representation of the real world, to help make choices in the distant and near future. How might we begin to imagine architecture as collective intelligence within this new system? Imagining architecture as a type of metadata. Mined through vision, camera, surveillance technology, connecting various strands of metadata produced surveillance capitalisms abilities. Imagine other connections mining this figural metadata could produce for a second just processing the knowns and unknowns, speculating on the possible city in Rumsfeldian ways, knowing from these systems, it is that they have the capabilities to find patterns and order not before seen. When past behavior is the basis of predicting future behavior, how might we revisit the city that was, to forge the city to come?
by Aaron Powers.
M. Arch.
M.Arch. Massachusetts Institute of Technology, Department of Architecture
Pilla, Mauricio Lima. "RST: Reuse through Speculation on Traces." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2004. http://hdl.handle.net/10183/5888.
Full textIn this thesis, we present a novel approach to combine both reuse and prediction of dynamic sequences of instructions called Reuse through Speculation on Traces (RST). Our technique allows the dynamic identification of instruction traces that are redundant or predictable, and the reuse (speculative or not) of these traces. RST addresses the issue, present on Dynamic Trace Memoization (DTM), of traces not being reused because some of their inputs are not ready for the reuse test. These traces were measured to be 69% of all reusable traces in previous studies. One of the main advantages of RST over just combining a value prediction technique with an unrelated reuse technique is that RST does not require extra tables to store the values to be predicted. Applying reuse and value prediction in unrelated mechanisms but at the same time may require a prohibitive amount of storage in tables. In RST, the values are already stored in the Trace Memoization Table, and there is no extra cost in reading them if compared with a non-speculative trace reuse technique. . The input context of each trace (the input values of all instructions in the trace) already stores the values for the reuse test, which may also be used for prediction. Our main contributions include: (i) a speculative trace reuse framework that can be adapted to different processor architectures; (ii) specification of the modifications in a superscalar, superpipelined processor in order to implement our mechanism; (iii) study of implementation issues related to this architecture; (iv) study of the performance limits of our technique; (v) a performance study of a realistic, constrained implementation of RST; and (vi) simulation tools that can be used in other studies which represent a superscalar, superpipelined processor in detail. In a constrained architecture with realistic confidence, our RST technique is able to achieve average speedups (harmonic means) of 1.29 over the baseline architecture without reuse and 1.09 over a non-speculative trace reuse technique (DTM).
Kully, Deborah Grace. "Speculating on architecture : morality, the new real estate, and the bourgeois apartment industry in late nineteenth-century France." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/63061.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 216-232).
The topic of architecture as a commodity-something that can be possessed and traded-has been largely ignored within the discipline of architectural history, or even written off altogether as an inevitable consequence of modem capitalism. But the history of the commodification of architecture is by no means as simple as it may seem. It has its roots in Haussmann's Paris, and the speculative property market of the 1860s, where we see, for the first time, a complex intermingling of new mortgage structures and residential typologies, the use of standardization, and the proliferation of discourses concerning apartment decoration. The project also treats reactions expressed by architects, aesthetic theorists, and religious and political figures over the course of the Third Republic against speculation practices and their architectural effects. The changes brought by property's increased circulation-the very idea of apartments designed for unknown future occupants-were compounded by the perception of a real estate market held in the grips of commodity culture. The possibility that anyone could own property was unsettling for some political and religious authorities; perhaps even more so was the sense of an assault on the way in which property had traditionally stood as a representation of individuality. Speculative architecture brought about a separation of the subject (the particular owner of an apartment) from its object (the apartment unit now rendered ubiquitous). The powerful critique of modem capitalism and the ostensive ill effects on private life that emerged from all of this was bound up in liberal and Catholic ideologies, as I argue in my dissertation. I look at a set of figures from vastly different professions who, perforce, collectively developed and implemented rules governing finances, architecture, decoration, and, ultimately, human conduct. These include developers like the Saint-Simonien Emile Pdreire, whose experimental Credit Mobilier sponsored standard models for residential architecture, democratized credit, and underwrote the design and construction of thousands of new apartments. These also include taste-makers like Charles Blanc, director of the Academie des beaux-arts, whose works included decoration manuals. And finally, these include politicians such as Frederic Le Play, the Catholic modernist and proto-sociologist who insisted on the connection between private property and morality, and Jules Simon, the conservative republican who linked the security of the family to that of the nation state. The reactionary moralization of design, to be detected in Catholic dogma, metaphysical philosophy, and the republican politics of the time, stands as one of the great unacknowledged precedents for the proselytizing ideology of architectural modernism at the dawn of the twentieth century.
by Deborah Grace Kully.
Ph.D.
Kalaitzidis, Kleovoulos. "Advanced speculation to increase the performance of superscalar processors." Thesis, Rennes 1, 2020. http://www.theses.fr/2020REN1S007.
Full textEven in the multicore era, making single cores faster is paramount to achieve high- performance computing, given the existence of programs that are either inherently sequential or expose non-negligible sequential parts. Sequential performance has been essentially improving with the scaling of the processor structures that enable instruction-level parallelism (ILP). However, as modern microarchitectures continue to extract more ILP by employing larger instruction windows, true data dependencies remain a major performance bottleneck. Value Prediction (VP) and Load-Address Prediction (LAP) are two developing techniques that allow to overcome this obstacle and harvest more ILP by enabling the execution of instructions in a data-wise speculative manner. This thesis proposes mechanisms that are related with VP and LAP and lead to effectively higher performance improvements. First, VP is examined in an ISA-aware manner, that discloses the impact of certain ISA particularities on the anticipated speedup. Second, a novel binary-based VP model is introduced, namely VSEP, that allows to exploit certain value patterns that although they are encountered frequently, they cannot be captured by previous works. VSEP improves the obtained speedup by 19% and also, by virtue of its structure, it mitigates the cost of predicting values wider than 64 bits. By adapting this approach to perform LAP allows to predict the memory addresses of 48% of the committed loads. Eventually, a microarchitecture that leverages carefully this LAP mechanism can execute 32% of the committed loads early
Wamhoff, Jons-Tobias [Verfasser], Christof [Akademischer Betreuer] Fetzer, and Pascal [Akademischer Betreuer] Felber. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures / Jons-Tobias Wamhoff. Gutachter: Christof Fetzer ; Pascal Felber. Betreuer: Christof Fetzer." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://d-nb.info/106909675X/34.
Full textLoew, Jason. "Quantifying the impacts of disabling speculation and relaxing the scheduling loop in multithreaded processors." Diss., Online access via UMI:, 2006.
Find full textPerombelon, Brice Désiré Jude. "Prioritising indigenous representations of geopower : the case of Tulita, Northwest Territories, Canada." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:71e14c26-d00a-4320-a385-df74715c45c8.
Full textKainth, Haresh S. "A data dependency recovery system for a heterogeneous multicore processor." Thesis, University of Derby, 2014. http://hdl.handle.net/10545/313343.
Full textTonchev, Anton. "Door, Passage, Courtyard: Shifting Perspective in Gamla Stan." Thesis, KTH, Arkitektur, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-281363.
Full textChuzeville, Sylvain. "Vie, œuvre et carrière de Jean-Antoine Morand, peintre et architecte à Lyon au XVIIIe." Thesis, Lyon 2, 2012. http://www.theses.fr/2012LYO20076/document.
Full textBorn in 1727, Jean-Antoine Morand is 14 years old when he embraces an artistic career, following his father’s death. Having settled down in Lyon, he establishes his own painter’s workshop in 1748. Receiving public and private commissions and working for the theatre on a regular basis, he specializes in trompe l’œil painting and stage-setting, including machinery. In the late 1750s, spurred on by Soufflot, he turns to architecture and city-planning, as various aspects of his previous career could have prompted him to.As an autodidactic architect, Morand suffers from a lack of legitimacy against which he pursues public recognition. But his successes, which include the building of a privately-owned bridge across the Rhône, aren’t enough. Morand’s career is torn between entrepreneurial pride and his longing for tenure. His public image is marred by the alleged opposition between land speculation and the defense of public good. This concerns mostly his great work, a project for the extension of Lyon on the left bank of the Rhône, included in a circular general city plan.Morand hasn’t built much and very little remains of his pictorial work. This thesis is based on an extensive private archive that allows us to explore this otherwise unsung architect’s intentions, relations and psychology
Svahn, Garreau Hélène. "I originalets tjänst : Om framställandet och bevarandet av kalkmåleri i svenska kyrkorum mellan 1850 och 1980." Doctoral thesis, KTH, Arkitekturens historia och teori, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-171078.
Full textForskningsfinansiärer: FoU-medel: Riksantikvarieämbetet, Brandförsäkringsverkets stiftelse för bebyggelsehistorisk forskning, Elna Bengtsssons fond och Tyréns stiftelse.
Ett läsår på Columbia University kunde genomföras med stöd av Fulbright Commission. Erik & Lily Philipsons minnesfond och Axelson Johnsons stiftelse.
Valiukas, Tadas. "Kompiliatorių optimizavimas IA-64 architektūroje." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2014. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2009~D_20140701_180746-19336.
Full textAfter performance optimization of traditional architectures began to reach their limits, Intel corporation started to develop new architecture based on EPIC – Explicitly Parallel Instruction Counting. This main feature allowed up to six instructions to be executed in single CPU cycle. Also this architecture includes more features, which allowed efficient solution of traditional architectures code optimization problems. However for long time code optimization algorithms have been improved for traditional architectures only, as a result those algorithms should be adopted to new architecture. One of the ways to do that – exploration of internal compilers parameters, which are responsible for code optimizations. That is the primary target of this work and in order to reach it the features of the IA-64 architecture and impact to execution performance must be explored using real-life code examples. Tests results may be used later for internal parameters selection and further exploration of these parameters values by using special compiler performance testing benchmarks. The set of those new values could be tested with real life applications in order to prove efficiency of IA-64 architecture features.
Hung, Ming-Yu, and 洪明郁. "Compiler supports for Optimizing Speculative Multithreading Architecture." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/34974431939945341349.
Full text國立清華大學
資訊工程學系
92
By the progress of VLSI technology, there are more and more features added in a single processor. Speculative multithreading (SpMT) architecture is one of them. It has speculative function and multithreading feature in a processor, and it can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threads in parallel that are extracted from a sequential program. However, performance degradation might occur if the threads are highly dependent. A recovery mechanism will be activated when a speculative thread violates the sequential semantics. The recovery action usually incurs a very high penalty, because it must squash all living threads before doing recovery code. Therefore, it is essential for SpMT to quantify the degree of dependences and to turn off speculation if the degree of loop carried dependence is over a certain threshold. This paper presents a technique that quantitatively computes loop carried dependences and such information can be used to determine if loop iterations should be executed in parallel by speculative threads or not. This technique can be broken into two steps. First, probabilistic points-to analysis is performed to estimate the probabilities of points-to relationships in case there are pointer references in programs. That way, the degree of dependences between loop iterations is computed quantitatively. Second, experimental results show compiler-directed thread-level speculation based on the information gathered by this technique can guarantee the architecture to always do a right decision on the experimental platform, SImulator for Multithreaded Computer Architectures (SIMCA). SIMCA be modeled as SpMT architecture by inserting SIMCA specific instructions.
Chen, HsuanYu, and 陳宣宇. "Speculative Execution of Non-Blocking Multithreaded Architecture." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/77229340248370372217.
Full text輔仁大學
資訊工程學系
95
In the past decade, CPU speed has been increasing linearly, but the memory access has not kept up with this improvement. In the modern architectures if we want to increase the processor performance, we need to increase the ILP. TLP has been complemented to ILP, in multithreaded architectures. In this thesis, we present an evaluation of modern processor that decouples memory accesses to alleviate the gap, uses a non-blocking multithreaded together with the dataflow paradigm. We provide both clock cycles per instruction (CPI) and instructions per clock cycle (IPC) evaluation of a multithreaded architecture by using speculative execution. Current architectural paradigm shift is from high performance to high-throughput processing, using on chip processors or by using distributed components. Main reasons to experiment speculative execution is by the witnessing of the diminishing potential of the existing techniques to extract parallelism from single program and current technology trends that allow us to execute multiple independent threads. The existing architecture has been evaluated previously and shown that it has outperformed MIPS like architectures. In this particular study, we try to implement speculative execution of a multithread on this unique architecture. We have used hand coded examples for speculative and non-speculative execution. Using few benchmarks, we present the IPC and CPI improvement over non-speculative execution. Some of the benchmarks we used include I-structure that is unique to dataflow architecture and other benchmarks are without I-structure. All the benchmarks have shown speedup of about 1.3. Without speculation we can only divide the programs conservatively into non-speculative threads, whose mutual exclusion and independence is guaranteed. In a speculative execution, it divides the thread aggressively and the mutual exclusion and dependence are guaranteed to be parallel. Thus it can increase the performance of any program with high probability. That has been proved as a result of this research using in a non-blocking multithreaded architecture. We have used different architectural simulators to prove the existing performance improvement of speculative execution.
TSENG, YU-MING, and 曾淯銘. "Loop Transformation and Instruction Scheduling Techniques for Timing Speculative Architecture." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/as8mgc.
Full text國立中正大學
資訊工程研究所
106
Traditional processor design incorporates voltage and frequency guardbands to ensure correct execution of operations under worst-case conditions. As transistor density increases and manufacturing processes improve, increasingly costly guardbands are required to deal with the impacts of environmental variability. The use of timing speculation can relax the tight constraint for worst-case design by allowing occasional errors, which are detected and corrected later by an error resilience mechanism. However, a program's performance may suffer owing to timing errors. The thesis consists of three works. First, we analyze program behaviors and observe what influence the number of timing errors through a simulator. Second, we propose a loop transformation technique for Timing Speculative Architectures to reduce up to 37% the number of timing errors. Third, we propose an instruction scheduling technique to rearrange the instructions in the programs that make better cooperation between Timing Speculative Architecture and Adaptive Voltage Scaling technique and reduce up to 45% the number of timing errors. These proposed techniques are implemented in the LLVM compiler infrastructure to generate the optimized programs automatically.
"Adaptive modern and speculative urbanism: the architecture of the Crédit Foncier d'Extrême-Orient (C.F.E.O.) in Hong Kong and China's treaty ports, 1907-1959." 2013. http://library.cuhk.edu.hk/record=b5884271.
Full textThesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references (leaves ).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstracts also in Chinese.
Yuan, Yi. "A microprocessor performance and reliability simulation framework using the speculative functional-first methodology." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4848.
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Wamhoff, Jons-Tobias. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures." Doctoral thesis, 2014. https://tud.qucosa.de/id/qucosa%3A28598.
Full textRanganathan, Nitya. "Control flow speculation for distributed architectures." 2009. http://hdl.handle.net/2152/6586.
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Dodd, Samuel Tommy. "Merchandising the postwar model house at the Parade of Homes." Thesis, 2009. http://hdl.handle.net/2152/ETD-UT-2009-08-345.
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Carlerbäck, Johansson Linnea. "The living square : Speculating publicness." Thesis, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-171712.
Full textChen, Pei-yuan, and 陳沛源. "Front-End Policy based on Speculation Condition for Simultaneous Multithreading Architecture." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/vegfgr.
Full text大同大學
資訊工程學系(所)
95
For modern wide-issue superscalar processors, high performance instruction fetch unit is the key component to keep the powerful execution engine operating in full speed. The performance measurement to evaluate a front-end mechanism includes both the instruction delivery rate and speculation accuracy. That means a good front-end engine should be able to fetch and dispatch massive instructions on the right execution path, in a reasonable clock cycle time. Things may be a little different in Simultaneous Multithreading (SMT) architecture because there are multiple active contexts inside the CPU. If we can extract some information about future speculation conditions of each thread, the front-end fetch engine can then prefer threads with highly predictable execution path to avoid resource or energy waste on mis-speculative routes. In this paper, we focus on improving the front-end engine of SMT processor. We present a supplementary structure called Sequential Trace Table (STT) to provide a look-ahead into the future speculating conditions of each thread, and use the information to help improving fetch prioritizing policies.
Khosrow-Khavar, Farzad. "Assigning cost to branches for speculation control in superscalar processors." 2005. http://hdl.handle.net/1828/580.
Full textKelly, Daniel R. "Arithmetic data value speculation." Thesis, 2011. http://hdl.handle.net/2440/70234.
Full textThesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2011
(11132985), Thamir Qadah. "High-performant, Replicated, Queue-oriented Transaction Processing Systems on Modern Computing Infrastructures." Thesis, 2021.
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