Relevant bibliographies by topics / Spartan-7

Academic literature on the topic 'Spartan-7'

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Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "Spartan-7"

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Lockwood, Thornton. "Servile Spartans and Free Citizen-soldiers in Aristotle’s Politics 7–8." Apeiron 51, no. 1 (January 26, 2018): 97–123. http://dx.doi.org/10.1515/apeiron-2016-0055.

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Abstract In the last two books of the Politics, Aristotle articulates an education program for his best regime in contrast to what he takes to be the goal and practices of Sparta’s educational system. Although Aristotle never refers to his program as liberal education, clearly he takes its goal to be the production of free male and female citizens. By contrast, he characterizes the results of the Spartan system as ‘crude’ (φορτικός), ‘slavish’ (ἀνδραποδώδης), and ‘servile’ (βάναυσος). I argue that Aristotle’s criticisms of Spartan education elucidate his general understanding of Sparta and provide an interpretative key to understanding Politics 7–8. But although Aristotle contrasts the goals and methods of Spartan education with that of his own best regime, the citizens of his best regime are more like Spartan citizen-soldiers than Athenian participatory-citizens.
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Rashid, Muhammad, Harish Kumar, Sikandar Zulqarnain Khan, Ismail Bahkali, Ahmed Alhomoud, and Zahid Mehmood. "Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol." Applied Sciences 12, no. 8 (April 18, 2022): 4091. http://dx.doi.org/10.3390/app12084091.

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This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.
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Rashid, Muhammad, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, and Amer Aljaedi. "A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography." Electronics 10, no. 21 (November 4, 2021): 2698. http://dx.doi.org/10.3390/electronics10212698.

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.
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Shuster, Amy L. "The Problem of the Partheniae in Aristotle’s Political Thought." Polis: The Journal for Ancient Greek Political Thought 28, no. 2 (2011): 279–308. http://dx.doi.org/10.1163/20512996-90000189.

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This article examines Aristotle’s discussion of the Spartan revolt of the Partheniae in Politics V.7. Aristotle appears to use the Partheniae as examples of two sources of instability within so-called aristocracies, but the analysis of this case raises delicate interpretive issues. Sections I–III draw upon surviving accounts of the Parthenian revolt from Antiochus, Ephorus and Myron of Priene in order to illuminate the significance of this example for Aristotle’s ethical and political thought. Section IV reconstructs the state of the Spartan constitution around the time of the revolt in order to understand what Aristotle might have thought about what precipitated the revolt. This article argues that generational politics is at stake in the revolt, and Section V locates the revolt’s politics within its broader historical and cultural context. In the end, this article finds that Aristotle may have intended to leave the interpretation of this example ambiguous due to his own unresolved views towards the politics at stake in this revolt.
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Kalia, Kartik, Khyati Nanda, Arushi Aggarwal, Akshita Goel, and Shivani Malhotra. "Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA." Advanced Materials Research 1098 (April 2015): 37–43. http://dx.doi.org/10.4028/www.scientific.net/amr.1098.37.

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In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.
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Jáuregui, Francisco Plascencia, J. J. Raygoza Panduro, Susana Ortega C., and Edwin Becerra. "Implementación de un circuito custom DSP en FPGAs para cálculo del determinante 3x3, y matriz inversa de matrices ortogonales 3x3." RECIBE, REVISTA ELECTRÓNICA DE COMPUTACIÓN, INFORMÁTICA, BIOMÉDICA Y ELECTRÓNICA 4, no. 2 (December 6, 2015): E1–1—E1–23. http://dx.doi.org/10.32870/recibe.v4i2.38.

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En este artículo se presenta el diseño e implementación de un circuito digital a medida para el cálculo de determinantes de orden 3x3 y matriz inversa de matrices ortogonales 3x3. Se analizan los resultados de la implementación de los circuitos en dos plataformas de familias de dispositivos reconfigurables, estas son Artix 7 y Spartan 6 Low-Power, en los que se comparan la ocupación y los tiempos de respuesta. La descripción del circuito se realizó en Lenguaje de Descripción de Hardware (HDL).
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EL GOURI, Rachid, Wassima Ait Ahmed, Ahmed Lichioui, and Laamari Hlou. "Conception and Implementation of a BCH Code on a FPGA Board." International Journal of Engineering & Technology 2, no. 4 (November 28, 2013): 293. http://dx.doi.org/10.14419/ijet.v2i4.1430.

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In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGAs Board will be shown at last.
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Younis, Dr Basma MohammedKamal, and Dua’a Basman Younis. "Fuzzy Image Processing Based Architecture for Contrast Enhancement in Diabetic Retinopathy Images." International Journal of Computer Engineering and Information Technology 12, no. 4 (April 30, 2020): 26–30. http://dx.doi.org/10.47277/ijceit/12(4)1.

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Diabetic retinopathy” is damage to retina denotes one of the problems of diabetes which is a significant reason for visual infirmity and blindness. A comprehensive and routine eye check is important to early detection and rapid treatment. This study proposes a hardware system that can enhance the contrast in the diabetic retinopathy eye fundus images as a first step in different eye disease diagnoses. The fuzzy histogram equalization technique is proposed to increases the local contrast of Diabetic Retinopathy Images. First, a histogram construction hardware architecture for different image processing purposes has been built then modified with fuzzy techniques to create fuzzy histogram equalization architecture, which is used to enhance the original images. Both architectures are designed using a finite-state machine (FSM) technique and programmed with VHDL programming language. The first one is implemented using two (Spartan 3E-XC3S500 and Xilinx Artix-7 XC7A100T) kits, while the second architecture is implemented using (Spartan 3E-XC3S500) kit. The system consists also of a modified video graphics array (VGA) port to display the input and resulted images with a proper resolution. All the hardware outputs are compared to that results produce from MatLab for verification and the resulted images are tested by PSNR, MSE, ENTROPY ,and AMBE
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Pandey, Bishwajeet, Geetam S. Tomar, Rajina R. Mohamed, D. M. Akbar Hussain, and Amit Kant Pandit. "Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate." Journal of Computational and Theoretical Nanoscience 17, no. 11 (November 1, 2020): 5122–24. http://dx.doi.org/10.1166/jctn.2020.9351.

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Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our work, we are also using 16 nm technology based UltraScale+ FPGA for implementing our memory using VIVADO 2018.3 hardware programming tool and Verilog Hardware Description Language. There is 49.42%, 25.28% saving in design power on UltraScale+ FPGA when we minimize static probabilities to 0.1 and 0.2 respectively.
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10

Delamere, C., C. Jakins, and E. Lewars. "Tests for aromaticity applied to the pentalenoquinones — A computational study." Canadian Journal of Chemistry 79, no. 10 (October 1, 2001): 1492–504. http://dx.doi.org/10.1139/v01-164.

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Criteria for aromaticity and antiaromaticity were applied to the four pentalenoquinones, 1,2-, 1,5-, 1,4-, and 1,6-pentalenoquinone, i.e., bicyclo[3.3.0]octa-4,6,8-triene-2,3-dione (7a), bicyclo[3.3.0]octa-3,5,8-triene-2,7-dione (7b), bicyclo[3.3.0]octa-1(5),3,7-triene-2,6-dione (7c), and bicyclo[3.3.0]octa-1(5),3,6-triene-2,8-dione (7d). Geometry optimizations and frequency calculations were done with the pBP/DN* DFT method as implemented in Spartan, and single-point HF/3-21G calculations to obtain Löwdin bond orders (Spartan), as well as HF/6-31G* NICS calculations (Gaussian 98) were also carried out. Geometries and bond orders, chemical hardness, and NICS values gave no definite indication of aromatic or antiaromatic character. However, homodesmotic ring-opening reactions to give acyclic analogues indicated that 7a and 7b are nonaromatic (resonance energies –11 and 5 kJ mol–1) while 7c and 7d are antiaromatic (resonance energies –83 and –54 kJ mol–1). The resonance energies were obtained with the aid of an estimate of the strain energy of the molecules 7 (86 kJ mol–1) by a novel extrapolation procedure on hydropentalenes. Calculated pBP/DN* activation energies for Diels–Alder reactions with ethyne and ethene placed 7a and 7b in an "unreactive" class similar to 1,3-butadiene and fulvene, and 7c and 7d in a "reactive" class, similar to cyclopentadienone.Key words: aromaticity, pentalenoquinones, DFT, hardness, NICS, homodesmotic, resonance energy, bicyclo[3.3.0]octatrienediones.
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Dissertations / Theses on the topic "Spartan-7"

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Жданова, Ю. В., and І. В. Свид. "Огляд сьомої серії FPGA компанії Xilinx." Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9371.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://doi.org/10.35598/mcfpga.2019.008.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-008.

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Воргуль, О. В., and В. Є. Ганзин. "Моделювання напівсмугового фільтру." Thesis, ЗНТУ, 2018. http://openarchive.nure.ua/handle/document/8491.

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Об’єктом дослідження є напівсмуговий фільтр, що розробляється в цифровому вигляді. Такий фільтр корисний для розробника, оскільки є базовим елементом для виконання великої кількості операцій над сигналом - перенесення сигналів за частотою, модуляції, демодуляції. Зручно використовувати модель фільтру також тим, що це дозволяє виконувати перевірку якості роботи як за частотними так і за часовими характеристиками, а також за ключовими параметрами, істотними для поточного завдання дослідника, наприклад, чисельність вентилів, значення затримки тощо.
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Books on the topic "Spartan-7"

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Link, Stefan. Das frühe Sparta: Untersuchungen zur spartanischen Staatsbildung im 7. und 6. Jahrhundert v. Chr. St. Katharinen: Scripta Mercaturae Verlag, 2000.

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Aristokraten und Damoden: Untersuchungen zur inneren Entwicklung Spartas im 7. Jahrhundert v. Chr. und zur politischen Funktionder Dichtung des Tyrtaios. Stuttgart: Steiner, 1998.

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Book chapters on the topic "Spartan-7"

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"7. The Purported Jewish-Spartan Affiliation." In The Construct of Identity in Hellenistic Judaism, 153–66. De Gruyter, 2016. http://dx.doi.org/10.1515/9783110375558-010.

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Bayliss, Andrew J. "7. The later reception of Sparta." In The Spartans: A Very Short Introduction, 105–20. Oxford University Press, 2022. http://dx.doi.org/10.1093/actrade/9780198787600.003.0007.

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‘The later reception of Sparta’ addresses the ‘reception’ of Sparta in modern culture. This includes the ways in which the ancient testimony about the Spartans has been transmitted, interpreted, represented, and reimagined by later societies. Many Enlightenment-period thinkers stressed their admiration for the Spartans and their way of life. But other Enlightenment-era commentators were less convinced, and many of the Founding Fathers of the USA were critical of Sparta. Meanwhile, the dark ends to which admiration of Sparta can lead are best seen in Nazi Germany where Spartophilia was linked to official policy. The image of Sparta in films and fiction is an interesting area to examine as well. Also, it is a fact that sporting teams around the globe have invoked the Spartan legend to promote team spirit.
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"Chapter 7. A Spartan Domesticity: Household Life in La Isabela’s Bohíos." In Columbus’s Outpost among the Taínos, 131–62. Yale University Press, 2017. http://dx.doi.org/10.12987/9780300133899-008.

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Cartledge, Paul. "7. Sparta." In Ancient Greece, 50–61. Oxford University Press, 2011. http://dx.doi.org/10.1093/actrade/9780199601349.003.0007.

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"Becoming a Spartan W@rker." In The Spartan W@rker, 50–66. Routledge, 2017. http://dx.doi.org/10.4324/9781315163451-7.

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"The duplicitous Spartan: Alfred S. Bradford(University of Missouri, Columbia)." In The Shadow of Sparta, 64–90. Routledge, 2002. http://dx.doi.org/10.4324/9780203085073-7.

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Hammersley, Rachel. "Innovation in Substance: Democracy." In James Harrington, 109–21. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780198809852.003.0007.

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The emergence of modern democracy has tended to be associated with the eighteenth rather than the seventeenth century. Yet, as Chapter 7 shows, the English Revolution not only provoked proto-democratic ideas among the Levellers, but also led Harrington to embrace both the terminology and the substance of democracy. Harrington deliberately used this term to describe his model constitution, thereby tarnishing the ‘oligarchic’ pretensions of his opponents, and associating democracy with Sparta rather than Athens and therefore with a popular veto rather than popular debate. In Oceana, Harrington advocated a highly inclusive citizen body the members of which could exercise considerable political powers. He also expressed his commitment to meritocracy, which would be secured within his system. Ultimately, the chapter argues that Harrington’s distinctive understanding of democracy was both novel and influential.
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Kong, J. H., J. J. Ong, L. M. Ang, and K. P. Seng. "Low Complexity Processor Designs for Energy-Efficient Security and Error Correction in Wireless Sensor Networks." In Wireless Sensor Networks and Energy Efficiency, 348–66. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0101-7.ch017.

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This chapter presents low complexity processor designs for energy-efficient security and error correction for implementation on wireless sensor networks (WSN). WSN nodes have limited resources in terms of hardware, memory, and battery life span. Small area hardware designs for encryption and error-correction modules are the most preferred approach to meet the stringent design area requirement. This chapter describes Minimal Instruction Set Computer (MISC) processor designs with a compact architecture and simple hardware components. The MISC is able to make use of a small area of the FPGA and provides a processor platform for security and error correction operations. In this chapter, two example applications, which are the Advance Encryption Standard (AES) and Reed Solomon (RS) algorithms, were implemented onto MISC. The MISC hardware architecture for AES and RS were designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.
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