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Journal articles on the topic 'Spacers gate'

Author: Grafiati

Published: 12 October 2024

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1

Weng, Chun Jen. "Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration." Advanced Materials Research 154-155 (October 2010): 938–41. http://dx.doi.org/10.4028/www.scientific.net/amr.154-155.938.

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As wafer nanotechnology gate is scaling down, the fabrication technology of gate spacer for transistor becomes more critical in manufacturing processes. Because wafer fabrication technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present study is to overcome the fabrication processes limitations and proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and electrical characteristics.

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2

Weng, Chun Jen. "Etching Process Effects of CMOS Transistor Gate Manufacturing Nanotechnology Fabrication Integration." Applied Mechanics and Materials 83 (July 2011): 91–96. http://dx.doi.org/10.4028/www.scientific.net/amm.83.91.

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As the nanotechnology gate is scaling down, the fabrication technology of gate spacer for CMOS transistor becomes more critical in manufacturing processes. For CMOS technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. A sidewall spacer patterning technology yields critical dimension variations of minimum-sized features much smaller than that achieved by optical Complementary Metal–Oxide–Semiconductor (CMOS) fabrication processes integration. The present study is to overcome the fabrication limitations and more particularly focus on etching processes integration on structural and formation processing for complementary metal oxide semiconductor nanofabrication process on gate spacer technology and electrical characteristics performance of nanotechnology gate structure were included. Based on the investigation of the etching effect and interface film variation on the electrical characteristics of the gate oxide on etching profile and their impacts on the sidewall transistor gate structure, a novel etching integration process for optimal controlled sidewall gate spacer fabrication was developed.

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3

Wylie, Ian W., and N. Garry Tarr. "A new approach to gate/n− overlapped lightly doped drain structures: added gate after implantation of n− (AGAIN)." Canadian Journal of Physics 69, no. 3-4 (March 1, 1991): 174–76. http://dx.doi.org/10.1139/p91-027.

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A new lightly doped drain (LDD) metal oxide semiconductor field effect transistor structure is presented that provides substantial overlap of the gate over the n− region independent of the n− junction depth. This structure uses polysilicon spacers to replace the oxide sidewall spacers used in a conventional LDD device. The structure has been given the acronym "AGAIN," for added gate after implantation of n−.

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4

Kumar, Padakanti Kiran, Bukya Balaji, and Karumuri Srinivasa Rao. "Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (June 1, 2023): 3519. http://dx.doi.org/10.11591/ijece.v13i3.pp3519-3529.

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In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10<sup>-17</sup> farads and 1.11x10<sup>-12</sup> seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.

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5

Wostyn, Kurt, Karine Kenis, Hans Mertens, Adrian Vaisman Chasin, Andriy Hikavyy, Frank Holsteyns, and Naoto Horiguchi. "Low Temperature SiGe Steam Oxide - Aqueous Hf and NH₃/NF₃ Remote Plasma Etching and its Implementation as Si GAA Inner Spacer." Solid State Phenomena 282 (August 2018): 126–31. http://dx.doi.org/10.4028/www.scientific.net/ssp.282.126.

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For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH3/NF3remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si0.75Ge0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.

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6

Guo, Mengxue, Weifeng Lü, Ziqiang Xie, Mengjie Zhao, Weijie Wei, and Ying Han. "Effects of Symmetric and Asymmetric Double-Layer Spacers on a Negative-Capacitance Nanosheet Field-Effect Transistor." Journal of Nanoelectronics and Optoelectronics 17, no. 6 (June 1, 2022): 873–82. http://dx.doi.org/10.1166/jno.2022.3266.

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The effect of three double-layer spacers (corner/selective/dual) on the performance of a negative-capacitance nanosheet field-effect transistor (NC-NSFET) was investigated for the first time. Sentaurus technology computer-aided design simulations revealed that the NC-NSFET with corner spacer will be significantly improved in transfer and high frequency characteristics due to the increase of ferroelectric layer thickness, and the NC-NSFET with a selective spacer structure exhibits better gate controllability. Compared with the ordinary dual-k spacer structure, the switching current ratio is doubled, and its subthreshold swing and drain-induced barrier lowering are reduced by 3.0% and 48%, respectively. In addition, by introducing a selective spacer at the source side and a corner spacer at the drain side, the NC-NSFET has a smaller intrinsic delay and exhibits better capacitance matching and stronger gate controllability than that with a symmetric spacer. For the double-layer spacer, the extension of the high-k spacer in the horizontal direction is more beneficial to the improvement of the device performance than that in the vertical direction, which provides a more comprehensive reference for the spacer application in NC-NSFET.

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7

Durfee, Curtis, Ivo Otto IV, Subhadeep Kal, Shanti Pancharatnam, Matthew Flaugh, Toshiki Kanaki, Matthew Rednor, et al. "Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors." ECS Transactions 112, no. 1 (September 29, 2023): 45–52. http://dx.doi.org/10.1149/11201.0045ecst.

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Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated using inner spacers or buffers to prevent damage during Channel Release (CR). The damage can be further mitigated with optimized CR etch chemistry, enabling IS scaling. We highlight S/D damage mechanisms during CR, then demonstrate reduced S/D damage by co-optimization of the IS, CR chemistry and S/D epitaxy.

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8

Convertino, Clarissa, Cezar Zota, Heinz Schmid, Daniele Caimi, Marilyne Sousa, Kirsten Moselund, and Lukas Czornomaz. "InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities." Materials 12, no. 1 (December 27, 2018): 87. http://dx.doi.org/10.3390/ma12010087.

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III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

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9

Li, Junjie, Yongliang Li, Na Zhou, Wenjuan Xiong, Guilei Wang, Qingzhu Zhang, Anyan Du, et al. "Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors." Nanomaterials 10, no. 4 (April 20, 2020): 793. http://dx.doi.org/10.3390/nano10040793.

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Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

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10

Bacquié, Valentin, Aurélien Tavernier, François Boulard, Olivier Pollet, and Nicolas Possémé. "Gate spacers etching of Si3N4 using cyclic approach for 3D CMOS devices." Journal of Vacuum Science & Technology A 39, no. 3 (May 2021): 033005. http://dx.doi.org/10.1116/6.0000871.

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11

Kalarickal, Nidhin Kurian, Ashok Dheenan, Joe F. McGlone, Sushovan Dhara, Mark Brenner, Steven A. Ringel, and Siddharth Rajan. "Demonstration of self-aligned β-Ga₂O₃ δ-doped MOSFETs with current density >550 mA/mm." Applied Physics Letters 122, no. 11 (March 13, 2023): 113506. http://dx.doi.org/10.1063/5.0131996.

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We report on the design and fabrication of [Formula: see text]-Ga2O3 self-aligned lateral MOSFETs by utilizing a heavily doped [Formula: see text]-Ga2O3 cap layer. The fabrication of the self-aligned device used a combination of in situ Ga etching for damage free gate recess, in situ growth of Al2O3 for gate dielectric, and atomic layer deposited Al2O3 based sidewall spacers to form highly scaled (<100 nm) source–gate and gate–drain access regions. The fabricated device showed a record high DC drain current density of 560 mA/mm at a drain bias of 5 V. The DC current density was found to be limited by excessive self-heating resulting in premature current saturation in the device. Pulsed I–V measurements of the device showed a record high current density of 895 mA/mm and a high transconductance of 43 mS/mm, thanks to reduced self-heating in the device. The high current densities obtained in this work are promising for the development of high power density devices based on [Formula: see text]-Ga2O3.

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12

Narula, Mandeep Singh, and Archana Pandey. "Performance Evaluation of Stacked Gate Oxide/High K Spacers Based Gate All Around Device Architectures at 10 nm Technology Node." Silicon 14, no. 5 (January 20, 2022): 2397–407. http://dx.doi.org/10.1007/s12633-022-01685-9.

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13

Gu, Jie, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, et al. "Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs." Nanomaterials 11, no. 2 (January 26, 2021): 309. http://dx.doi.org/10.3390/nano11020309.

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A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

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14

Mo, Fabrizio, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, and Marco Vacca. "NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance." Electronics 12, no. 6 (March 21, 2023): 1487. http://dx.doi.org/10.3390/electronics12061487.

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NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

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15

Hsieh, C. S., P. C. Kao, C. S. Chiu, C. H. Hon, C. C. Fan, W. C. Kung, Z. W. Wang, and E. S. Jeng. "NVM Characteristics of Single-MOSFET Cells Using Nitride Spacers With Gate-to-Drain NOI." IEEE Transactions on Electron Devices 51, no. 11 (November 2004): 1811–17. http://dx.doi.org/10.1109/ted.2004.836796.

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16

Liu, Peng, Chuncheng Xie, Feng Zhang, Jianguo Chen, and Dongmin Chen. "Elimination of Gate Leakage in GaN FETs by Placing Oxide Spacers on the Mesa Sidewalls." IEEE Electron Device Letters 34, no. 10 (October 2013): 1232–34. http://dx.doi.org/10.1109/led.2013.2278013.

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17

van Dam, D. B., M. P. J. Peeters, C. J. Curling, R. Schroeders, and M. A. Verschuuren. "Application of Printable Electronics for LCD Manufacturing: Printing of TFT Gate Layers and Pillar Spacers." NIP & Digital Fabrication Conference 20, no. 1 (January 1, 2004): 284–90. http://dx.doi.org/10.2352/issn.2169-4451.2004.20.1.art00065_1.

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18

Beghalem, Hamida, Khadidja Aliliche, and Ahmed Landoulsi. "Phylogeny and Sequence Analysis of Sulla species Based on Intergenic Spacers trnL-trnF." South Asian Journal of Experimental Biology 11, no. 3 (May 24, 2021): 321–26. http://dx.doi.org/10.38150/sajeb.11(3).p321-326.

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Chloroplast DNA (cpDNA) sequence variations are broadly used to investi-gate interspecific relationships among plants. The trnL-trnF spacer is located in the large single-copy region of the chloroplast genome. The objective of this study was to evaluate the level of genetic variability between the Algeri-an and Tunisian species Hedysarum pallidum (North African endemic spe-cies) and H. capitatum. The phylogenetic relationships among the studied species were investigated by means of maximum Likehood analysis of se-quence polymorphism from chloroplast trnL-trnF spacer DNA; the tree parti-tioned the studied species in two clades. In addition, some specific variations loci- were identified between the species. The observed variations suggest considerable differentiation among cpDNA which could be useful to identify species.

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19

Chen, I. C., C. C. Wei, and C. W. Teng. "Simple gate-to-drain overlapped MOSFETs using poly spacers for high immunity to channel hot-electron degradation." IEEE Electron Device Letters 11, no. 2 (February 1990): 78–81. http://dx.doi.org/10.1109/55.46934.

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20

Ji Hun Choi, Tae Kyun Kim, Jung Min Moon, Young Gwang Yoon, Byeong Woon Hwang, Dong Hyun Kim, and Seok-Hee Lee. "Origin of Device Performance Enhancement of Junctionless Accumulation-Mode (JAM) Bulk FinFETs With High-$\kappa $ Gate Spacers." IEEE Electron Device Letters 35, no. 12 (December 2014): 1182–84. http://dx.doi.org/10.1109/led.2014.2364093.

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21

Miyashita, Toshihiko, Katsuaki Ookoshi, Akiyoshi Hatada, Keiji Ikeda, Young Suk Kim, Masatoshi Nishikawa, and Hajime Kurata. "Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications." Japanese Journal of Applied Physics 48, no. 4 (April 20, 2009): 04C053. http://dx.doi.org/10.1143/jjap.48.04c053.

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22

Abdula, Daner, YuJen Chiu, Brendan Marozas, Rami Khazaka, Caleb K. Miskin, Jung Soo Lee, and Alexandros T. Demos. "Low-Temperature Selective Si:As Epitaxy." ECS Transactions 114, no. 2 (September 27, 2024): 37–46. http://dx.doi.org/10.1149/11402.0037ecst.

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A selective low-temperature Si:As (LT-SiAs) process is presented which utilizes cyclic deposition-etch (CDE) at <450oC. Selectivity against SiN and SiOx dielectrics and crystallinity are confirmed on gate-all-around (GAA) patterned structures. Hall measurements on blanket wafers show a resistivity minimum of 0.42 mΩ-cm at ~1.7% As for selective LT-SiAs. Secondary-ion mass spectroscopy (SIMS) profiles of P and As diffusion into intrinsic Si (i-Si) for LT-SiP/LT-SiAs/i-Si and LT-SiP/i-Si stacks show >2× benefit of using LT-SiAs spacers to minimize dopant diffusion for as-deposited, soak-annealed and spike-annealed samples. Improvement is attributed to relatively limited diffusivity of As in Si versus P and the lower As concentration needed for LT-SiAs layer to achieve minimum resistivity relative to LT-SiP (~3%). Lastly, a comparison of LT-SiAs and high-temperature Si:As (HT-SiAs) shows a ~2× reduction of As diffusion into i-Si for LT-SiAs at length scales of >10nm.

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23

Zhao, Jianli, Yilin Wang, Xiaowei Wang, and Yisheng Zhang. "An Experimental Investigation of the Material Properties of the A356 Aluminum Alloy Power Fittings in the Vacuum Die-Casting Process." Materials 17, no. 6 (March 8, 2024): 1242. http://dx.doi.org/10.3390/ma17061242.

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To enhance the performance of ultra-high voltage power fittings in severe weather conditions without altering their current structure, the high-strength and toughness aluminum alloys were rationally selected to study the optimization of the die-casting process. This approach aims to improve the overall longevity and function of the power fittings in extreme climates. First of all, the propose of this study is to use the material’s strength–toughness product (STP) concept to evaluate the material stability of the power fitting impact resistance and fatigue toughness in order to determine the appropriate material selection. Secondly, the location of the mold’s sprue and gate was optimized through finite element simulation to prevent gas volume and flow defects during the casting process. This improves the material’s toughness and anti-fatigue failure characteristics of the product. Then, vacuum equipment and a vacuum valve auxiliary system were added based on the existing die-casting machine, and the mold structure was optimized to enable the vacuum die-casting process. Finally, a water-based boron nitride environmentally friendly mold release agent was used to solve demolding difficulties with an A356 aluminum alloy and improve mold lubrication and surface quality. The production of quad-bundled spacers using A356 and vacuum die casting has resulted in parts with a tensile strength of at least 250 MPa and an elongation of no less than 7%. This improvement has laid a foundation for enhancing the operational reliability of existing overhead transmission line fittings.

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24

Bernard, E., T. Ernst, B. Guillaumot, N. Vulliet, Tao Chuan Lim, O. Rozeau, F. Danneville, et al. "First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements." IEEE Electron Device Letters 30, no. 2 (February 2009): 148–51. http://dx.doi.org/10.1109/led.2008.2009008.

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25

Heifetz, Aviad. "Non-well-founded-Type Spaces." Games and Economic Behavior 16, no. 2 (October 1996): 202–17. http://dx.doi.org/10.1006/game.1996.0083.

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26

Heifetz, Aviad, and Philippe Mongin. "Probability Logic for Type Spaces." Games and Economic Behavior 35, no. 1-2 (April 2001): 31–53. http://dx.doi.org/10.1006/game.1999.0788.

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27

Rana, Ashwani K. "Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs." Semiconductor Physics Quantum Electronics and Optoelectronics 14, no. 2 (June 30, 2011): 203–8. http://dx.doi.org/10.15407/spqeo14.02.203.

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Heifetz, Aviad, and Dov Samet. "Knowledge Spaces with Arbitrarily High Rank." Games and Economic Behavior 22, no. 2 (February 1998): 260–73. http://dx.doi.org/10.1006/game.1997.0591.

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29

RANA, ASHWANI K., NAROTTAM CHAND, and VINOD KAPOOR. "MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER." Journal of Circuits, Systems and Computers 20, no. 08 (December 2011): 1659–75. http://dx.doi.org/10.1142/s0218126611008006.

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Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

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30

Park, Dong Gyu, Hyunwoo Kim, and Jang Hyun Kim. "Improvement Breakdown Voltage by a Using Crown-Shaped Gate." Electronics 12, no. 3 (January 17, 2023): 474. http://dx.doi.org/10.3390/electronics12030474.

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In this paper, a crown-shaped trench gate formed by a sidewall spacer in insulated gate bipolar transistors (IGBT) is proposed to improve breakdown voltage. When a sidewall spacer is added to trench bottom corners, the electric field is distributed to the surface of the sidewall spacer and decreased to 48% peak value of the electric field. Thus, the sidewall spacer IGBT improved to 5% breakdown voltage. Another study proposed an additional oxide layer for trench bottom corners and improved breakdown voltage similar to the proposed IGBT. Previous studies have shown degradation in other electrical characteristics. However, this study shows a sidewall spacer IGBT that increases the current over 3% compared to a conventional trench IGBT when the applied gate voltage is under 4 V. Additionally, the turn-off loss characteristic is similar to conventional trench IGBT. Therefore, the breakdown voltage of the IGBT was improved while maintaining similar electrical properties to existing IGBTs through the crown-shaped gate.

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Fitrianatsany, Fitrianatsany. "Harmonisasi Kehidupan Masyarakat Beragama pada Lingkungan Gated Community di Kelurahan Panggungharjo Yogyakarta." Aceh Anthropological Journal 8, no. 1 (April 30, 2024): 97. http://dx.doi.org/10.29103/aaj.v8i1.15986.

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Living harmoniously in religious communities is crucial to fostering amicable relationships between different religious groups, especially in gated communities. A gated community is a diverse group of people from different ethnicities, religions, and cultures living together. Gated communities offer comfortable, safe, and exclusive housing with security systems, such as a gate arrangement. They also provide public facilities like green open spaces and even a place of worship for residents. This study uses qualitative research methods to explore the development trends of gated communities and how religious life can harmonized within them. The results of this research show that millennials living in gated community complexes view many communities as exclusive, and they do not find these gated communities appealing. However, they still live in harmony with the residents by smiling, greeting each other, being polite, and welcoming to everyone. Additionally, residents of these communities use public facilities for routine gatherings and social-religious activities to strengthen kinship and promote harmony between residents.Abstrak: Kehidupan masyarakat beragama yang harmonis menjadi kunci dalam sebuah kerukunan hidup antar umat beragama pada umumnya dan khususnya di lingkungan gated community atau yang sering disebut sebagai komunitas berpagar. gated community merupakan tempat bermukim masyarakat dengan beragam suku bangsa, agama dan juga budaya. Selain itu, gated community juga menawarkan hunian yang nyaman dan aman serta ekslusif dengan menawarkan sistem keamanan seperti one gate system. Di dalamnya juga menawarkan fasilitas umum seperti ruang terbuka hijau dan bahkan tempat ibadah bagi para penghuninya. Penelitian ini menggunakan metode penelitian kualitatif untuk melihat lebih dalam terkait dengan tren perkembangan gated community dan harmonisasi kehidupan beragama masyarakat gated community di Kelurahan Panggungharjo Yogyakarta. Hasil yang didapat dalam penelitian ini adalah kehidupan kaum milenial yang bermukim di kompleks gated community atau perumahan yang notabene di konstruks oleh masyarakat luas sebagai masyarakat yang ekslusif dan individual ternyata tidak ditemukan di komunitas berpagar tersebut. Mereka justru menerapkan hidup rukun dengan para warga dengan saling senyum, sapa, sopan, ramah dan tamah kepada setiap orang. Selanjutnya warga hunian tersebut juga memanfaatkan fasilitas umum untuk perkumpulan rutin dan kegiatan sosial keagamaan yang bertujuan untuk mempererat tali persaudaraan dan kerukunan antar warga.

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Vimala, Palanichamy, and N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer." Journal of Nano Research 56 (February 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.

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In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

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Veloso, Anabela, Geert Eneman, Eddy Simoen, Bogdan Cretu, An De Keersgieter, Anne Jourdain, and Naoto Horiguchi. "(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1059. http://dx.doi.org/10.1149/ma2022-01191059mtgabs.

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CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option to replace finFETs. Reduced gate lengths should be feasible thanks to their improved electrostatics, thus allowing further scaling of the contacted-gate-pitch and of the cell height via a reduced number of metal tracks. Other key characteristics include high design flexibility, with various NS widths possible on a given wafer, and larger drivability per layout footprint by increasing the number of vertically stacked NS per device and/or using wider NS [1,2] (Fig.1). An extension of this technology could in principle be envisioned by strongly reducing the p-n separation in the so-called forksheet configuration [3]. Beyond that, the concept of stacking devices with different polarity on top of each other is also being looked at [4,5]. Other future technology candidates include FETs with vertical transport [6] and non-silicon channels [7]. Each new architecture will have its own specific challenges such as the internal routeability for stacked structures in functional logic blocks (e.g., standard cell or SRAM) but, in general, many elements can be shared by the various branches of the NS family of devices. Overall, a careful balance between drive strength and capacitance is required in NS FETs engineering. In particular, the presence of dielectric inner spacers in-between vertically stacked nanosheets is a critical element, also as it leads to a different growth regime for the source/drain (S/D) epi as compared to the situation in finFETs [8]. This is an important differentiator as channel strain induced by S/D has been traditionally used to boost device performance. The feasibility of continuing using process-induced stress techniques for mobility enhancement is in fact a key challenge for several new architectures, namely for the top device in stacked structures or when S/D are placed in different vertical levels. Moreover, faced with power scaling stagnation, cold computing is also becoming an attractive option to consider for enabling high performance boosting in an energy efficient way. Our results confirm improved DC properties for NS FETs (e.g., subthreshold swing (SS), mobility), with similar mechanisms responsible for their noise behavior at room and low temperatures (300K (RT), 78K) [9]. In addition to the need for the introduction of new transistor technologies, given the increased complexity and cost in back-end-of-line processing, it has also become ever more pressing to address both wiring and power delivery network (PDN) bottlenecks to take full advantage of the scaling performance benefits at transistor level. The concept of moving the PDN to the wafer’s backside (BS) such that it can alleviate routing congestion on its frontside (FS) has been recently gaining traction [10,11]. This is illustrated in Fig.2 wherein, by combining logic and 3D technologies, both wafer sides are used. In our work, after frontside processing, device and carrier wafers are bonded at RT, including a 523K post-bond anneal. Extreme wafer thinning is then implemented prior to nano-through-silicon-vias (n-TSV) definition (landing on the metal-1 level (M1) in the frontside) and backside metallization. Evaluating the impact on scaled transistors from BS processing, our results show similar p/n threshold voltages (VTs) can be obtained with an extra sinter at the end of fabrication. Inclusion of an additional high-pressure H2-anneal prior to the final sinter is also seen to help lower the SS values for pmos without significant IOFF effect. Reliability-wise, constant ramped voltage stress measurements also show no BTI degradation for p/nmos, with additional indication of potential benefits by the final anneal(s) treatment selection. These findings are further corroborated by LF-noise analysis. References [1] N. Loubet et al., VLSI Tech. Dig., 2017, p.230. [2] A. Veloso et al., SSDM Tech. Dig., 2019, p.559. [3] P. Weckx et al., IEDM Tech. Dig., 2019, p.871. [4] W. Rachmady et al., IEDM Tech. Dig., 2019, p.697. [5] C.-Y. Huang et al., IEDM Tech. Dig., 2020, p.425. [6] A. Veloso et al., IEDM Tech. Dig., 2019, p.230. [7] P.-C. Shen et al., Nature, 2021, Vol.593, p.211. [8] G. Eneman et al., ECS Trans., 2020, Vol.98(5), p.253. [9] B. Cretu et al., EuroSOI-ULIS Tech. Dig., 2021. [10] A. Veloso et al., VLSI Tech. Dig., 2021, TFS2-6. [11] https://www.intel.com/content/www/us/en/events/accelerated.html. Figure 1

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Kim, Hyun Woo, and Daewoong Kwon. "Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer." Applied Sciences 10, no. 9 (April 27, 2020): 3054. http://dx.doi.org/10.3390/app10093054.

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Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.

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Sil, Monali, Sk Masum Nawaz, and Abhijit Mallik. "On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer." Semiconductor Science and Technology 37, no. 4 (February 23, 2022): 045006. http://dx.doi.org/10.1088/1361-6641/ac52b7.

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Abstract This paper reports a thorough investigation of the impacts of a spacer dielectric on the performance of HfO2-ferroelectric-based negative capacitance (NC)-FinFETs for 10 nm technology (gate length 22 nm) as per International Roadmap for Devices and Systems with in comparison with similarly-sized conventional FinFETs by means of an industry standard technology computer aided design tool. It is found that, although a high-k spacer results in improved subthreshold swing (SS) and I ON, it increases delay due to enhanced gate capacitance for both types of devices. In spite of having higher gate capacitance for a given spacer, the delay is lower for the NC devices than the conventional devices with identical I OFF, which is due to higher I ON in such devices. Comparing with the baseline FinFET; I ON, SS, threshold voltage, delay and power dissipation of NC-FinFET have been found to improve by 69%, 7%, 5%, 14% and 9% respectively, when Si3N4 spacer is used. Implications of spacer on V DD scalability, delay and power dissipation of NC-FinFETs have also been investigated in one-to-one comparison with similarly-sized conventional FinFETs. If identical delay is considered in both the devices, higher active power dissipation due to enhanced gate capacitance is a concern for HfO2-ferroelectric-based NC-FinFETs.

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Saxena, Raghvendra Sahai, and M. Jagadesh Kumar. "Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET." IEEE Transactions on Electron Devices 59, no. 3 (March 2012): 738–44. http://dx.doi.org/10.1109/ted.2011.2176946.

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Spiteri, Jake C., Jonathan S. Schembri, and David C. Magri. "A naphthalimide-based ‘Pourbaix sensor’: a redox and pH driven AND logic gate with photoinduced electron transfer and internal charge transfer mechanisms." New Journal of Chemistry 39, no. 5 (2015): 3349–52. http://dx.doi.org/10.1039/c5nj00068h.

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Mykhaylyuk, Volodymyr. "Namioka spaces, GO-spaces and an o-game." Topology and its Applications 235 (February 2018): 1–13. http://dx.doi.org/10.1016/j.topol.2017.11.008.

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Romig, Kevin. "The Upper Sonoran Lifestyle: Gated Communities in Scottsdale, Arizona." City & Community 4, no. 1 (March 2005): 67–86. http://dx.doi.org/10.1111/j.1535-6841.2005.00103.x.

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While much has been written on gated communities and the motivations and proposed implications of such a building paradigm, little has informed us about how a landscape is socially and economically transformed by the influx of this community design principle. This article explores a place defined by gated communities highlighting significant differences in social and community life in the city of Scottsdale, Arizona. This is a location, unlike many other gated spaces, where the gating of the community has little to do with avoiding crime. It is mainly a symbol of prestige and exclusivity. Housing in the Northern part of Scottsdale is mostly gated, master‐planned communities geared toward the upper class while the Southern part of Scottsdale is comprised of older housing stock and more organic community life. Both primary and secondary data are analyzed to highlight the socio‐cultural nature of the Upper Sonoran landscape. This article also explores social theory and proposes the use of multi‐scalar thinking and grounded fieldwork in gathering a more detailed, multi‐dimensional picture of community life behind the gate. This picture illustrates the changing nature of institutional forces shaping urban life as neoliberal policies in local government engender the proliferation of private institutions, as residents are willing to relinquish personal property rights for economic and social stability.

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Aurichi, Leandro F., and Rodrigo R. Dias. "Topological Games and Alster Spaces." Canadian Mathematical Bulletin 57, no. 4 (December 1, 2014): 683–96. http://dx.doi.org/10.4153/cmb-2013-048-5.

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AbstractIn this paper we study connections between topological games such as Rothberger, Menger, and compact-open games, and we relate these games to properties involving covers byGδsubsets. The results include the following: (1) If TWO has a winning strategy in theMenger game on a regular spaceX, thenXis an Alster space. (2) If TWO has a winning strategy in the Rothberger game on a topological spaceX, then theGδ-topology onXis Lindelöf. (3) The Menger game and the compact-open game are (consistently) not dual.

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VANNUCCI, STEFANO. "GAME FORMATS AS CHU SPACES." International Game Theory Review 09, no. 01 (March 2007): 119–38. http://dx.doi.org/10.1142/s021919890700131x.

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It is argued that when morphisms are ignored virtually all coalitional, strategic and extensive game formats as currently employed in the extant game-theoretic literature may be presented in a fairly natural way as (concrete categories over) discrete subcategories of Chu(Set,2). Moreover, under a suitable choice of coalitional morphisms, coalitional game formats are shown to be (concrete categories over) full subcategories of Chu(Set,2).

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Dress, Andreas W. M., and Rudolf Scharlau. "Gated sets in metric spaces." Aequationes Mathematicae 34, no. 1 (February 1987): 112–20. http://dx.doi.org/10.1007/bf01840131.

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Vassilevski, Konstantin, Irina P. Nikitina, Alton B. Horsfall, Nicolas G. Wright, Andrew J. Smith, and C. Mark Johnson. "Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts." Materials Science Forum 679-680 (March 2011): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.670.

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Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

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Chattopadhyay, Ankush, Arpan Dasgupta, Rahul Das, Atanu Kundu, and Chandan K. Sarkar. "Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack." Superlattices and Microstructures 101 (January 2017): 87–95. http://dx.doi.org/10.1016/j.spmi.2016.11.024.

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Stone, Sally. "Gate 81:." idea journal 14, no. 1 (July 3, 2018): 80–95. http://dx.doi.org/10.37113/ideaj.vi0.70.

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The discovery and recognition of the embodied meaning of a place can be interpreted through the existing building. The installation artist, the designer and the architect regard the building not as a blank canvas but as multi- layered structure, which they have the opportunity to activate. They have the opportunity to reflect upon the contingency, usefulness and emotional resonance of a particular place and use this knowledge to heighten the viewer’s perception of it. The relationship between the building and its wider location has often been seen as somewhat ambiguous and yet it is possible to describe some spaces as encapsulating, in miniature, the characteristic qualities or features of a much wider situation.The interior has an obvious and direct relationship with the building that it occupies, the people who use it, and also it can have a connection with the area in which it is located. Preston Bus Station is a marvellously brutal building. In 2012, the Preston City Council proposed its demolition and replacement with a surface car park; they refused to consider proposals for building re-use. This provocative act galvanised the various groups that were campaigning to save the building and proved to be the impetus for a number of different types of projects. Gate 81, a collaboration between architects, designers, academics and arts organisations, curated a series of events within the Bus Station with the intention of raising the profile of the building.This paper will discuss the nature of the building, document the Gate 81 projects and report upon this sanguine approach to conservation.

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Rao, Mukund Kadursrinivas, K. R. Sridhara Murthi, and Baldev Raj. "Future Indian Space: Perspectives of Game Changers." New Space 6, no. 2 (June 2018): 103–8. http://dx.doi.org/10.1089/space.2017.0013.

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Wucherpfennig, Claudia, and Anke Strüver. "„Es ist ja nur ein Spiel…“ – Zur Performativität geschlechtlich codierter Körper, Identitäten und Räume." Geographische Zeitschrift 102, no. 3 (2014): 175–89. http://dx.doi.org/10.25162/gz-2014-0018.

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Kuang, Fengyu, Cong Li, Haokun Li, Hailong You, and M. Jamal Deen. "Effect of Non-Ideal Cross-Sectional Shape on the Performance of Nanosheet-Based FETs." Electronics 12, no. 16 (August 11, 2023): 3419. http://dx.doi.org/10.3390/electronics12163419.

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In this article, the effects of non-ideal cross-sectional shapes of stacked nanosheet FET (NSFET) and nanosheet FET with inter-bridge channel (TreeFET) are studied through calibrated 3D TCAD simulations. The impact of non-ideal cross-sectional shapes on the electrical characteristics due to insufficient/excessive etch processes are investigated in terms of inner spacer (IS), nanosheet (NS) channel, and inter-bridge (IB) channel. Simulation results show that the geometry and material of the IS have significant effects on the performance of the NSFET. Compared with the rectangular inner spacer (RIS), the low-k crescent inner spacer (CIS) enhances the gate control capability while the high-k CIS degrades the drain-induced barrier lowering (DIBL) and reduces the gate capacitance (Cgg). The tapered NS channel improves short-channel effects (SCEs), but sacrifices the driving current. For the TreeFET, considering the fin angle and concave arc, the IB channel can degrade the gate control capability, and SCEs degradation is severe compared to the ideal structure. Therefore, the non-ideal cross-sectional shapes have a significant impact on NSFET-based structure. This research provides development guidelines for process and structure optimization in advanced transistor technology nodes.

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Li, Yu Kui, and Yun Peng Liu. "Characteristics of a Triode Field Emission Display Panel with the Suspension Gate Structure." Materials Science Forum 663-665 (November 2010): 203–6. http://dx.doi.org/10.4028/www.scientific.net/msf.663-665.203.

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With the effective screen-printing technique and high-temperature sintering process, the suspersion gate structure was developed. The silver slurry was printed on the gate substrate to form the gate electrode. Using carbon nanotube as cold field emitter, the triode field emission display (FED) panel was fabricated, and the detailed manufacture process was also presented. The anode back plane, the cathode back plane and spacer combined to device room, in which the suspension gate structure would be included. The distance between the gate electrode and carbon nanotube cathode could be reduced, which could decrease the device manufacture cost because of the small gate voltage. The modulation of emitted electron by the gate voltage would be confirmed, and the field emission characteristics was measured. The sealed FED panel with simple fabrication process and designed structure possessed better field emission uniformity, high display brightness and field emission perofrmance.

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N, Anitha, and Dr Srividya P. "Parameter Analysis of CNTFET." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (July 30, 2019): 5355–59. http://dx.doi.org/10.35940/ijrte.b2609078219.

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In this paper, a parameter analysis of CNTFET is presented with different parameters variations such as gate to source voltage vgs, oxide thickness tox, gate oxide dielectric Kox, channel length L, source/drain spacer dielectric constant Kspa ect. All the parameters of CNTFET have been varied in CADENCE Virtuoso environment and verified with the preferred value of stanford VS-CNTFET model.

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