Journal articles on the topic 'Software-based fault injection'
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Laurent, J., C. Deleuze, F. Pebay-Peyroula, and V. Beroulle. "Bridging the Gap between RTL and Software Fault Injection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–24. http://dx.doi.org/10.1145/3446214.
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Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.
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Park, Jihyun, and Byoungju Choi. "ASFIT: AUTOSAR-Based Software Fault Injection Test for Vehicles." Electronics 9, no. 5 (May 20, 2020): 850. http://dx.doi.org/10.3390/electronics9050850.
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With recent increases in the amount of software installed in vehicles, the probability of automotive software faults that lead to accidents has also increased. Because automotive software faults can lead to serious accidents or even mortalities, vehicle software design and testing must consider safety a top priority. ISO 26262 recommends fault injection testing as a measure to verify the functional safety of vehicles. However, the standard does not clearly specify when and where faults should be injected, and the tools to support fault injection testing for automotive software are also insufficient. In the present study, we define faults that may occur in Automotive Open System Architecture (AUTOSAR)-based automotive software and propose a fault injection method to be applied during the software development process. The proposed method can inject different types of faults that may occur in AUTOSAR-based automotive software, such as access, asymmetric, and timing errors, while minimizing performance degradation due to fault injection, and without using any separate hardware devices. The superior performance of the proposed method is demonstrated through empirical studies applied to fault injection testing of a range of vehicle electronic control unit software.
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Arasteh, Bahman. "A Program-Aware Fault-Injection Method for Dependability Evaluation Against Soft-Error Using Genetic Algorithm." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850144. http://dx.doi.org/10.1142/s021812661850144x.
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Decreasing the scale of transistors and exponential increase in the transistor counts has made the soft-errors as one of the major causes of software failures. Fault injection is a powerful method for dependability assessment of a computer system against soft-errors. A considerable number of randomly injected faults in the current methods and tools are effect-less or equivalent. To overcome this problem and reduce the cost of fault injection, this study presents a software based fault-injection method that accurately evaluates the dependability of a computer system with a limited number fault-injection. Using a genetic algorithm (GA) the most vulnerable executable paths of an input program is identified; then only the basic blocs (BBs) into the identified vulnerable paths are considered as the target of fault injection. The results of fault injections on the set of 8 traditional benchmark-programs show that the proposed method reduces about 20% of effect-less faults by avoiding the injection of faults in the error-derating blocks of a program. Furthermore, the number of injected faults is reduced to 60% of its original size in the random injection. Also, the proposed method provides more stable and accurate results than the random injection.
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Shamim Hos, Mohammod. "Web Service Based Software Implemented Fault Injection." Information Technology Journal 5, no. 1 (December 15, 2005): 138–43. http://dx.doi.org/10.3923/itj.2006.138.143.
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Li, Yi, Ping Xu, and Han Wan. "A Fault Injection System Based on QEMU Simulator and Designed for BIT Software Testing." Applied Mechanics and Materials 347-350 (August 2013): 580–87. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.580.
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An important step in the development of dependable systems is the validation of their fault tolerance properties. Fault injection has been widely used for this purpose. This paper presents a simulator implemented fault injection and monitoring environment based on the QEMU platform, called BitVaSim, which is targeted for the embedded development boards equipped with PowerPC or ARM processor together with Built-In Test software operating environment.BitVaSim takes advantage of simulation and do no harm or irruption to either the real hardware or the software, in addition, all the simulated parts are reachable so that more fault modes are available to achieve.BitVaSim uses abstract key-value pairs to describe the functional fault modes, and then simulates the hardware board as while as realistic faults incurred by hardware into the simulator, in order to monitor the activation of the faults and their impact on the target system especially the BIT system behavior in detail. Fault injection interfaces are configured to implement failure mode matching and fault conditions triggering to inject faults on demand in simulator runtime.Faults injected by BitVaSim can affect any process running on the target system (including the kernel), and it is possible to inject faults in applications for which the source code is not available.Experimental results are presented to demonstrate the accuracy and potential of BitVaSim in the evaluation of the dependability properties of the complex computer systems and the BIT system.
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Shi, Biao Biao, and Xiao Peng Gao. "An Implementation of Simulation-Based Environment for Bus Fault Injection Techniques." Advanced Materials Research 756-759 (September 2013): 4672–76. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4672.
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Reliability is the most important feature in this more and more complex computer system era. Fault injection is dependability validation technique to evaluating the system. Hardware and Software implementations of fault injection have a long history and are much more mature than simulated fault injection. In this paper, we compare the differences between these three types of fault injections at first. Then, we identify and understand the types of fault. We design a low-cost, simulation-based fault injection system and design experiments to verify the correctness.
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Aguilera, Carlos J. G., Cristiano P. Chenet, and Tiago R. Balen. "Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation." Journal of Integrated Circuits and Systems 11, no. 3 (December 28, 2016): 185–91. http://dx.doi.org/10.29292/jics.v11i3.443.
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This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.
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Gangolli, Aakash, Qusay H. Mahmoud, and Akramul Azim. "A Systematic Review of Fault Injection Attacks on IoT Systems." Electronics 11, no. 13 (June 28, 2022): 2023. http://dx.doi.org/10.3390/electronics11132023.
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The field of the Internet of Things (IoT) is growing at a breakneck pace and its applications are becoming increasingly sophisticated with time. Fault injection attacks on IoT systems are aimed at altering software behavior by introducing faults into the hardware devices of the system. Attackers introduce glitches into hardware components, such as the clock generator, microcontroller, and voltage source, which can affect software functioning, causing it to misbehave. The methods proposed in the literature to handle fault injection attacks on IoT systems vary from hardware-based attack detection using system-level properties to analyzing the IoT software for vulnerabilities against fault injection attacks. This paper provides a systematic review of the various techniques proposed in the literature to counter fault injection attacks at both the system level and the software level to identify their limitations and propose solutions to address them. Hybrid attack detection methods at the software level are proposed to enhance the security of IoT systems against fault injection attacks. Solutions to the identified limitations are suggested using machine learning, dynamic code instrumentation tools, hardware emulation platforms, and concepts from the software testing domain. Future research possibilities, such as the use of software fault injection tools and supervised machine learning for attack detection at the software level, are investigated.
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Geoghegan, Sean J., and D. R. Avresky. "Designing and Validation of Error Detection Software." International Journal of Reliability, Quality and Safety Engineering 05, no. 04 (December 1998): 337–57. http://dx.doi.org/10.1142/s0218539398000297.
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We propose a systematic approach for design and validation of error detection software. Formally, the semantic of a specification is represented by a transition system. This representation is then used to generate a flowgraph or ddgraph which is used to construct an execution path tree. The information obtained from this algorithm representation is used to aid in the design of software-based fault detection techniques for hardware faults. Flowgraph and ddgraph representations provide information to predict future program flow. During execution, the current program path is recorded, along with the expected path. Checks are placed to verify that the program path follows the predicted path. Algorithm-based fault tolerance (ABFT) techniques are used to detect data structure corrupting faults and to improve the fault coverage. Fault coverage provided by this approach for different types of hardware faults has been estimated through experiments with the software-based fault injection tool (SOFIT) and the data is presented to demonstrate the effectiveness of the method.
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Azimi, Sarah, Corrado De Sio, Daniele Rizzieri, and Luca Sterpone. "Analysis of Single Event Effects on Embedded Processor." Electronics 10, no. 24 (December 18, 2021): 3160. http://dx.doi.org/10.3390/electronics10243160.
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The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.
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Węgrzyn, Mariusz, and Janusz Sosnowski. "Tracing Fault Effects in FPGA Systems." International Journal of Electronics and Telecommunications 60, no. 1 (March 1, 2014): 92–97. http://dx.doi.org/10.2478/eletel-2014-0012.
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Abstract The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets - SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.
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Kanawati, G. A., N. A. Kanawati, and J. A. Abraham. "FERRARI: a flexible software-based fault and error injection system." IEEE Transactions on Computers 44, no. 2 (1995): 248–60. http://dx.doi.org/10.1109/12.364536.
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Muñoz-Quijada, Maria, Luis Sanz, and Hipolito Guzman-Miranda. "A Virtual Device for Simulation-Based Fault Injection." Electronics 9, no. 12 (November 24, 2020): 1989. http://dx.doi.org/10.3390/electronics9121989.
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This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable Gate Array)-based hardware devices. Multiple instances of the virtual device can be launched in parallel in order to speed-up the fault injection campaigns, without any preexisting limitations on number, such as available license seats, since the virtual device can be compiled with the open-source simulator GHDL. This virtual device also allows one to find bugs in both software and firmware, and to reproduce in simulation, with total visibility of the internal states, corner cases that may have occurred in the real hardware.
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Bhandari, Guru Prasad, Ratneshwer Gupta, and Satyanshu Kumar Upadhyay. "An approach for fault prediction in SOA-based systems using machine learning techniques." Data Technologies and Applications 53, no. 4 (September 3, 2019): 397–421. http://dx.doi.org/10.1108/dta-03-2019-0040.
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Purpose Software fault prediction is an important concept that can be applied at an early stage of the software life cycle. Effective prediction of faults may improve the reliability and testability of software systems. As service-oriented architecture (SOA)-based systems become more and more complex, the interaction between participating services increases frequently. The component services may generate enormous reports and fault information. Although considerable research has stressed on developing fault-proneness prediction models in service-oriented systems (SOS) using machine learning (ML) techniques, there has been little work on assessing how effective the source code metrics are for fault prediction. The paper aims to discuss this issue. Design/methodology/approach In this paper, the authors have proposed a fault prediction framework to investigate fault prediction in SOS using metrics of web services. The effectiveness of the model has been explored by applying six ML techniques, namely, Naïve Bayes, Artificial Networks (ANN), Adaptive Boosting (AdaBoost), decision tree, Random Forests and Support Vector Machine (SVM), along with five feature selection techniques to extract the essential metrics. The authors have explored accuracy, precision, recall, f-measure and receiver operating characteristic curves of the area under curve values as performance measures. Findings The experimental results show that the proposed system can classify the fault-proneness of web services, whether the service is faulty or non-faulty, as a binary-valued output automatically and effectively. Research limitations/implications One possible threat to internal validity in the study is the unknown effects of undiscovered faults. Specifically, the authors have injected possible faults into the classes using Java C3.0 tool and only fixed faults are injected into the classes. However, considering the Java C3.0 community of development, testing and use, the authors can generalize that the undiscovered faults should be few and have less impact on the results presented in this study, and that the results may be limited to the investigated complexity metrics and the used ML techniques. Originality/value In the literature, only few studies have been observed to directly concentrate on metrics-based fault-proneness prediction of SOS using ML techniques. However, most of the contributions are regarding the fault prediction of the general systems rather than SOS. A majority of them have considered reliability, changeability, maintainability using a logging/history-based approach and mathematical modeling rather than fault prediction in SOS using metrics. Thus, the authors have extended the above contributions further by applying supervised ML techniques over web services metrics and measured their capability by employing fault injection methods.
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Yin, Yuan Wei, Chao Xuan Shang, Yan Heng Ma, and Gang Li. "The Application of Fault Injection Using Circuit Simulation in Testability Verification." Applied Mechanics and Materials 347-350 (August 2013): 937–41. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.937.
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The fault injection technology is an important aspect in testability verification, because the actual fault injection in equipment can damage itself, so using circuit simulation fault injection method to instead. Research on the simulation method that based on PSPICE, using VC++ software to design a simulated fault injection system, its structure and function to achieve workflow introduced. Finally, taking a circuit for example uses the system to fault injection and analysis to prove the availability and correctness of the system.
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Carrozza, Gabriella, and Roberto Natella. "A Recovery-Oriented Approach for Software Fault Diagnosis in Complex Critical Systems." International Journal of Adaptive, Resilient and Autonomic Systems 2, no. 1 (January 2011): 77–104. http://dx.doi.org/10.4018/jaras.2011010105.
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This paper proposes an approach to software faults diagnosis in complex fault tolerant systems, encompassing the phases of error detection, fault location, and system recovery. Errors are detected in the first phase, exploiting the operating system support. Faults are identified during the location phase, through a machine learning based approach. Then, the best recovery action is triggered once the fault is located. Feedback actions are also used during the location phase to improve detection quality over time. A real world application from the Air Traffic Control field has been used as case study for evaluating the proposed approach. Experimental results, achieved by means of fault injection, show that the diagnosis engine is able to diagnose faults with high accuracy and at a low overhead.
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Lee, Sangho, and Seunghwan Shin. "Software Fault Injection Test Methodology for the Software Verification of ISO 26262 Standards-based." Transactions of the Korean Society of Automotive Engineers 22, no. 3 (April 1, 2014): 68–74. http://dx.doi.org/10.7467/ksae.2014.22.3.068.
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Shin, Donghoon, Kang-moon Park, and Manbok Park. "Development of Fail-Safe Algorithm for Exteroceptive Sensors of Autonomous Vehicles." Electronics 9, no. 11 (October 26, 2020): 1774. http://dx.doi.org/10.3390/electronics9111774.
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This paper presents a fail-safe algorithm for the exteroceptive sensors of autonomous vehicles. The proposed fault diagnosis mechanism consists of three parts: (1) fault detecting by a duplication-comparison method, (2) fault isolating by possible area prediction and (3) in-vehicle sensor fail-safes. The main ideas are the usage of redundant external sensor pairs, which estimate the same target, whose results are compared to detect the fault by a modified duplication-comparison method and the novel fault isolation method using target predictions. By comparing the estimations of surrounding vehicles and the raw measurement data, the location of faults can be determined whether they are from sensors themselves or a software error. In addition, faults were isolated by defining possible areas where existing sensor coordinates could be measured, which can be predicted by using previous estimation results. The performance of the algorithm has been tested by using offline vehicle data analysis via MATLAB. Various fault injection experiments were conducted and the performance of the suggested algorithm was evaluated based on the time interval between injection and the detection of faults.
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Abboush, Mohammad, Daniel Bamal, Christoph Knieke, and Andreas Rausch. "Hardware-in-the-Loop-Based Real-Time Fault Injection Framework for Dynamic Behavior Analysis of Automotive Software Systems." Sensors 22, no. 4 (February 10, 2022): 1360. http://dx.doi.org/10.3390/s22041360.
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A well-known challenge in the development of safety-critical systems in vehicles today is that reliability and safety assessment should be rigorously addressed and monitored. As a matter of fact, most safety problems caused by system failures can lead to serious hazards and loss of life. Notwithstanding the existence of several traditional analytical techniques used for evaluation based on specification documents, a complex design, with its multivariate dynamic behavior of automotive systems, requires an effective method for an experimental analysis of the system’s response under abnormal conditions. Simulation-based fault injection (FI) is a recently developed approach to simulate the system behavior in the presence of faults at an early stage of system development. However, in order to analyze the behavior of the system accurately, comprehensively and realistically, the real-time conditions, as well as the dynamic system model of the vehicle, should be considered. In this study, a real-time FI framework is proposed based on a hardware-in-the-loop (HiL) simulation platform and a real-time electronic control unit (ECU) prototype. The framework is modelled in the MATLAB/Simulink environment and implemented in the HiL simulation to enable the analysis process in real time during the V-cycle development process. With the objective of covering most of the potential faults, nine different types of sensor and actuator control signal faults are injected programmatically into the HiL system as single and multiple faults without changing the original system model. Besides, the model of the whole system, containing vehicle dynamics with the environment system model, is considered with complete and comprehensive behavioral characteristics. A complex gasoline engine system is used as a case study to demonstrate the capabilities and advantages of the proposed framework. Through the proposed framework, transient and permanent faults are injected in real time during the operation of the system. Finally, experimental results show the effects of single and simultaneous faults on the system performance under a faulty mode compared to the golden running mode.
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AVRESKY, DIMITER R., and PRADEEP K. TAPADIYA. "A MULTI-STAGED SOFTWARE DESIGN APPROACH FOR FAULT TOLERANCE." International Journal of Reliability, Quality and Safety Engineering 01, no. 02 (June 1994): 197–218. http://dx.doi.org/10.1142/s0218539394000155.
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This paper presents a multi-stage software design approach for fault-tolerance. In the first stage, a formalism is introduced to represent the behavior of the system by means of a set of assertions. This formalism enables an execution tree (ET) to be generated where each path from the root to the leaf is, in fact, a well-defined formula. During the automatic generation of the execution tree, properties like completeness and consistency of the set of assertions can be verified and consequently design faults can be revealed. In the second stage, the testing strategy is based on a set of WDFs. This set represents the structural deterministic test for the model of the software system and provides a framework for the generation of a functional deterministic test for the code implementation of the model. This testing strategy can reveal the implementation faults in the program code. In the third stage, the fault-tolerance of the software system against hardware failures is improved in a way such that the design and implementation features obtained from the first two stages are preserved. The proposed approach provides a high level of user-transparency by employing object-oriented principles of data encapsulation and polymorphism. The reliability of the software system against hardware failures is also evaluated. A tool, named Software Fault-Injection Tool (SFIT), is developed to estimate the reliability of a software system.
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Abboush, Mohammad, Daniel Bamal, Christoph Knieke, and Andreas Rausch. "Intelligent Fault Detection and Classification Based on Hybrid Deep Learning Methods for Hardware-in-the-Loop Test of Automotive Software Systems." Sensors 22, no. 11 (May 27, 2022): 4066. http://dx.doi.org/10.3390/s22114066.
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Hardware-in-the-Loop (HIL) has been recommended by ISO 26262 as an essential test bench for determining the safety and reliability characteristics of automotive software systems (ASSs). However, due to the complexity and the huge amount of data recorded by the HIL platform during the testing process, the conventional data analysis methods used for detecting and classifying faults based on the human expert are not realizable. Therefore, the development of effective means based on the historical data set is required to analyze the records of the testing process in an efficient manner. Even though data-driven fault diagnosis is superior to other approaches, selecting the appropriate technique from the wide range of Deep Learning (DL) techniques is challenging. Moreover, the training data containing the automotive faults are rare and considered highly confidential by the automotive industry. Using hybrid DL techniques, this study proposes a novel intelligent fault detection and classification (FDC) model to be utilized during the V-cycle development process, i.e., the system integration testing phase. To this end, an HIL-based real-time fault injection framework is used to generate faulty data without altering the original system model. In addition, a combination of the Convolutional Neural Network (CNN) and Long Short-Term Memory (LSTM) is employed to build the model structure. In this study, eight types of sensor faults are considered to cover the most common potential faults in the signals of ASSs. As a case study, a gasoline engine system model is used to demonstrate the capabilities and advantages of the proposed method and to verify the performance of the model. The results prove that the proposed method shows better detection and classification performance compared to other standalone DL methods. Specifically, the overall detection accuracies of the proposed structure in terms of precision, recall and F1-score are 98.86%, 98.90% and 98.88%, respectively. For classification, the experimental results also demonstrate the superiority under unseen test data with an average accuracy of 98.8%.
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Nikseresht, Mohaddaseh, Jens Vankeirsbilck, and Jeroen Boydens. "A Study on Selective Implementation Approaches for Soft Error Detection Using S-SWIFT-R." Electronics 11, no. 20 (October 19, 2022): 3380. http://dx.doi.org/10.3390/electronics11203380.
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This article analyzes diverse criteria for effectively implementing selective hardening against soft errors through software-based strategies. The goal is to obtain maximum fault coverage with the least amount of overhead for each specific application. To achieve this objective, the analysis is conducted based on two important phases, pre-selection and selective hardening of registers. In the pre-selection phase, the impact of the two most used selection metrics has been examined: (1) selecting registers based on their memory interaction vs. (2) selecting registers depending on fault injection vulnerability. Toward the selective hardening phase, the impact of gradually increasing the number of registers to protect is examined. Experiments have been conducted on 8 academic case studies and 1 industrial case study. Faults have been injected into the case studies using our in-house fault injector. The results indicate that selecting registers based on the fault injected into the system has an overall 10% better performance in comparison to selecting registers based on the memory interaction in 6 out of 8 academic case studies and also the industrial case study. Additionally, there is a significant improvement in reliability when increasing the number of registers to protect at the expense of rising overhead. In this work, these comparisons and analyses are presented.
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Berre, Inga, Ivar Stefansson, and Eirik Keilegavlen. "Fault slip in hydraulic stimulation of geothermal reservoirs: Governing mechanisms and process-structure interaction." Leading Edge 39, no. 12 (December 2020): 893–900. http://dx.doi.org/10.1190/tle39120893.1.
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Hydraulic stimulation of geothermal reservoirs in low-permeability basement and crystalline igneous rock can enhance permeability by reactivation and shear dilation of existing fractures. The process is characterized by interaction between fluid flow, deformation, and the fractured structure of the formation. The flow is highly affected by the fracture network, which in turn is deformed because of hydromechanical stress changes caused by the fluid injection. This process-structure interaction is decisive for the outcome of hydraulic stimulation, and, in analysis of governing mechanisms, physics-based modeling has potential to complement field and experimental data. Here, we show how recently developed simulation technology is a valuable tool to understand governing mechanisms of hydromechanical coupled processes and the reactivation and deformation of faults. The methodology fully couples flow in faults and matrix with poroelastic matrix deformation and a contact mechanics model for the faults, including dilation because of slip. Key elements are high aspect ratios of faults and strong nonlinearities in highly coupled governing equations. Example simulations using our open-source software illustrate direct and indirect hydraulic fault reactivation and corresponding permeability enhancement. We investigate the effect of the fault and matrix permeability and the Biot coefficient. A higher matrix permeability leads to more leakage from a permeable fault and thus suppresses reactivation and slip of the fault compared to the case with a lower matrix permeability. If a fault is a barrier to flow, increase of pressure because of the fluid injection results in stabilization of the fault; the situation is opposite if the fault is highly permeable compared to the matrix. For the given setup, lowering the Biot coefficient results in more slip than the base case. While conceptually simple, the examples illustrate the strong hydromechanical couplings and the prospects of physics-based numerical models in investigating the dynamics.
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Ferraretto, Davide, and Graziano Pravadelli. "Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software." Journal of Electronic Testing 32, no. 1 (January 9, 2016): 43–57. http://dx.doi.org/10.1007/s10836-015-5555-z.
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Vimaladevi M. and Zayaraz G. "A Game Theoretic Approach for Quality Assurance in Software Systems Using Antifragility-Based Learning Hooks." Journal of Cases on Information Technology 22, no. 3 (July 2020): 1–18. http://dx.doi.org/10.4018/jcit.2020070101.
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The use of software in mission critical applications poses greater quality needs. Quality assurance activities are aimed at ensuring such quality requirements of the software system. Antifragility is a property of software that increases its quality as a result of errors, faults, and attacks. Such antifragile software systems proactively accepts the errors and learns from these errors and relies on test-driven development methodology. In this article, an innovative approach is proposed which uses a fault injection methodology to perform the task of quality assurance. Such a fault injection mechanism makes the software antifragile and it gets better with the increase in the intensity of such errors up to a point. A software quality game is designed as a two-player game model with stressor and backer entities. The stressor is an error model which injects errors into the software system. The software system acts as a backer, and tries to recover from the errors. The backer uses a cheating mechanism by implementing software Learning Hooks (SLH) which learn from the injected errors. This makes the software antifragile and leads to improvement of the code. Moreover, the SLH uses a Q-Learning reinforcement algorithm with a hybrid reward function to learn from the incoming defects. The game is played for a maximum of K errors. This approach is introduced to incorporate the anti-fragility aspects into the software system within the existing framework of object-oriented development. The game is run at the end of every increment during the construction of object-oriented systems. A detailed report of the injected errors and the actions taken is output at the end of each increment so that necessary actions are incorporated into the actual software during the next iteration. This ensures at the end of all the iterations, the software is immune to majority of the so-called Black Swans. The experiment is conducted with an open source Java sample and the results are studied selected two categories of evaluation parameters. The defect related performance parameters considered are the defect density, defect distribution over different iterations, and number of hooks inserted. These parameters show much reduction in adopting the proposed approach. The quality parameters such as abstraction, inheritance, and coupling are studied for various iterations and this approach ensures considerable increases in these parameters.
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Jayasinghe, Darshana, Aleksandar Ignjatovic, Roshan Ragel, Jude Angelo Ambrose, and Sri Parameswaran. "QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks." ACM Transactions on Design Automation of Electronic Systems 26, no. 5 (June 5, 2021): 1–36. http://dx.doi.org/10.1145/3443706.
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Side channel analysis attacks employ the emanated side channel information to deduce the secret keys from cryptographic implementations by analyzing the power traces during execution or scrutinizing faulty outputs. To be effective, a countermeasure must remove or conceal as many as possible side channels. However, many of the countermeasures against side channel attacks are applied independently. In this article, the authors present a novel countermeasure (referred to as QuadSeal ) against Power Analysis Attacks and Electromagentic Fault Injection Attacks (FIAs), which is an extension of the work proposed in Reference [27]. The proposed solution relies on algorithmically balancing both Hamming distances and Hamming weights (where the bit transitions on the registers and gates are balanced, and the total number of 1s and 0s are balanced) by the use of four identical circuits with differing inputs and modified SubByte tables. By randomly rotating the four encryptions, the system is protected against variations, path imbalances, and aging effects. After generating the ciphertext, the output of each circuit is compared against each other to detect any fault injections or to correct the faulty ciphertext to gain reliability. The proposed countermeasure allows components to be switched off to save power or to run four executions in parallel for high performance when resistance against power analysis attacks is not of high priority, which is not available with the existing countermeasures (except software based where source code can be changed). The proposed countermeasure is implemented for Advanced Encryption Standard (AES) and tested against Correlation Power Analysis and Mutual Information Attacks attacks (for up to a million traces), and none of the secret keys was found even after one million power traces (the unprotected AES circuit is vulnerable for power analysis attacks within 5,000 power traces). A detection circuit (referred to as C-FIA circuit) is operated using the algorithmic redundancy presented in four circuits of QuadSeal to mitigate Electromagnetic Fault Injection Attacks. Using Synopsys PrimeTime, we measured the power dissipation of QuadSeal registers and XOR gates to test the effectiveness of Quadruple balancing methodology. We tested the QuadSeal countermeasure with C-FIA circuit against Differential Fault Analysis Attacks up to one million traces; no bytes of the secret key were found. This is the smallest known circuit that is capable of withstanding power-based side channel attacks when electromagnetic injection attack resistance, process variations, path imbalances, and aging effects are considered.
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Azimi, Sarah, Corrado De Sio, Andrea Portaluri, Daniele Rizzieri, Eleonora Vacca, Luca Sterpone, and David Merodio Codinachs. "Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems." Electronics 12, no. 1 (December 30, 2022): 169. http://dx.doi.org/10.3390/electronics12010169.
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The continuous scaling of electronic components has led to the development of high-performance microprocessors that are suitable even for safety-critical applications where radiation-induced errors such as Single Event Effects (SEEs) can have a significant impact on the performance and reliability of the system. This work is dedicated to investigating the reliability of systems based on programmable hardware and Real-time operating Systems (RTOS) in the presence of architectural faults induced by soft errors in the configuration memory of the programmable hardware. We performed a proton radiation test campaigned at PSI radiation facility to identify the fault model affecting the configuration memory of Xilinx Zynq-7020 reconfigurable AP-Soc Device. The identified fault model in terms of SEU and MBU clusters has been used to evaluate the impact of proton-induced faults on applications running within FreeRTOS on a Microblaze soft processor. A Single Event Multiple Upset fault model resulting from a proton test is presented, focusing on characteristics such as shape, size, and frequency of observed cluster of errors. We conduct two fault injection campaigns and analyze the results to assess the effect of cluster size on system reliability. Moreover, we discuss software exceptions caused by faults that can affect the hardware structure of the soft processor.
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Ruano, Óscar, Francisco García-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, and Juan Antonio Maestro. "Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial." Sensors 21, no. 4 (February 17, 2021): 1392. http://dx.doi.org/10.3390/s21041392.
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Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.
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Aponte-Moreno, Alexander, Felipe Restrepo-Calle, and Cesar Pedraza. "A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations." Journal of Integrated Circuits and Systems 16, no. 3 (April 2, 2022): 1–14. http://dx.doi.org/10.29292/jics.v16i3.539.
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Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.
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Kazemi, Zahra, David Hely, Mahdi Fazeli, and Vincent Beroulle. "A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications." Electronics 9, no. 7 (July 16, 2020): 1153. http://dx.doi.org/10.3390/electronics9071153.
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The Internet-of-Things (IoT) has gained significant importance in all aspects of daily life, and there are many areas of application for it. Despite the rate of expansion and the development of infrastructure, such systems also bring new concerns and challenges. Security and privacy are at the top of the list and must be carefully considered by designers and manufacturers. Not only do the devices need to be protected against software and network-based attacks, but proper attention must also be paid to recently emerging hardware-based attacks. However, low-cost unit software developers are not always sufficiently aware of existing vulnerabilities due to these kinds of attacks. To tackle the issue, various platforms are proposed to enable rapid and easy evaluation against physical attacks. Fault attacks are the noticeable type of physical attacks, in which the normal and secure behavior of the targeted devices is liable to be jeopardized. Indeed, such attacks can cause serious malfunctions in the underlying applications. Various studies have been conducted in other research works related to the different aspects of fault injection. Two of the primary means of fault attacks are clock and voltage fault injection. These attacks can be performed with a moderate level of knowledge, utilizing low-cost facilities to target IoT systems. In this paper, we explore the main parameters of the clock and voltage fault generators. This can help hardware security specialists to develop an open-source platform and to evaluate their design against such attacks. The principal concepts of both methods are studied for this purpose. Thereafter, we conclude our paper with the need for such an evaluation platform in the design and production cycle of embedded systems and IoT devices.
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Choi, Ki-Yong, and Jung-Won Lee. "CNN-Based Fault Localization Method Using Memory-Updated Patterns for Integration Test in an HiL Environment." Applied Sciences 9, no. 14 (July 12, 2019): 2799. http://dx.doi.org/10.3390/app9142799.
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Automotive electronic components are tested via hardware-in-the-loop (HiL) testing at the unit and integration test stages, according to ISO 26262. It is difficult to obtain debugging information from the HiL test because the simulator runs a black-box test automatically, depending on the scenario in the test script. At this time, debugging information can be obtained in HiL tests, using memory-updated information, without the source code or the debugging tool. However, this method does not know when the fault occurred, and it is difficult to select the starting point of debugging if the execution flow of the software is not known. In this paper, we propose a fault-localization method using a pattern in which each memory address is updated in the HiL test. Via a sequential pattern-mining algorithm in the memory-updated information of the transferred unit tests, memory-updated patterns are extracted, and the system learns using a convolutional neural network. Applying the learned pattern in the memory-updated information of the integration test can determine the fault point from the normal pattern. The point of departure from the normal pattern is highlighted as a fault-occurrence time, and updated addresses are presented as fault candidates. We applied the proposed method to an HiL test of an OSEK/VDX-based electronic control unit. Through fault-injection testing, we could find the cause of faults by checking the average memory address of 3.28%, and we could present the point of fault occurrence with an average accuracy of 80%.
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Voas, J., A. Binns, J. Payne, and R. Mills. "An Experiment in Applying a Fault Injection-Based Hazard Mitigation Technique to a Software Automobile Control System." IFAC Proceedings Volumes 28, no. 25 (November 1995): 193–98. http://dx.doi.org/10.1016/s1474-6670(17)44844-0.
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Rösch, Susanne, Dmitry Tikhonov, Daniel Schütz, and Birgit Vogel-Heuser. "Model-based testing of PLC software: test of plants' reliability by using fault injection on component level." IFAC Proceedings Volumes 47, no. 3 (2014): 3509–15. http://dx.doi.org/10.3182/20140824-6-za-1003.01238.
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Cheng, Keqiang, Qiang Wang, Dongyu Yang, Qingyun Dai, and Meilin Wang. "Digital-Twins-Driven Semi-Physical Simulation for Testing and Evaluation of Industrial Software in a Smart Manufacturing System." Machines 10, no. 5 (May 18, 2022): 388. http://dx.doi.org/10.3390/machines10050388.
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To satisfy the needs of the individualized manufacturing of products, the smart manufacturing system (SMS) is frequently reconfigured. To quickly verify the reliability and adaptability of industrial software in reconfiguring the SMS for new or upgraded product orders, a semi-physical simulation method for testing and evaluation of industrial software is proposed based on digital-twins-driven technology. By establishing a semi-physical simulation model of SMS, the reliability and robustness of the software system are quickly verified by running industrial software in various manufacturing scenarios. In this paper, the key technologies to carry out semi-physical simulation testing and evaluation of industrial software for SMSs are expounded in detail, including how to synchronize cyber and physical systems, how to conduct semi-physical accelerated simulation testing, and how to identify defects quickly in industrial software used in actual production environments. By establishing a semi-physical simulation production line model for stepper motors, the effectiveness and practicality of the proposed approach are verified, and the testing verification time of industrial software is significantly reduced. Finally, the robustness of the industrial software for SMS is further verified by conducting fault injection testing, so as to provide implications for fault prognostics or fault-prevention research.
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So, Hwisoo, Moslem Didehban, Yohan Ko, Reiley Jeyapaul, Jongho Kim, Youngbin Kim, Kyoungwoo Lee, and Aviral Shrivastava. "Revisiting Symptom-Based Fault Tolerant Techniques against Soft Errors." Electronics 10, no. 23 (December 4, 2021): 3028. http://dx.doi.org/10.3390/electronics10233028.
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Aggressive technology scaling and near-threshold computing have made soft error reliability one of the leading design considerations in modern embedded microprocessors. Although traditional hardware/software redundancy-based schemes can provide a high level of protection, they incur significant overheads in terms of performance and hardware resources. The considerable overheads from such full redundancy-based techniques has motivated researchers to propose low-cost soft error protection schemes, such as symptom-based error protection schemes. The main idea behind a symptom-based error protection scheme is that soft errors in the system will quickly generate some symptoms, such as exceptions, branch mispredictions, cache or TLB misses, or unpredictable variable values. Therefore, monitoring such infrequent symptoms makes it possible to cover the manifestation of failures caused by soft errors. Symptom-based protection schemes have been suggested as shortcuts to achieve acceptable reliability with comparable overheads. Since the symptom-based protection schemes seem attractive due to their generality and simplicity, even state-of-the-art protection schemes exploit them as the baseline protections. However, our detailed analysis of the fault coverage and performance overheads of such schemes reveals that the user-visible failure coverage, particularly of ReStore, is limited (29% on average). By contrast, the runtime overheads are significant (40% on average) because the majority of the fault injection experiments, which were considered as detected/recovered failures by low-level symptoms, are actually benign faults by program-level masking effects.
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Li, Ling, Jie Yao, Fen Liu, and Zhi Fu Weng. "Hardware-In-Loop Test Platform for Electronic Control Unit of Fuel Cell System." Applied Mechanics and Materials 529 (June 2014): 465–70. http://dx.doi.org/10.4028/www.scientific.net/amm.529.465.
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Due to the features of complicated test environment, variable parameters, and limited conditions in real car experiment, it has proposed a Hardware-in-Loop test platform for Fuel Cell System (Short for FCS) based on hardware of NI PXI and software of NI Labview to fuel cell vehicle. According to FCS’s control strategy, I/O signal map, CAN communication and sensor characteristics, it has designed the hardware configuration, software program, test interface, and rapidly made validation to control logic and fault diagnosis of Fuel Cell System’s Electronic Control Unit (Short for FCU). The experiment result shows that this test platform is effective for FCU control logic validation, system status monitor, fault injection, fault tracing, and it can shorten the vehicle research and development cycle, reduce the development cost, optimize test environment and promise safety for test engineer. This test platform will make good effect to vehicle electrical system development and supply reference for vehicle test.
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Li, Ling, Xu Nian Lai, Wei Ming Liang, Bing Long Wang, and Fen Liu. "Research and Development of Test Platform for Plug-In Fuel Cell Vehicle’s Hydrogen Management System." Applied Mechanics and Materials 241-244 (December 2012): 721–27. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.721.
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Due to the features of complicated test environment, variable parameters, and limited conditions in real car experiment, it has proposed a Hardware-in-Loop test platform in this paper for Hydrogen Management System (Short for HMS) based on hardware of NI PXI and software of NI Labview to plug-in fuel cell vehicle. According to HMS’s control strategy, I/O signal map, CAN communication and sensor characteristics, it has designed the hardware configuration, software program, test interface, and rapidly made validation to control logic and fault diagnosis of Hydrogen Management Unit (Short for HMU). The experiment result shows that this test platform is effective for HMU control logic validation, system status monitor, fault injection, fault tracing, and it can shorten the vehicle research and development cycle, reduce the development cost, optimize test environment and promise safety for test engineer. This test platform will make good effect to vehicle electrical system development and supply reference for vehicle test.
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Liu, Wei Tao, Jian Jun Shen, and Yun Juan Liu. "Deterministic Method of Floor Rock Permeability Tensor of Mining over Confined Water and Application in Numerical Simulation." Applied Mechanics and Materials 204-208 (October 2012): 4840–44. http://dx.doi.org/10.4028/www.scientific.net/amm.204-208.4840.
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Based on equivalent continuum media theory of fractured rock mass, the author got the permeability tensor of floor strata in some mine according to core logging method, drilling imaging method and boring water injection method, and determined the floor rock permeability tensor using correction method. The author simulated the floor inrush problem by coupling fluid-solid theory and anisotropic flow model with FLAC3D software. The result shows that, the destroyed depth of floor and the confined water rising height are all slight when the coal mining workface is 150m apart from the fault, but they increase obviously when the coal mining workface is 30m apart from the fault, and are extremely easy to get through and casue water inrush through fault.
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Choi, Ki-Yong, and Jung-Won Lee. "Fault Localization by Comparing Memory Updates between Unit and Integration Testing of Automotive Software in an Hardware-in-the-Loop Environment." Applied Sciences 8, no. 11 (November 15, 2018): 2260. http://dx.doi.org/10.3390/app8112260.
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During the inspection stage, an integration test is performed on electronic automobile parts that have passed a unit test. The faults found during this test are reported to the developer, who subsequently modifies the source code. If the tester provides the developer with memory usage information (such as functional symbol or interface signal), which works differently from normal operation in failed Hardware-in-the-Loop (HiL) testing (even when the tester has no source code), that information will be useful for debugging. In this paper, we propose a fault localization method for automotive software in an HiL environment by comparing the analysis results of updated memory between units and integration tests. Analyzing the memory usage of a normally operates unit test, makes it possible to obtain memory-updated information necessary for the operation of that particular function. By comparing this information to the memory usage when a fault occurs during an integration test, erroneously operated symbols and stored values are presented as potential root causes of the fault. We applied the proposed method to HiL testing for an OSEK/VDX-based electronic control unit (ECU). As a result of testing using fault injection, we confirmed that the fault causes can be found by checking the localized memory symbols with an average of 5.77%. In addition, when applying this methodology to a failure that occurred during a body control module (BCM) (which provides seat belt warnings) test, we could identify a suspicious symbol and find the cause of the test failure with only 8.54% of localized memory symbols.
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Shi, Qi, Lu Li, Jiaqi Feng, Wen Chen, and Jinpei Yu. "Automated Model Hardening with Reinforcement Learning for On-Orbit Object Detectors with Convolutional Neural Networks." Aerospace 10, no. 1 (January 16, 2023): 88. http://dx.doi.org/10.3390/aerospace10010088.
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On-orbit object detection has received extensive attention in the field of artificial intelligence (AI) in space research. Deep-learning-based object-detection algorithms are often computationally intensive and rely on high-performance devices to run. However, those devices usually lack space-qualified versions, and they can hardly meet the reliability requirement if directly deployed on a satellite platform, due to software errors induced by the space environment. In this paper, we evaluated the impact of space-environment-induced software errors on object-detection algorithms through large-scale fault injection tests. Aside from silent data corruption (SDC), we propose an extended criterial SDC-0.1 to better quantify the effect of the transient faults on the object-detection algorithms. Considering that a bit-flip error could cause severe detection result corruption in many cases, we propose a novel automated model hardening with reinforcement learning (AMHR) framework to solve this problem. AMHR searches for error-sensitive kernels in a convolutional neural network (CNN) through trial and error with a deep deterministic policy gradient (DDPG) agent and has fine-grained modular-level redundancy to increase the fault tolerance of the CNN-based object detectors. Compared to other selective hardening methods, AMHR achieved the lowest SDC-0.1 rates for various detectors and could tremendously improve the mean average precision (mAP) of the SSD detector by 28.8 in the presence of multiple errors.
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Aerabi, Ehsan, David Hély, Cyril Bresch, Athanasios Papadimitriou, and Mahdi Fazeli. "CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes." Cryptography 5, no. 2 (May 6, 2021): 13. http://dx.doi.org/10.3390/cryptography5020013.
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CONFISCA is the first generic SIMD-based software countermeasure that can concurrently resist against Side-Channel Attack (SCA) and Fault Injection (FI). Its promising strength is presented in a PRESENT cipher case study and compared to software-based Dual-rail with Pre-charge Logic concurrent countermeasure. It has lower overhead, wider usability, and higher protection. Its protection has been compared using Correlation Power Analysis, Welch’s T-Test, Signal-to-Noise Ratio and Normalized Inter-Class Variance testing methods. CONFISCA can on-the-fly switch between its two modes of operation: The High-Performance and High-Security by having only one instance of the cipher. This gives us the flexibility to trade performance/energy with security, based on the actual critical needs.
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Karimi, Abbas, Faraneh Zarafshan, S. A. R. Al-Haddad, and Abdul Rahman Ramli. "A NovelN-Input Voting Algorithm forX-by-Wire Fault-Tolerant Systems." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/672832.
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Voting is an important operation in multichannel computation paradigm and realization of ultrareliable and real-time control systems that arbitrates among the results ofNredundant variants. These systems includeN-modular redundant (NMR) hardware systems and diversely designed software systems based onN-version programming (NVP). Depending on the characteristics of the application and the type of selected voter, the voting algorithms can be implemented for either hardware or software systems. In this paper, a novel voting algorithm is introduced for real-time fault-tolerant control systems, appropriate for applications in whichNis large. Then, its behavior has been software implemented in different scenarios of error-injection on the system inputs. The results of analyzed evaluations through plots and statistical computations have demonstrated that this novel algorithm does not have the limitations of some popular voting algorithms such as median and weighted; moreover, it is able to significantly increase the reliability and availability of the system in the best case to 2489.7% and 626.74%, respectively, and in the worst case to 3.84% and 1.55%, respectively.
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Iqbal Hossain, Muhammad, and Woo Jin Lee. "Integration testing based on indirect interaction for embedded system." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 86. http://dx.doi.org/10.11591/ijres.v8.i2.pp86-98.
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<span>Embedded systems comprise several modules that exchange data by interacting among themselves. Exchanging wrong resource data among modules may lead to execution errors or anomalies. Interacting resources produce dependencies between two modules where any change of resources by one module affects the functionality of another module. Several investigations of the embedded system such as aerospace or automobile system show interaction faults between modules are one of the major cause of critical software failures. Therefore, interaction testing is an essential phase to reduce the interaction faults and minimize the risk. The direct and indirect interaction between modules generates interaction faults where indirect interaction is made underneath the interface in which data dependence relationship with resources may cause a different outcome. We investigate errors based on the indirect interaction between modules and introduce a new test criterion for finding errors detectable by existing approaches in unit level but not in integration level. In this paper, we propose a noble approach to generate an interaction model using indirect interaction pattern and design test criteria based on different interaction errors to generate test cases. Finally, we use fault injection and data flow coverage techniques to evaluate the feasibility and effectiveness of our approach</span>
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Li, Jiemin, Shancong Zhang, and Chong Bao. "DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA." Electronics 11, no. 1 (December 30, 2021): 122. http://dx.doi.org/10.3390/electronics11010122.
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With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.
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Denil, Joachim, Paul De Meulenaere, Serge Demeyer, and Hans Vangheluwe. "DEVS for AUTOSAR-based system deployment modeling and simulation." SIMULATION 93, no. 6 (February 6, 2017): 489–513. http://dx.doi.org/10.1177/0037549716684552.
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AUTOSAR (AUTomotive Open System ARchitecture) is an open and standardized automotive software architecture, developed by automobile manufacturers, suppliers, and tool developers. Its design is a direct consequence of the increasingly important role played by software in vehicles. As design choices during the software deployment phase have a large impact on the behavior of the system, designers need to explore various trade-offs. Examples of such design choices are the mapping of software components to processors, the priorities of tasks and messages, and buffer allocation. In this paper, we evaluate the appropriateness of DEVS, the Discrete-Event System specification, for modeling and subsequent performance evaluation of AUTOSAR-based systems. Moreover, a DEVS simulation model is constructed for AUTOSAR-based electronic control units connected by a communication bus. To aid developers in evaluating a deployment solution, the simulation model is extended with co-simulation with a plant and environment model, evaluation at different levels of detail, and fault injection. Finally, we examine how the simulation model supports the relationship between the supplier and the original equipment manufacturer in the automotive industry. We demonstrate and validate our work by means of a power window case study.
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Amel Solouki, Mohammadreza, Jacopo Sini, and Massimo Violante. "Implementation of Control Flow Checking—A New Perspective Adopting Model-Based Software Design." Electronics 11, no. 19 (September 27, 2022): 3074. http://dx.doi.org/10.3390/electronics11193074.
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A common requirement of embedded software in charge of safety tasks is to guarantee the identification of random hardware failures (RHFs) that can affect digital components. RHFs are unavoidable. For this reason, the functional safety standard devoted to automotive applications requires embedded software designs able to detect and eventually mitigate them. For this purpose, various software-based error detection techniques have been proposed over the years, focusing mainly on detecting control flow errors. Many control flow checking (CFC) algorithms have been proposed to accomplish this task. However, applying these approaches can be difficult because their respective literature gives little guidance on their practical implementation in high-level programming languages, and they have to be implemented in low-level code, e.g., assembly. Moreover, the current trend in the automotive industry is to adopt the so-called model-based software design approach, where an executable algorithm model is automatically translated into C or C++ source code. This paper presents two novelties: firstly, the compliance of the experimental data on the capabilities of control flow checking (CFC) algorithms with the ISO 26262 automotive functional safety standard; secondly, by implementing the CFC algorithm in the application behavioral model, the off-the-shelves code generator seamlessly produces the hardened source code of the application. The assessment was performed using a novel fault injection environment targeting a RISC-V (RV32I) microcontroller.
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Dubreuil, Jean, Guillaume Bouffard, Bhagyalekshmy N. Thampi, and Jean-Louis Lanet. "Mitigating Type Confusion on Java Card." International Journal of Secure Software Engineering 4, no. 2 (April 2013): 19–39. http://dx.doi.org/10.4018/jsse.2013040102.
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One of the challenges for smart card deployment is the security interoperability. A smart card resistant to an attack on a given platform should be able to guarantee the same behavior on another platform. But the current implementations do not comply with this requirement. In order to improve such standardization the authors propose a framework based on annotations with an external pre-processing to switch the Java Card Virtual Machine (JCVM) into a secure mode by activating a set of countermeasures. An example has been proposed in this paper for implementing a countermeasure against type confusion with a fault attack. Smart cards are often the target of software, hardware or combined attacks. In recent days most of the attacks are based on fault injection which can modify the behavior of applications loaded onto the card, changing them into mutant applications. This countermeasure requires a transformation of the original program byte codes which remain semantically equivalent. It needs a modification of the JCVM which stays backward compatible and a dedicated framework to deploy these applications. Thus, the proposed platform can resist to a fault enabled mutant.
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Sánchez Muñoz, David, Ernesto Pérez González, Juan Fernando Piñeros, and Laura Agudelo Zapata. "Simplified Inverter-Based Generation Model for Protection and Short-Term Stability Studies in Electromagnetic Transient Resolution." TecnoLógicas 25, no. 55 (November 9, 2022): e2347. http://dx.doi.org/10.22430/22565337.2347.
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The new dynamics of inverter-based generation (IBG) and the lack of accurate models jeopardize the safety of power systems. Additionally, most of the detailed models for electromagnetic transients (EMT) from manufacturers are black boxes. For this reason, the objective of this work was to propose a generic IBG model in EMT resolution suitable for short-circuit, protections, and short-term voltage stability studies. For this purpose, the model considered different functionalities, such as synchronization in case of unbalanced voltage sags, flexible negative sequence current injection, peak current limitation, dynamic reactive power control, and fault ride-through (FRT). This model allowed grid operators to meet the challenge of performing accurate simulations with high integration of renewable resources in their energy matrix. The model was also based on a voltage-controlled current source in the ATP/EMTP software. The short-circuit response was evaluated in a simulation scenario for different fault events presenting a reliable behavior due to the consideration of technical and regulatory requirements and constraints of IBGs. Finally, the proposed model has a fast initialization and is suitable for simulations with large time steps, making it valuable for EMT simulations in large grids.
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Moheb, Aya M., Enas A. El-Hay, and Attia A. El-Fergany. "Comprehensive Review on Fault Ride-Through Requirements of Renewable Hybrid Microgrids." Energies 15, no. 18 (September 16, 2022): 6785. http://dx.doi.org/10.3390/en15186785.
Full textAbstract:
The world is interested in applying grid codes to increase the reliability of power systems through a micro-grid (MG). In a common practice, the MG comprises a wind farm, and/or photovoltaic (PV) arrays that are integrated with diesel generators and energy storage devices. Fault ride-through (FRT) capability is an important requirement of grid codes. FRT means that the MG is still connected to the grid during numerous disturbances such as faults. This is required to ensure that there is no loss of power generated due to grid faults. Reactive currents must be injected into the grid to increase the power system stability and restore voltage. To enhance FRT for doubly fed induction generator (DFIG) based WT installation, internal control modifications of rotor-side converters and grid-side converters are applied. The solutions that depend on these modifications are traditional and advanced control techniques. Advanced control techniques are needed due to the non-linear nature and less robustness of traditional ones. External hardware devices are also added to improve the FRT of DFIG which are classified into protection devices, reactive power injection devices, and energy storage devices. A comprehensive review of FRT enhancements of DFIG-based WTs, PV systems, and MGs using hardware and software methods is presented in this effort. A classification of FRT of PV systems is characterized plus various inverter control techniques are indicated. Several FRT methods for hybrid PV-WT are presented, with full comparisons. The overall operation and the schematic diagrams of the DFIG-WT with FRT methods are discussed and highlighted. Many Robust control methods for controlling grid connected AC, DC and hybrid AC/DC MGs in power systems are addressed. A total of 210 reported articles were review, including the most up-to-date papers published in the literature. This review may be used as the basis to improve system reliability for those interested in FRT methods. Various traditional and advanced control techniques to improve the FRT abilities are summarized and discussed, including protection devices, reactive power injection devices, and energy storage. In addition, the classifications of FRT hardware methods for DFIG are presented, including grid code requirements.
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Chen, Jinfu, Yansheng Lu, Huanhuan Wang, and Chengying Mao. "A Quantitative Assessment Approach to COTS Component Security." Mathematical Problems in Engineering 2013 (2013): 1–11. http://dx.doi.org/10.1155/2013/165029.
Full textAbstract:
The vulnerability of software components hinders the development of component technology. An effective assessment approach to component security level can promote the development of component technology. Thus, the current paper proposes a quantitative assessment approach to COTS (commercial-off-the-shelf) component security. The steps of interface fault injection and the assessment framework are given based on the internal factors of the tested component. The quantitative assessment algorithm and formula of component security level are also presented. The experiment results show that the approach not only can detect component security vulnerabilities effectively but also quantitatively assess the component security level. The score of component security can be accurately calculated, which represents the security level of the tested component.