Relevant bibliographies by topics / Software architecture – Reliability

Academic literature on the topic 'Software architecture – Reliability'

Author: Grafiati
Published: 4 June 2021
Last updated: 28 January 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Contents

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Software architecture – Reliability.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Software architecture – Reliability"

1

Wang, Wen-Li, Dai Pan, and Mei-Hwa Chen. "Architecture-based software reliability modeling." Journal of Systems and Software 79, no. 1 (January 2006): 132–46. http://dx.doi.org/10.1016/j.jss.2005.09.004.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

GOKHALE, SWAPNA S. "SOFTWARE RELIABILITY ANALYSIS INCORPORATING SECOND-ORDER ARCHITECTURAL STATISTICS." International Journal of Reliability, Quality and Safety Engineering 12, no. 03 (June 2005): 267–90. http://dx.doi.org/10.1142/s0218539305001768.

Full text
Abstract:
Architecture-based techniques for reliability assessment of software applications have received increased attention in the past few years due to the advent of component-based software development paradigm. Most of the prior research efforts in architecture-based analysis use the composite solution approach to solve the architecture-based models in order to estimate application reliability. Though the composite solution approach produces an accurate estimate of application reliability, it suffers from several drawbacks. The most notable drawback of the composite solution approach is that it does not allow an analysis of the sensitivity of the application reliability to the reliabilities of the components comprising the application and the application structure. The hierarchical solution approach on the other hand, has the potential of overcoming the drawbacks of the composite approach. However, in the present form, the hierarchical solution approach produces an estimate of application reliability which is only an approximation of the estimate produced by the composite approach since it does not take into consideration the second-order architectural statistics. Also, although the hierarchical solution approach can be used for sensitivity analysis, mathematical techniques to perform such analysis are lacking. Development of an accurate hierarchical solution approach to estimate application reliability based on its architecture is the focus of this paper. Using the approach described in this paper, an analytical application reliability function which incorporates second-order architectural statistics can be obtained. Sensitivity analysis techniques and expressions to determine the mean time to failure of the application are developed based on this analytical reliability function. We illustrate the reliability prediction, sensitivity analysis, and mean time to failure computation techniques presented in this paper using two case studies.
APA, Harvard, Vancouver, ISO, and other styles
3

Goševa-Popstojanova, K., and K. S. Trivedi. "Architecture-based approaches to software reliability prediction." Computers & Mathematics with Applications 46, no. 7 (October 2003): 1023–36. http://dx.doi.org/10.1016/s0898-1221(03)90116-7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

EL KHARBOUTLY, REHAB A., SWAPNA S. GOKHALE, and REDA A. AMMAR. "ARCHITECTURE-BASED SOFTWARE RELIABILITY ANALYSIS INCORPORATING CONCURRENCY." International Journal of Reliability, Quality and Safety Engineering 14, no. 05 (October 2007): 479–99. http://dx.doi.org/10.1142/s0218539307002751.

Full text
Abstract:
With the growing complexity of software applications and increasing reliance on the services provided by these applications, architecture-based reliability analysis has become the focus of several recent research efforts. Most of the prevalent research in this area does not consider simultaneous or concurrent execution of application components. Concurrency, however, may be common in modern software applications. Thus, reliability analysis considering concurrent component execution within the context of the application architecture is necessary for contemporary software applications. This paper presents an architecture-based reliability analysis methodology for concurrent software applications. Central to the methodology is a state space approach, based on discrete time Markov chains (DTMCs), to represent the application architecture taking into consideration simultaneous component execution. A closed form, analytical expression for the expected application reliability based on the average execution times, constant failure rates, and the average number of visits to the components is derived. The average number of visits to application components are obtained from the solution of the DTMC model representing the application architecture. The potential of the methodology to facilitate sensitivity analysis, identification of reliability bottlenecks, and an assessment of the impact of workload and component changes, in addition to providing a reliability estimate, is discussed. To enable the application of the methodology in practice, estimation of model parameters from different software artifacts is described. The methodology is illustrated with a case study. Finally, strategies to alleviate the state space explosion issue for an efficient application of the methodology are proposed.
APA, Harvard, Vancouver, ISO, and other styles
5

Tekinerdogan, Bedir, Hasan Sozer, and Mehmet Aksit. "Software architecture reliability analysis using failure scenarios." Journal of Systems and Software 81, no. 4 (April 2008): 558–75. http://dx.doi.org/10.1016/j.jss.2007.10.029.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Alam, Tanweer, and Mohammed Aljohani. "Software Defined Networks: Review and Architecture." IAIC Transactions on Sustainable Digital Innovation (ITSDI) 1, no. 2 (March 24, 2020): 143–51. http://dx.doi.org/10.34306/itsdi.v1i2.114.

Full text
Abstract:
In the fifth-generation communication system, secured and reliable data packets will rely on the network with high availability and low latency. The 5G network enables the dynamic control of nodes with low latency. Ultra-reliability is one of the challenging tasks in software-defined networks. The ultra-reliability feature is an interface working with high availability and low latency that brings in fifth-generation networks. The Internet of Things will work in the societies so that it required ultra-reliability features to empower the peoples as well as machines for collaborating with their neighbors. The connections among ultra-reliability networks are extremely hard situations to keep low packets corruption. The Software Defined Networks (SDN) will provide a platform for measuring, controlling, monitoring and scaling the smart objects in reality or virtually. Virtualization enables IT, specialists, to combine or separate the considerable networking or create new programmable networking among virtual machines. In this article, the authors are reviewed the architecture of SDN based on virtualization under the umbrella of 5G networks.
APA, Harvard, Vancouver, ISO, and other styles
7

El Kharboutly, Rehab, and Swapna S. Gokhale. "Efficient Reliability Analysis of Concurrent Software Applications Considering Software Architecture." International Journal of Software Engineering and Knowledge Engineering 24, no. 01 (February 2014): 43–60. http://dx.doi.org/10.1142/s0218194014500028.

Full text
Abstract:
Architecture-based reliability analysis of software applications is gaining prominence as it can provide valuable guidance to software architects during early design phases. Concurrent component execution is common among modern software applications, and hence, reliability analysis considering concurrency within the context of software architecture is essential. Our preliminary analysis approach considering concurrency suffers from state-space explosion; due to which it cannot be applied to practical software applications. This paper proposes solutions to the model specification and solution challenges arising from the state-space explosion problem. The specification challenge is alleviated using the Stochastic Reward Net (SRN) modelling paradigm which can intuitively and concisely represent concurrent software architecture at a higher level of abstraction. The computational challenge is alleviated by aggregating the original state space. Our illustrations show that aggregation introduces only a small inaccuracy into the reliability estimate, and hence, preserves the utility of the original model to produce design guidance via sensitivity analysis.
APA, Harvard, Vancouver, ISO, and other styles
8

Srinivas Rao, Sabbineni. "Evaluating Software System Reliability Using Architecture Based Approach." International Journal of Intelligent Information Systems 7, no. 1 (2018): 1. http://dx.doi.org/10.11648/j.ijiis.20180701.11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Gokhale, Swapna S. "Architecture-Based Software Reliability Analysis: Overview and Limitations." IEEE Transactions on Dependable and Secure Computing 4, no. 1 (January 2007): 32–40. http://dx.doi.org/10.1109/tdsc.2007.4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Hac, A. "Using a software reliability model to design a telecommunications software architecture." IEEE Transactions on Reliability 40, no. 4 (1991): 488–94. http://dx.doi.org/10.1109/24.93771.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Software architecture – Reliability"

1

Perugupalli, Ranganath. "Empirical assessment of architecture-based reliability of open-source software." Morgantown, W. Va. : [West Virginia University Libraries], 2004. https://etd.wvu.edu/etd/controller.jsp?moduleName=documentdata&jsp%5FetdId=3677.

Full text
Abstract:
Thesis (M.S.)--West Virginia University, 2004.
Title from document title page. Document formatted into pages; contains x, 70 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 66-70).
APA, Harvard, Vancouver, ISO, and other styles
2

Zhu, Liming Computer Science &amp Engineering Faculty of Engineering UNSW. "Software architecture evaluation for framework-based systems." Awarded by:University of New South Wales. Computer Science and Engineering, 2007. http://handle.unsw.edu.au/1959.4/28250.

Full text
Abstract:
Complex modern software is often built using existing application frameworks and middleware frameworks. These frameworks provide useful common services, while simultaneously imposing architectural rules and constraints. Existing software architecture evaluation methods do not explicitly consider the implications of these frameworks for software architecture. This research extends scenario-based architecture evaluation methods by incorporating framework-related information into different evaluation activities. I propose four techniques which target four different activities within a scenario-based architecture evaluation method. 1) Scenario development: A new technique was designed aiming to extract general scenarios and tactics from framework-related architectural patterns. The technique is intended to complement the current scenario development process. The feasibility of the technique was validated through a case study. Significant improvements of scenario quality were observed in a controlled experiment conducted by another colleague. 2) Architecture representation: A new metrics-driven technique was created to reconstruct software architecture in a just-in-time fashion. This technique was validated in a case study. This approach has significantly improved the efficiency of architecture representation in a complex environment. 3) Attribute specific analysis (performance only): A model-driven approach to performance measurement was applied by decoupling framework-specific information from performance testing requirements. This technique was validated on two platforms (J2EE and Web Services) through a number of case studies. This technique leads to the benchmark producing more representative measures of the eventual application. It reduces the complexity behind the load testing suite and framework-specific performance data collecting utilities. 4) Trade-off and sensitivity analysis: A new technique was designed seeking to improve the Analytical Hierarchical Process (AHP) for trade-off and sensitivity analysis during a framework selection process. This approach was validated in a case study using data from a commercial project. The approach can identify 1) trade-offs implied by an architecture alternative, along with the magnitude of these trade-offs. 2) the most critical decisions in the overall decision process 3) the sensitivity of the final decision and its capability for handling quality attribute priority changes.
APA, Harvard, Vancouver, ISO, and other styles
3

Dimitrov, Martin. "Architectural support for improving system hardware/software reliability." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4533.

Full text
Abstract:
It is a great challenge to build reliable computer systems with unreliable hardware and buggy software. On one hand, software bugs account for as much as 40% of system failures and incur high cost, an estimate of $59.5B a year, on the US economy. On the other hand, under the current trends of technology scaling, transient faults (also known as soft errors) in the underlying hardware are predicted to grow at least in proportion to the number of devices being integrated, which further exacerbates the problem of system reliability. We propose several methods to improve system reliability both in terms of detecting and correcting soft-errors as well as facilitating software debugging. In our first approach, we detect instruction-level anomalies during program execution. The anomalies can be used to detect and repair soft-errors, or can be reported to the programmer to aid software debugging. In our second approach, we improve anomaly detection for software debugging by detecting different types of anomalies as well as by removing false-positives. While the anomalies reported by our first two methods are helpful in debugging single-threaded programs, they do not address concurrency bugs in multi-threaded programs. In our third approach, we propose a new debugging primitive which exposes the non-deterministic behavior of parallel programs and facilitates the debugging process. Our idea is to generate a time-ordered trace of events such as function calls/returns and memory accesses in different threads. In our experience, exposing the time-ordered event information to the programmer is highly beneficial for reasoning about the root causes of concurrency bugs.
ID: 028916717; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 110-119).
Ph.D.
Doctorate
School of Electrical Engineering and Computer Science
Engineering and Computer Science
APA, Harvard, Vancouver, ISO, and other styles
4

Patel, Krutartha Computer Science &amp Engineering Faculty of Engineering UNSW. "Hardware-software design methods for security and reliability of MPSoCs." Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44854.

Full text
Abstract:
Security of a Multi-Processor System on Chip (MPSoC) is an emerging area of concern in embedded systems. MPSoC security is jeopardized by Code Injection attacks. Code Injection attacks, which are the most common types of software attacks, have plagued single processor systems. Design of MPSoCs must therefore incorporate security as one of the primary objectives. Code Injection attacks exploit vulnerabilities in \trusted" and legacy code. An architecture with a dedicated monitoring processor (MONITOR) is employed to simultaneously supervise the application processors on an MPSoC. The program code in the application processors is divided into basic blocks. The basic blocks in the application processors are statically instrumented with special instructions that allow communication with the MONITOR at runtime. The MONITOR verifies the execution of all the processors at runtime using control flow checks and either a timing or instruction count check. This thesis proposes a monitoring system called SOFTMON, a design methodology called SHIELD, a design flow called LOCS and an architectural framework called CUFFS for detecting Code Injection attacks. SOFTMON, a software monitoring system, uses a software algorithm in the MONITOR. SOFTMON incurs limited area overheads. However, the runtime performance overhead is quite high. SHIELD, an extension to the work in SOFTMON overcomes the limitation of high runtime overhead using a MONITOR that is predominantly hardware based. LOCS uses only one special instruction per basic block compared to two, as was the case in SOFTMON and SHIELD. Additionally, profile information is generated for all the basic blocks in all the application processors for the MPSoC designer to tune the design by increasing or decreasing the frequency of loop basic blocks. CUFFS detects attacks even without application processors communicating to the MONITOR. The SOFTMON, SHIELD and LOCS approaches can only detect attacks if the application processors communicate to the MONITOR. CUFFS relies on the exact number of instructions in basic blocks to determine an attack, rather than time-frame based measures used in SOFTMON, SHIELD and LOCS. The lowest runtime performance overhead was achieved by LOCS (worst case of 37.5%), while the SOFTMON monitoring system had the least amount of area overheads of about 25%. The CUFFS approach employed an active MONITOR and hence detected a greater range of attacks. The CUFFS framework also detects bit flip errors (reliability errors) in the control flow instructions of the application processors on an MPSoC. CUFFS can detect nearly 70% of all bit flip errors in the control flow instructions. Additionally, a modified CUFFS approach is proposed to ensure reliable inter-processor communication on an MPSoC. The modified CUFFS approach uses a hardware based checksum approach for reliable inter-processor communication and incurred a runtime performance overhead of up to 25% and negligible area overheads compared to CUFFS. Thus, the approaches proposed in this thesis equip an MPSoC designer with tools to embed security features during an MPSoC's design phase. Incorporating security measures at the processor design level provides security against software attacks in MPSoCs and incurs manageable runtime, area and code-size overheads.
APA, Harvard, Vancouver, ISO, and other styles
5

de, Silva Lakshitha R. "Towards controlling software architecture erosion through runtime conformance monitoring." Thesis, University of St Andrews, 2014. http://hdl.handle.net/10023/5220.

Full text
Abstract:
The software architecture of a system is often used to guide and constrain its implementation. While the code structure of an initial implementation is likely to conform to its intended architecture, its dynamic properties cannot always be fully checked until deployment. Routine maintenance and changing requirements can also lead to a deployed system deviating from this architecture over time. Dynamic architecture conformance checking plays an important part in ensuring that software architectures and corresponding implementations stay consistent with one another throughout the software lifecycle. However, runtime conformance checking strategies often force changes to the software, demand tight coupling between the monitoring framework and application, impact performance, require manual intervention, and lack flexibility and extensibility, affecting their viability in practice. This thesis presents a dynamic conformance checking framework called PANDArch framework, which aims to address these issues. PANDArch is designed to be automated, pluggable, non-intrusive, performance-centric, extensible and tolerant of incomplete specifications. The thesis describes the concept and design principles behind PANDArch, and its current implementation, which uses an architecture description language to specify architectures and Java as the target language. The framework is evaluated using three open source software products of different types. The results suggest that dynamic architectural conformance checking with the proposed features may be a viable option in practice.
APA, Harvard, Vancouver, ISO, and other styles
6

Brosch, Franz [Verfasser], and R. [Akademischer Betreuer] Reussner. "Integrated Software Architecture-Based Reliability Prediction for IT Systems / Franz Brosch ; Betreuer: R. Reussner." Karlsruhe : KIT-Bibliothek, 2012. http://d-nb.info/1024312801/34.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

König, Johan. "Analyzing Substation Automation System Reliability using Probabilistic Relational Models and Enterprise Architecture." Doctoral thesis, KTH, Industriella informations- och styrsystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145006.

Full text
Abstract:
Modern society is unquestionably heavily reliant on supply of electricity. Hence, the power system is one of the important infrastructures for future growth. However, the power system of today was designed for a stable radial flow of electricity from large power plants to the customers and not for the type of changes it is presently being exposed to, like large scale integration of electric vehicles, wind power plants, residential photovoltaic systems etc. One aspect of power system control particular exposed to these changes is the design of power system control and protection functionality. Problems occur when the flow of electricity changes from a unidirectional radial flow to a bidirectional. Such an implication requires redesign of control and protection functionality as well as introduction of new information and communication technology (ICT). To make matters worse, the closer the interaction between the power system and the ICT systems the more complex the matter becomes from a reliability perspective. This problem is inherently cyber-physical, including everything from system software to power cables and transformers, rather than the traditional reliability concern of only focusing on power system components. The contribution of this thesis is a framework for reliability analysis, utilizing system modeling concepts that supports the industrial engineering issues that follow with the imple-mentation of modern substation automation systems. The framework is based on a Bayesian probabilistic analysis engine represented by Probabilistic Relational Models (PRMs) in com-bination with an Enterprise Architecture (EA) modeling formalism. The gradual development of the framework is demonstrated through a number of application scenarios based on substation automation system configurations. This thesis is a composite thesis consisting of seven papers. Paper 1 presents the framework combining EA, PRMs and Fault Tree Analysis (FTA). Paper 2 adds primary substation equipment as part of the framework. Paper 3 presents a mapping between modeling entities from the EA framework ArchiMate and substation automation system configuration objects from the IEC 61850 standard. Paper 4 introduces object definitions and relations in coherence with EA modeling formalism suitable for the purpose of the analysis framework. Paper 5 describes an extension of the analysis framework by adding logical operators to the probabilistic analysis engine. Paper 6 presents enhanced failure rates for software components by studying failure logs and an application of the framework to a utility substation automation system. Finally, Paper 7 describes the ability to utilize domain standards for coherent modeling of functions and their interrelations and an application of the framework utilizing software-tool support.

QC 20140505

APA, Harvard, Vancouver, ISO, and other styles
8

Hassan, Ahmed. "Mining Software Repositories to Assist Developers and Support Managers." Thesis, University of Waterloo, 2004. http://hdl.handle.net/10012/1017.

Full text
Abstract:
This thesis explores mining the evolutionary history of a software system to support software developers and managers in their endeavors to build and maintain complex software systems. We introduce the idea of evolutionary extractors which are specialized extractors that can recover the history of software projects from software repositories, such as source control systems. The challenges faced in building C-REX, an evolutionary extractor for the C programming language, are discussed. We examine the use of source control systems in industry and the quality of the recovered C-REX data through a survey of several software practitioners. Using the data recovered by C-REX, we develop several approaches and techniques to assist developers and managers in their activities. We propose Source Sticky Notes to assist developers in understanding legacy software systems by attaching historical information to the dependency graph. We present the Development Replay approach to estimate the benefits of adopting new software maintenance tools by reenacting the development history. We propose the Top Ten List which assists managers in allocating testing resources to the subsystems that are most susceptible to have faults. To assist managers in improving the quality of their projects, we present a complexity metric which quantifies the complexity of the changes to the code instead of quantifying the complexity of the source code itself. All presented approaches are validated empirically using data from several large open source systems. The presented work highlights the benefits of transforming software repositories from static record keeping repositories to active repositories used by researchers to gain empirically based understanding of software development, and by software practitioners to predict, plan and understand various aspects of their project.
APA, Harvard, Vancouver, ISO, and other styles
9

Doudalis, Ioannis. "Hardware assisted memory checkpointing and applications in debugging and reliability." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42700.

Full text
Abstract:
The problems of software debugging and system reliability/availability are among the most challenging problems the computing industry is facing today, with direct impact on the development and operating costs of computing systems. A promising debugging technique that assists programmers identify and fix the causes of software bugs a lot more efficiently is bidirectional debugging, which enables the user to execute the program in "reverse", and a typical method used to recover a system after a fault is backwards error recovery, which restores the system to the last error-free state. Both reverse execution and backwards error recovery are enabled by creating memory checkpoints, which are used to restore the program/system to a prior point in time and re-execute until the point of interest. The checkpointing frequency is the primary factor that affects both the latency of reverse execution and the recovery time of the system; more frequent checkpoints reduce the necessary re-execution time. Frequent creation of checkpoints poses performance challenges, because of the increased number of memory reads and writes necessary for copying the modified system/program memory, and also because of software interventions, additional synchronization and I/O, etc., needed for creating a checkpoint. In this thesis I examine a number of different hardware accelerators, whose role is to create frequent memory checkpoints in the background, at minimal performance overheads. For the purpose of reverse execution, I propose the HARE and Euripus hardware checkpoint accelerators. HARE and Euripus create different types of checkpoints, and employ different methods for keeping track of the modified memory. As a result, HARE and Euripus have different hardware costs and provide different functionality which directly affects the latency of reverse execution. For improving the availability of the system, I propose the Kyma hardware accelerator. Kyma enables simultaneous creation of checkpoints at different frequencies, which allows the system to recover from multiple types of errors and tolerate variable error-detection latencies. The Kyma and Euripus hardware engines have similar architectures, but the functionality of the Kyma engine is optimized for further reducing the performance overheads and improving the reliability of the system. The functionality of the Kyma and Euripus engines can be combined into a unified accelerator that can serve the needs of both bidirectional debugging and system recovery.
APA, Harvard, Vancouver, ISO, and other styles
10

Mori, Fernando Maruyama. "Uma metodologia de desenvolvimento de diagnóstico guiado para veículos automotivos." Universidade Tecnológica Federal do Paraná, 2014. http://repositorio.utfpr.edu.br/jspui/handle/1/981.

Full text
Abstract:
A utilização de ferramentas externas de diagnóstico guiado tem se tornado cada vez mais importante nas atividades de pós-venda da indústria automotiva. Isso se dá principalmente devido ao uso extensivo de sistemas embarcados nos veículos, tornando-os mais complexos e difíceis de diagnosticar. Atualmente, as técnicas empregadas para o desenvolvimento da ferramenta de diagnóstico guiado são fortemente dependentes da experiência do projetista e centralizadas nas peças e subsistemas do veículo, possibilitando baixo grau de flexibilidade e reaproveitamento da informação. Este trabalho propõe uma nova metodologia para o desenvolvimento da ferramenta de diagnóstico guiado, aplicado a um estudo de caso da indústria automotiva, numa arquitetura de software em três camadas: peças e componentes do veículo, informações e estratégia para o diagnóstico e uma camada de apresentação. Isso permite grande flexibilidade no projeto da ferramenta de diagnóstico guiado para diferentes modelos de veículos, fabricantes de peças e sistemas automotivos. A metodologia proposta é aplicada em um estudo de caso de diagnóstico da Volvo caminhões, mostrando o processo de adaptação da arquitetura de software de três camadas à metodologia proposta e seu impacto no custo do desenvolvimento da ferramenta de diagnóstico.
External guided diagnostic tools are increasingly important to the aftermarket business of automotive industry. It occurs mainly due to the extensive using of embedded systems in vehicles, making them more complex and difficult to diagnose. Currently, the techniques used to develop a guided diagnostic tool are strongly dependent on designer’s experience and are usually focused on parts and vehicle’s subsystems, allowing low flexibility and reduced information reusage. This paper proposes a new methodology for development of a guided diagnostic tool applied to the automotive industry. This methodology is based on a three-tier software architecture composed of vehicle’s parts and components, diagnostic information and strategy, and presentation layer. It allows great flexibility for designing a guided diagnostic tool for different vehicle models, parts OEMs and automotive systems. The proposed methodology has been applied to a case study at Volvo Trucks. The corresponding adaptation process to the three-tier software architecture is presented as well as its impact on development costs.
5000
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Software architecture – Reliability"

1

Semegn, Assefa D. Software architecture and design for reliability and predictability. Newcastle upon Tyne: Cambridge Scholars, 2012.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Shimeall, Tomothy J. An empirical comparison of software fault tolerance and fault elimination. Monterey, California: Naval Postgraduate School, 1989.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Christine, Hofmeister, Crnkovic Ivica, and Reussner Ralf, eds. Quality of software architectures: Second International Conference on Quality of Software Architectures, QoSA 2006, Västeraas, Sweden, June 27-29, 2006 : revised papers. Berlin: Springer, 2006.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

International Conference on the Quality of Software Architectures (6th 2010 Prague, Czech Republic). Research into practice - reality and gaps: 6th International Conference on the Quality of Software Architectures, QoSA 2010, Prague, Czech Republic, June 23-25, 2010 ; proceedings. Berlin: Springer, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

David, Hutchison. Architectures for Adaptive Software Systems: 5th International Conference on the Quality of Software Architectures, QoSA 2009, East Stroudsburg, PA, USA, June 24-26, 2009 Proceedings. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

David, Hutchison. Quality of Software Architectures. Models and Architectures: 4th International Conference on the Quality of Software-Architectures, QoSA 2008, Karlsruhe, Germany, October 14-17, 2008. Proceedings. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Hess, Claudia. Trust-based recommendations in multi-layer networks. Berlin: Aka, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

1961-, Lemos Rogério de, Gacek Cristina 1964-, and Romanovsky Alexander 1954-, eds. Architecting dependable systems IV. Berlin: Springer, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Yuan-Shum, Dai, and Poh Kim-Leng, eds. Computing systems reliability: Models and analysis. New York: Kluwer Academic/Plenum Publishers, 2004.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

1971-, Ho Pin-Han, ed. Optical networks: Architecture and survivability. Boston: Kluwer Academic, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Software architecture – Reliability"

1

Cortellessa, Vittorio, Fabrizio Marinelli, and Pasqualina Potena. "Automated Selection of Software Components Based on Cost/Reliability Tradeoff." In Software Architecture, 66–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11966104_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Gusmanov, Kamill. "CNN LSTM Network Architecture for Modeling Software Reliability." In Software Technology: Methods and Tools, 210–17. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-29852-4_17.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Immonen, Anne. "A Method for Predicting Reliability and Availability at the Architecture Level." In Software Product Lines, 373–422. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/978-3-540-33253-4_10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Tol, Ronald M., and Wolfgang A. Halang. "ARTIE: A Proven Correct Architecture for Safety-Critical Applications." In Safety and Reliability of Software Based Systems, 452–60. London: Springer London, 1997. http://dx.doi.org/10.1007/978-1-4471-0921-1_28.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Park, Doo-soon, and Seokhoon Kim. "Design of Software Reliability Test Architecture for the Connected Car." In Advances in Computer Science and Ubiquitous Computing, 366–70. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3023-9_56.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Fox, John, Subrata Das, David Elsdon, and Peter Hammond. "Decision Making and Planning by Autonomous Agents; A Generic Architecture for Safety-Critical Applications." In Safety and Reliability of Software Based Systems, 122–34. London: Springer London, 1997. http://dx.doi.org/10.1007/978-1-4471-0921-1_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Alam, Irina, Lara Dolecek, and Puneet Gupta. "Lightweight Software-Defined Error Correction for Memories." In Dependable Embedded Systems, 207–32. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_9.

Full text
Abstract:
AbstractReliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.
APA, Harvard, Vancouver, ISO, and other styles
8

Kriebel, Florian, Faiq Khalid, Bharath Srinivas Prabakaran, Semeen Rehman, and Muhammad Shafique. "Fault-Tolerant Computing with Heterogeneous Hardening Modes." In Dependable Embedded Systems, 161–80. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_7.

Full text
Abstract:
AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).
APA, Harvard, Vancouver, ISO, and other styles
9

Wang, Zhuoyue, Zhiqiang Wang, Jinyang Zhao, and Yaping Chi. "PCCP: A Private Container Cloud Platform Supporting Domestic Hardware and Software." In Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications, 399–407. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2456-9_41.

Full text
Abstract:
AbstractWith the widespread use of container cloud, the security issue is becoming more and more critical. While dealing with common security threats in cloud platforms and traditional data centres, there are some new security issues and challenges in the container cloud platform. For example, there are significant challenges in network isolation and resource management. This paper proposes a private container cloud platform PCCP based on Docker supporting domestic software and hardware to solve these security problems. This paper introduces the system architecture and functional architecture of the platform. The system has been tested and confirmed to have high availability and high reliability. The platform gives full play to the value of domestic software and hardware and is better able to serve the information construction of our country.
APA, Harvard, Vancouver, ISO, and other styles
10

Sozer, Hasan, Bedir Tekinerdogan, and Mehmet Aksit. "Extending Failure Modes and Effects Analysis Approach for Reliability Analysis at the Software Architecture Design Level." In Architecting Dependable Systems IV, 409–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-74035-3_18.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Software architecture – Reliability"

1

Ramachandrany, Pradeep, Sarita V. Adve, Pradip Bose, and Jude A. Rivers. "Metrics for Architecture-Level Lifetime Reliability Analysis." In Software (ISPASS). IEEE, 2008. http://dx.doi.org/10.1109/ispass.2008.4510752.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Gokhale, Swapna S., and Veena B. Mendiratta. "Architecture-Based Assessment of Software Reliability." In 2008 Eighth International Conference on Quality Software (QSIC). IEEE, 2008. http://dx.doi.org/10.1109/qsic.2008.57.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Wang, Jun, Weiru Chen, and Jun Liu. "A Modeling of Software Architecture Reliability." In 2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007). IEEE, 2007. http://dx.doi.org/10.1109/npc.2007.17.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Shahmohammadi, Gholamreza. "Reliability Evaluation of Software Architecture Styles." In Sixth International conference on Computer Science and Information Technology. Academy & Industry Research Collaboration Center (AIRCC), 2016. http://dx.doi.org/10.5121/csit.2016.60111.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Wang, Jun, Weiru Chen, and Jun Liu. "A Modeling of Software Architecture Reliability." In 2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007). IEEE, 2007. http://dx.doi.org/10.1109/icnpcw.2007.4351614.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Franco, J. M., R. Barbosa, and M. Zenha-Rela. "Reliability Analysis of Software Architecture Evolution." In 2013 Sixth Latin-American Symposium on Dependable Computing (LADC). IEEE, 2013. http://dx.doi.org/10.1109/ladc.2013.16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Grunske, Lars. "Session details: Reliability." In Comparch '11: Federated Events on Component-Based Software Engineering and Software Architecture. New York, NY, USA: ACM, 2011. http://dx.doi.org/10.1145/3244773.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Franco, Joao M., Raul Barbosa, and M'rio Zenha-Rela. "Automated Reliability Prediction from Formal Architectural Descriptions." In 2012 Joint Working IEEE/IFIP Conference on Software Architecture (WICSA) & European Conference on Software Architecture (ECSA). IEEE, 2012. http://dx.doi.org/10.1109/wicsa-ecsa.212.50.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Zeshan, Furkh, and Radziah Mohamad. "Software architecture reliability prediction models: An overview." In 2011 5th Malaysian Conference in Software Engineering (MySEC). IEEE, 2011. http://dx.doi.org/10.1109/mysec.2011.6140654.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wang, Jun, and Weiru Chen. "Reliability evaluation system based on software architecture." In 2010 2nd International Conference on Future Computer and Communication. IEEE, 2010. http://dx.doi.org/10.1109/icfcc.2010.5497377.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Software architecture – Reliability' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography