Relevant bibliographies by topics / Software and hardware protection methods

Academic literature on the topic 'Software and hardware protection methods'

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Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "Software and hardware protection methods"

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He, Gao Ming. "Research on Protection Methods of Embedded Operating System Software Based on Hardware Compiler." Applied Mechanics and Materials 443 (October 2013): 556–60. http://dx.doi.org/10.4028/www.scientific.net/amm.443.556.

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This paper describes a system; CODESSEAL can provide protection and evaluation to system software. CODESSEAL was designed to protect embedded systems with sufficient expertise and resources to capture attack equipment and manipulator, not only to protect software but also to protect hardware. By using the reconfigurable hardware allows CODESSEAL to provide confidentiality, integrity of security services and a platform-independent program flow without having to redesign the processor. System uses software and data protection technology and designs cycle simulation methods for data analysis. Experimental results show that the protected instructions and data with a high level of safety can be realized a low, which in most cases the performance loss can be reduced to below 10%, so the research of software protection methods of the embedded operating system of hardware compiler has important practical significance.
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Mamarajabov Odil Elmurzayevich. "Cloud technology to ensure the protection of fundamental methods and use of information." International Journal on Integrated Education 3, no. 10 (October 30, 2020): 313–15. http://dx.doi.org/10.31149/ijie.v3i10.780.

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A comparative analysis of attacks carried out in cloud technologies, the main methods and methods of information protection, the possibilities of using hardware and software, and methods to combat threats when eliminating them, ensuring data protection were carried out
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Sidhu, Simranjeet, Bassam J. Mohd, and Thaier Hayajneh. "Hardware Security in IoT Devices with Emphasis on Hardware Trojans." Journal of Sensor and Actuator Networks 8, no. 3 (August 10, 2019): 42. http://dx.doi.org/10.3390/jsan8030042.

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Security of IoT devices is getting a lot of attention from researchers as they are becoming prevalent everywhere. However, implementation of hardware security in these devices has been overlooked, and many researches have mainly focused on software, network, and cloud security. A deeper understanding of hardware Trojans (HTs) and protection against them is of utmost importance right now as they are the prime threat to the hardware. This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate enough. These devices must be protected against sophisticated attacks, especially if the groundwork for the attacks is already laid in devices during design or manufacturing process, such as with HTs. This paper will discuss the stealthy nature of these HT, highlight HT taxonomy and insertion methods, and provide countermeasures.
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Bawane, Manjiri R., Madhavi S. Borkar, Payal R. Wawarkar, Sanika M. Shende, Heena K. Chandel, and Ketki R. Bhakare. "USB Key Based Antipiracy Solution." Journal of Advance Research in Computer Science & Engineering (ISSN: 2456-3552) 2, no. 2 (February 28, 2015): 12–17. http://dx.doi.org/10.53555/nncse.v2i2.507.

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USBkey is a new kind of intelligent security product that comprises microprocessor and operation system. Computer software is intellectual property, and is protected by copyright law. This paper proposes a software protection method that utilizes efficient calculation ability and security space of USB key in environment, which combines protection methods, identity authentication and trusted computing technology. In this project we proposed to develop a hardware based solution to prevent software piracy. A hardware based system consist of physical device and hence cannot be shared over the internet and hence eliminates the flaws of conventional mechanisms discussed above.
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Borovikov, Aleksey, Oleg Maslov, Stepan Mordvinov, and Andrei Esafiev. "Increasing Hardware-Software Platforms Trust Levels to Prevent Exploiting BIOS Vulnerabilities." Voprosy kiberbezopasnosti, no. 6(46) (2021): 68–77. http://dx.doi.org/10.21681/2311-3456-2021-6-68-77.

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Abstract: in this publicaton, a technique to increase trust levels of foreign and domestic-made hardware-software platforms, which are used to create specialised devices and computing facilities, which are meeting safety requirements and protected from BIOS vulnerabilities, to work with classified information, was made. Problems, which developer might encounter, were listed; methods of troubleshooting were proposed, and conclusions were made. The purpose of research is to investigate an ability of designing trusted foreign and domestic-made hardwaresoftware platforms, protected from exploiting BIOS vulnerabilities. Research methods: in order to achieve the purpose of research, an analysis of Russian’s industrial-grade PC modules was made in order to choose PC module that will be used for designing trusted hardware-software platform, an analysis of known BIOS vulnerabilities was made; proprietary BIOS replacement in a form of domestic-made Horizon bootloader, which includes unauthorised access to information protection measures, was made and possibilty of practical use of trusted hardware-software platform with Horizon bootloader was overviewed. Obtained result: PC module for trusted hardware-software platform was selected, proprietary BIOS replacement in a form of domestic-made Horizon bootloader, which includes unauthorized access to information protection measures, was made; technique to increase trust levels of foreign and domestic-made hardware-software platforms, which are used to create specialized devices and computing facilities, which are meeting safety requirements and protected from BIOS vulnerabilities, to work with classified information, was made; an approach to create trusted hardware-software platform design requirements and conditions was made; needs to exclude potentially dangerous Intel Management Engine controller’s functionality were justified and proposal to use trusted hardware-software platform with Horizon bootloader was made.
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Alekseev, V. V., V. A. Gridnev, A. V. Yakovlev, O. S. Mashkova, U. A. Savilova, D. A. Shibkov, and D. A. Yakovleva. "A System Approach to the Construction of the Software and Hardware Complex for Training Information Security Specialists." Vestnik Tambovskogo gosudarstvennogo tehnicheskogo universiteta 27, no. 1 (2021): 020–30. http://dx.doi.org/10.17277/vestnik.2021.01.pp.020-030.

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In order to train specialists in information security (IS), a software and hardware complex “Means of protecting information from leakage through technical channels” has been developed; it provides an opportunity to study the process of information leakage through technical channels and methods of its protection, as well as apply various modules and additional software (software) that clearly demonstrate the features of various methods of information security. The composition of this complex is shown: laboratory stands simulating acoustic, vibroacoustic, acoustoelectric channels and a channel of side electromagnetic radiation and interference. At each of the stands there are information security means (ISMs) that prevent the leakage of confidential information through the corresponding technical channel. To adjust the ISMs for acoustic and vibroacoustic channels, the ISIDORA software has been developed; it allows adjusting the level of the generated acoustic interference to meet the requirements of the security of the room and at the same time to have a comfortable conversation in this room.
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Lobyzov, Viktor, and Vadim Shevtsov. "The concept of a Hardware-Software System for Protecting IIoT Devices." NBI Technologies, no. 2 (October 2021): 16–21. http://dx.doi.org/10.15688/nbit.jvolsu.2021.2.3.

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The Internet of Things is a new trend in the development of information technologies, actively spreading as interconnected functional nodes that by default have the means to ensure interaction directly with each other, or with the external environment. The development of such networks is a phenomenon that can radically change the world economy, as well as social processes. As a result of the application of this layer of information technologies, the need for direct human control over actions and operations will be eliminated. One of the most common household examples is a “smart home” – a computer network of interconnected devices using various data transfer protocols with the ability to access this network from an external network. So, thanks to IoT, it is possible to configure devices in the house by remote access. The paper deals with the main security methods against attacks and threats of IIoT devices. The information infrastructure was analyzed, an idea of the architecture of IIoT systems was obtained, and the information transmission path was identified. An analysis of the IIoT regulatory framework governing security, architecture and data exchange in IIoT systems has been carried out, documents governing the Industrial Internet of Things have been identified. The best communication protocol has been identified. Subsequently, the threats of the protocol were selected, and possible means and methods of protection were identified. For IIoT gateways, the concept of a hardware-software complex was presented as a prototype, and a comparison was made with existing solutions.
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Wu, Zongbo, Wenhui Xiao, Han Deng, and Lan Yang. "Research on data privacy protection methods based on genome-wide association study." International Journal of Embedded Systems 15, no. 1 (2022): 1. http://dx.doi.org/10.1504/ijes.2022.122105.

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Deng, Han, Lan Yang, Zongbo Wu, and Wenhui Xiao. "Research on data privacy protection methods based on genome-wide association study." International Journal of Embedded Systems 15, no. 1 (2022): 1. http://dx.doi.org/10.1504/ijes.2022.10046007.

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Tian, Hong Lei, Jian Feng Liu, Yong Kuan Liu, Yuan Fang, Wen Huai Chen, and Liang Gao. "The Research on Relay Protection Settings On-Line Verification System Application in Smart Grid." Advanced Materials Research 1070-1072 (December 2014): 1378–83. http://dx.doi.org/10.4028/www.scientific.net/amr.1070-1072.1378.

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The intelligrid-oriented on-line relay settings verification system based on EMS real-time data are discussed, with related software system designed and fulfilled. Firstly, the research background and current situation of on-line relay settings verification system are summarized. Secondly, the on-line relay settings verification system's general principle, hardware and software design are mainly discussed. And this paper shows the designed hardware structure diagram, the software structure diagram. And the flowchart of main procedure is given. Thirdly, the methods of dealing with EMS real-time data of the on-line verification system are discussed in detail. The verifying principles of sensitivity & selectivity of relay protection are given definitely. It is able to simulate two simultaneous faults, faults in network oscillation, and faults during auto-reclosing. It checks reliability & sensitivity of relay settings under these circumstances. Finally, considering substation-area and wide-area relay protections, this paper points out some key problems of on-line relay settings verification system to be resolved, and its application prospect.
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Dissertations / Theses on the topic "Software and hardware protection methods"

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Рой, Юлія Володимирівна. "Дослідження особливостей створення захищеної персональної інформаційної мережі житлового будинку." Master's thesis, КПІ ім. Ігоря Сікорського, 2020. https://ela.kpi.ua/handle/123456789/38563.

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Актуальність дослідження. У сучасному світі активно розвиваються мережеві та інформаційні технології. Зараз неможливо в рамках міста знайти будівлю, де б не були розгорнуті підключення до мережі передачі даних на основі технологій Інтернету. Така мережа спрощує і оптимізує велику кількість задач, таких як обмін інформацією, робота над документами, користування програмами, обмін ресурсами та інформацією тощо. В якості такої будівлі доцільно розглянути житловий будинок на визначену кількість квартир. Інформація – це дуже цінний ресурс, тому зловмисники досить часто намагаються отримати доступ до мереж як корпоративних, так і домашніх. Основною причиною впровадження мережевої безпеки є захист мережі та системних ресурсів, підключених до мережі. Інформація в будь-якій формі вважається цінною властивістю мережі, і її втрата чи доступ до неї може коштувати грошей або в гіршому випадку, спричинить катастрофу. Зламування мережі може призвести до різних наслідків: перехоплення даних, зараження шкідливим ПЗ та знищенням усієї інформації. Мета дослідження полягає в пошуку можливостей захисту персональної інформаційної мережі житлового будинку програмно-апаратним комплексом. Завдання для досягнення мети: проаналізувати особливості проектування захищеної персональної інформаційної мережі, зробити огляд мережевої безпеки(можливі вразливості, загрози та атаки), оцінити методи аналізу загроз та відповідно дослідити можливості рішення щодо усування потенційних загроз мережі. Об’єкт дослідження: захищена персональна інформаційна мережа житлового будинку. Предмет дослідження: програмні та програмно апаратні методи захисту персональної інформаційної мережі. Методи дослідження: алгоритми та методи, які визначені в основі функціонування систем та технологій в рамках захищеної локальної мережі, технології та алгоритми методів захисту локальних мереж. Наукова новизна отриманих результатів: 1) запропоновані варіанти створення захищеної персональної інформаційної мережі; 2) запропоновано послідовний алгоритм налаштування програмних методів захисту персональної мережі. Практичне значення одержаних результатів: результати роботи можуть бути використанні при проектуванні домашніх мереж та «будинкових» мереж багатоквартирних будинків.
Relevance of research. In the modern world, network and information technologies are actively developing. At present, it is impossible to find a building within the city where connections to the data network based on Internet technologies have not been deployed. This network simplifies and optimizes many tasks, such as information exchange, working on documents, using programs, exchanging resources and information, and more. As such a building, it is advisable to consider a residential building for a certain number of apartments. Information is a very valuable resource, so attackers often try to access both corporate and home networks. The main reason for implementing network security is to protect the network and system resources connected to the network. Information in any form is considered a valuable property of the network, and its loss or access to it can cost money or, in the worst case, cause a catastrophe. Hacking a network can lead to various consequences: data interception, malware infection and destruction of all information. Therefore, it is important to pay attention to network protection, search for vulnerabilities and identify potential threats that could harm the current system and resources. The purpose of the study is to find opportunities to protect the personal information network of a residential building software and hardware. Objectives to achieve the goal: to analyze the features of designing a secure personal information network, to review network security (possible vulnerabilities, threats and attacks), to evaluate methods of threat analysis and, accordingly, to explore the possibility of solving potential threats to the network. Object of study: protected personal information network of a residential building. Subject of study: software and hardware methods of personal information network protection. Research methods algorithms and methods that are defined in the basis of the functioning of systems and technologies within a secure local area network, technologies and algorithms of local area network protection methods. Scientific novelty of the obtained results: 1) proposed options for creating a secure personal information network; 2) a sequential algorithm for configuring software methods for personal network protection is proposed. The practical implications of the findings: the results of the work can be used in the design of home networks and "home" networks of apartment buildings.
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Mendoza, Jose Antonio Kougianos Elias. "Hardware & software codesign of a JPEG200 watermarking encoder." [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-9752.

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Volynkin, Alexander S. "Advanced methods for detection of malicious software." Diss., Online access via UMI:, 2007.

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Aravalli, SaiKrishna. "Some Novice methods for Software Protection with Obfuscation." ScholarWorks@UNO, 2006. http://scholarworks.uno.edu/td/479.

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Previously software is distributed to the users by using devices like CD.S and floppies and in the form of bytes. Due to the high usage of internet and in order to perform the tasks rapidly without wasting time on depending physical devices, software is supplied through internet in the form of source code itself. Since source code is available to the end users there is a possibility of changing the source code by malicious users in order to gain their personnel benefits which automatically leads to malfunctioning of the software. The method proposed in this thesis is based on the concept of using hardware to protect the software. We will obfuscate the relation between variables and statements in the software programs so that the attacker can not find the direct relation between them. The method combines software security with code obfuscation techniques, uses the concepts of cryptography like hashing functions and random number generators.
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Patel, Krutartha Computer Science &amp Engineering Faculty of Engineering UNSW. "Hardware-software design methods for security and reliability of MPSoCs." Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44854.

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Security of a Multi-Processor System on Chip (MPSoC) is an emerging area of concern in embedded systems. MPSoC security is jeopardized by Code Injection attacks. Code Injection attacks, which are the most common types of software attacks, have plagued single processor systems. Design of MPSoCs must therefore incorporate security as one of the primary objectives. Code Injection attacks exploit vulnerabilities in \trusted" and legacy code. An architecture with a dedicated monitoring processor (MONITOR) is employed to simultaneously supervise the application processors on an MPSoC. The program code in the application processors is divided into basic blocks. The basic blocks in the application processors are statically instrumented with special instructions that allow communication with the MONITOR at runtime. The MONITOR verifies the execution of all the processors at runtime using control flow checks and either a timing or instruction count check. This thesis proposes a monitoring system called SOFTMON, a design methodology called SHIELD, a design flow called LOCS and an architectural framework called CUFFS for detecting Code Injection attacks. SOFTMON, a software monitoring system, uses a software algorithm in the MONITOR. SOFTMON incurs limited area overheads. However, the runtime performance overhead is quite high. SHIELD, an extension to the work in SOFTMON overcomes the limitation of high runtime overhead using a MONITOR that is predominantly hardware based. LOCS uses only one special instruction per basic block compared to two, as was the case in SOFTMON and SHIELD. Additionally, profile information is generated for all the basic blocks in all the application processors for the MPSoC designer to tune the design by increasing or decreasing the frequency of loop basic blocks. CUFFS detects attacks even without application processors communicating to the MONITOR. The SOFTMON, SHIELD and LOCS approaches can only detect attacks if the application processors communicate to the MONITOR. CUFFS relies on the exact number of instructions in basic blocks to determine an attack, rather than time-frame based measures used in SOFTMON, SHIELD and LOCS. The lowest runtime performance overhead was achieved by LOCS (worst case of 37.5%), while the SOFTMON monitoring system had the least amount of area overheads of about 25%. The CUFFS approach employed an active MONITOR and hence detected a greater range of attacks. The CUFFS framework also detects bit flip errors (reliability errors) in the control flow instructions of the application processors on an MPSoC. CUFFS can detect nearly 70% of all bit flip errors in the control flow instructions. Additionally, a modified CUFFS approach is proposed to ensure reliable inter-processor communication on an MPSoC. The modified CUFFS approach uses a hardware based checksum approach for reliable inter-processor communication and incurred a runtime performance overhead of up to 25% and negligible area overheads compared to CUFFS. Thus, the approaches proposed in this thesis equip an MPSoC designer with tools to embed security features during an MPSoC's design phase. Incorporating security measures at the processor design level provides security against software attacks in MPSoCs and incurs manageable runtime, area and code-size overheads.
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Mendoza, Jose Antonio. "Hardware and Software Codesign of a JPEG2000 Watermarking Encoder." Thesis, University of North Texas, 2008. https://digital.library.unt.edu/ark:/67531/metadc9752/.

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Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration.
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Lei, Li. "Hardware/Software Interface Assurance with Conformance Checking." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2323.

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Hardware/Software (HW/SW) interfaces are pervasive in modern computer systems. Most of HW/SW interfaces are implemented by devices and their device drivers. Unfortunately, HW/SW interfaces are unreliable and insecure due to their intrinsic complexity and error-prone nature. Moreover, assuring HW/SW interface reliability and security is challenging. First, at the post-silicon validation stage, HW/SW integration validation is largely an ad-hoc and time-consuming process. Second, at the system deployment stage, transient hardware failures and malicious attacks make HW/SW interfaces vulnerable even after intensive testing and validation. In this dissertation, we present a comprehensive solution for HW/SW interface assurance over the system life cycle. This solution is composited of two major parts. First, our solution provides a systematic HW/SW co-validation framework which validates hardware and software together; Second, based on the co-validation framework, we design two schemes for assuring HW/SW interfaces over the system life cycle: (1) post-silicon HW/SW co-validation at the post-silicon validation stage; (2) HW/SW co-monitoring at the system deployment stage. Our HW/SW co-validation framework employs a key technique, conformance checking which checks the interface conformance between the device and its reference model. Furthermore, property checking is carried out to verify system properties over the interactions between the reference model and the driver. Based on the conformance between the reference model and the device, properties hold on the reference model/driver interface also hold on the device/driver interface. Conformance checking discovers inconsistencies between the device and its reference model thereby validating device interface implementations of both sides. Property checking detects both device and driver violations of HW/SW interface protocols. By detecting device and driver errors, our co-validation approach provides a systematic and ecient way to validate HW/SW interfaces. We developed two software tools which implement the two assurance schemes: DCC (Device Conformance Checker), a co-validation framework for post-silicon HW/SW integration validation; and CoMon (HW/SW Co-monitoring), a runtime verication framework for detecting bugs and malicious attacks across HW/SW interfaces. The two software tools lead to discovery of 42 bugs from four industry hardware devices, the device drivers, and their reference models. The results have demonstrated the signicance of our approach in HW/SW interface assurance of industry applications.
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Zhang, Zhao. "Software and hardware methods for memory access latency reduction on ILP processors." W&M ScholarWorks, 2002. https://scholarworks.wm.edu/etd/1539623407.

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While microprocessors have doubled their speed every 18 months, performance improvement of memory systems has continued to lag behind. to address the speed gap between CPU and memory, a standard multi-level caching organization has been built for fast data accesses before the data have to be accessed in DRAM core. The existence of these caches in a computer system, such as L1, L2, L3, and DRAM row buffers, does not mean that data locality will be automatically exploited. The effective use of the memory hierarchy mainly depends on how data are allocated and how memory accesses are scheduled. In this dissertation, we propose several novel software and hardware techniques to effectively exploit the data locality and to significantly reduce memory access latency.;We first presented a case study at the application level that reconstructs memory-intensive programs by utilizing program-specific knowledge. The problem of bit-reversals, a set of data reordering operations extensively used in scientific computing program such as FFT, and an application with a special data access pattern that can cause severe cache conflicts, is identified in this study. We have proposed several software methods, including padding and blocking, to restructure the program to reduce those conflicts. Our methods outperform existing ones on both uniprocessor and multiprocessor systems.;The access latency to DRAM core has become increasingly long relative to CPU speed, causing memory accesses to be an execution bottleneck. In order to reduce the frequency of DRAM core accesses to effectively shorten the overall memory access latency, we have conducted three studies at this level of memory hierarchy. First, motivated by our evaluation of DRAM row buffer's performance roles and our findings of the reasons of its access conflicts, we propose a simple and effective memory interleaving scheme to reduce or even eliminate row buffer conflicts. Second, we propose a fine-grain priority scheduling scheme to reorder the sequence of data accesses on multi-channel memory systems, effectively exploiting the available bus bandwidth and access concurrency. In the final part of the dissertation, we first evaluate the design of cached DRAM and its organization alternatives associated with ILP processors. We then propose a new memory hierarchy integration that uses cached DRAM to construct a very large off-chip cache. We show that this structure outperforms a standard memory system with an off-level L3 cache for memory-intensive applications.;Memory access latency has become a major performance bottleneck for memory-intensive applications. as long as DRAM technology remains its most cost-effective position for making main memory, the memory performance problem will continue to exist. The studies conducted in this dissertation attempt to address this important issue. Our proposed software and hardware schemes are effective and applicable, which can be directly used in real-world memory system designs and implementations. Our studies also provide guidance for application programmers to understand memory performance implications, and for system architects to optimize memory hierarchies.
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Jafri, Nisrine. "Formal fault injection vulnerability detection in binaries : a software process and hardware validation." Thesis, Rennes 1, 2019. http://www.theses.fr/2019REN1S014/document.

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L'injection de faute est une méthode bien connue pour évaluer la robustesse et détecter les vulnérabilités des systèmes. La détection des vulnérabilités créées par injection de fautes a été approchée par différentes méthodes. Dans la littérature deux approches existent: les approches logicielles et les approches matérielles. Les approches logicielles peuvent fournir une large et rapide couverture, mais ne garantissent pas la présence de vulnérabilité dans le système. Les approches matérielles sont incontestables dans leurs résultats, mais nécessitent l’utilisation de matériaux assez coûteux et un savoir-faire approfondi, qui ne permet tout de même pas dans la majorité des cas de confirmer le modèle de faute représentant l'effet créé. Dans un premier lieu, cette thèse se concentre sur l'approche logicielle et propose une approche automatisée qui emploie les techniques de la vérification formelle pour détecter des vulnérabilités créées par injection de faute au niveau binaire. L'efficacité de cette approche est montrée en l'appliquant à des algorithmes de cryptographie implémentés dans les systèmes embarqués. Dans un second lieu, cette thèse établit un rapprochement entre les deux approches logicielles et matérielles sur la détection de vulnérabilité d'injection de faute en comparant les résultats des expériences des deux approches. Ce rapprochement des deux approches démontre que: toutes les vulnérabilités détectées par l'approche logicielle ne peuvent pas être reproduites dans le matériel; les conjectures antérieures sur le modèle de faute par des attaques d'impulsion électromagnétique ne sont pas précises ; et qu’il y a un lien entre les résultats de l’approche logicielle et l'approche matérielle. De plus, la combinaison des deux approches peut rapporter une approche plus précise et plus efficace pour détecter les vulnérabilités qui peuvent être créées par injection de faute
Fault injection is a well known method to test the robustness and security vulnerabilities of systems. Detecting fault injection vulnerabilities has been approached with a variety of different but limited methods. Software-based and hardware-based approaches have both been used to detect fault injection vulnerabilities. Software-based approaches can provide broad and rapid coverage, but may not correlate with genuine hardware vulnerabilities. Hardware-based approaches are indisputable in their results, but rely upon expensive expert knowledge, manual testing, and can not confirm what fault model represent the created effect. First, this thesis focuses on the software-based approach and proposes a general process that uses model checking to detect fault injection vulnerabilities in binaries. The efficacy and scalability of this process is demonstrated by detecting vulnerabilities in different cryptographic real-world implementations. Then, this thesis bridges software-based and hardware-based fault injection vulnerability detection by contrasting results of the two approaches. This demonstrates that: not all software-based vulnerabilities can be reproduced in hardware; prior conjectures on the fault model for electromagnetic pulse attacks may not be accurate; and that there is a relationship between software-based and hardware-based approaches. Further, combining both software-based and hardware-based approaches can yield a vastly more accurate and efficient approach to detect genuine fault injection vulnerabilities
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Varma, Krishnaraj M. "Fast Split Arithmetic Encoder Architectures and Perceptual Coding Methods for Enhanced JPEG2000 Performance." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/26519.

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JPEG2000 is a wavelet transform based image compression and coding standard. It provides superior rate-distortion performance when compared to the previous JPEG standard. In addition JPEG2000 provides four dimensions of scalability-distortion, resolution, spatial, and color. These superior features make JPEG2000 ideal for use in power and bandwidth limited mobile applications like urban search and rescue. Such applications require a fast, low power JPEG2000 encoder to be embedded on the mobile agent. This embedded encoder needs to also provide superior subjective quality to low bitrate images. This research addresses these two aspects of enhancing the performance of JPEG2000 encoders. The JPEG2000 standard includes a perceptual weighting method based on the contrast sensitivity function (CSF). Recent literature shows that perceptual methods based on subband standard deviation are also effective in image compression. This research presents two new perceptual weighting methods that combine information from both the human contrast sensitivity function as well as the standard deviation within a subband or code-block. These two new sets of perceptual weights are compared to the JPEG2000 CSF weights. The results indicate that our new weights performed better than the JPEG2000 CSF weights for high frequency images. Weights based solely on subband standard deviation are shown to perform worse than JPEG2000 CSF weights for all images at all compression ratios. Embedded block coding, EBCOT tier-1, is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT tier-1 hardware implementations has concentrated on cycle efficient context formation. These pass-parallel architectures require that JPEG2000's three mode switches be turned on. While turning on the mode switches allows for arithmetic encoding from each coding pass to run independent of each other (and thus in parallel), it also disrupts the probability estimation engine of the arithmetic encoder, thus sacrificing coding efficiency for improved throughput. In this research a new fast EBCOT tier-1 design is presented: it is called the Split Arithmetic Encoder (SAE) process. The proposed process exploits concurrency to obtain improved throughput while preserving coding efficiency. The SAE process is evaluated using three methods: clock cycle estimation, multithreaded software implementation, a field programmable gate array (FPGA) hardware implementation. All three methods achieve throughput improvement; the hardware implementation exhibits the largest speedup, as expected. A high speed, task-parallel, multithreaded, software architecture for EBCOT tier-1 based on the SAE process is proposed. SAE was implemented in software on two shared-memory architectures: a PC using hyperthreading and a multi-processor non-uniform memory access (NUMA) machine. The implementation adopts appropriate synchronization mechanisms that preserve the algorithm's causality constraints. Tests show that the new architecture is capable of improving throughput as much as 50% on the NUMA machine and as much as 19% on a PC with two virtual processing units. A high speed, multirate, FPGA implementation of the SAE process is also proposed. The mismatch between the rate of production of data by the context formation (CF) module and the rate of consumption of data by the arithmetic encoder (AE) module is studied in detail. Appropriate choices for FIFO sizes and FIFO write and read capabilities are made based on the statistics obtained from test runs of the algorithm. Using a fast CF module, this implementation was able to achieve as much as 120% improvement in throughput.
Ph. D.
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Books on the topic "Software and hardware protection methods"

1

Dedicated digital processors: Methods in hardware/software system design. Chichester, West Sussex, England: John Wiley, 2004.

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Pratt, Terrence W. Methods for design and evaluation of integrated hardware/software sytems for concurrent computation. Charlottesville, VA: Dept. of Computer Science, University of Virginia, 1987.

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Wagstaff, Adam. Health equity and financial protection: Streamlined analysis with ADePT software. Washington, D.C: World Bank, 2011.

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F, Li Hon, Probst D. K, and IFIP WG 10 5, eds. Advances in hardware design and verification: IFIP TC10 WG10.5 International Conference on Correct Hardware and Verification Methods, 16-18 October 1997, Montreal, Canada. London: Chapman & Hall on behalf of the International Federation for Information Processing (IFIP), 1997.

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David, Hutchison. Cryptographic Hardware and Embedded Systems – CHES 2008: 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings. Berlin, Heidelberg: Springer-Verlag Berlin Heidelberg, 2008.

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Schneider, Jochen. Handbuch des EDV-Rechts: Vertragsrecht (Hardware, Software, Wartung, Pflege, Systeme jeweils mit AGB), Gewährleistung, Haftung, Online, Datenschutz, Rechtsschutz. 2nd ed. Köln: O. Schmidt, 1997.

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Advanced Research Working Conference on Correct Hardware Design Methodologies (1993 Arles, France). Correct hardware design and verification methods: IFIP WG10.2 Advanced Research Working Conference, CHARME '93, Arles, Frances [sic], May 24-26, 1993 : proceedings. Berlin: Springer, 1993.

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International School on Formal Methods for the Design of Computer, Communication, and Software Systems (6th 2006 Bertinoro, Italy). Formal methods for hardware verification: 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006 : advanced lectures. Berlin: Springer, 2006.

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Preneel, Bart. Cryptographic Hardware and Embedded Systems – CHES 2011: 13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings. Berlin, Heidelberg: International Association for Cryptologic Research, 2011.

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E-patent strategies for software, e-commerce, the internet, telecom services, financial services, and business methods (with case studies and forecasts). Washington, DC: LBI Institute, 2000.

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Book chapters on the topic "Software and hardware protection methods"

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Penkin, Yu M., G. I. Khara, and A. A. Fedoseeva. "The New Cryptographic Method for Software and Hardware Protection of Communication Channels in Open Environments." In Data-Centric Business and Applications, 589–619. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-43070-2_26.

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Shakya, Bicky, Mark M. Tehranipoor, Swarup Bhunia, and Domenic Forte. "Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation." In Hardware Protection through Obfuscation, 3–32. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49019-9_1.

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Qin, Shengchao, Jifeng He, Zongyan Qiu, and Naixiao Zhang. "Hardware/Software Partitioning in Verilog." In Formal Methods and Software Engineering, 168–79. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36103-0_19.

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Pierre, Laurence. "VHDL: A Hardware Description Language and its Simulation Semantics." In Software Specification Methods, 113–30. London: Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0701-9_7.

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Yu, Zhengqi, Armin Biere, and Keijo Heljanko. "Certifying Hardware Model Checking Results." In Formal Methods and Software Engineering, 498–502. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32409-4_32.

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Oliveira, Marcel, and Jim Woodcock. "Automatic Generation of Verified Concurrent Hardware." In Formal Methods and Software Engineering, 286–306. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-76650-6_17.

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Abdel-Hamid, Amr T., Sofiène Tahar, and John Harrison. "Enabling Hardware Verification through Design Changes." In Formal Methods and Software Engineering, 459–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36103-0_47.

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Belous, Anatoly, and Vitali Saladukha. "Methods of Detecting Hardware Trojans in Microcircuits." In Viruses, Hardware and Software Trojans, 453–502. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-47218-4_5.

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Keerup, Kalmer, Dan Bogdanov, Baldur Kubo, and Per Gunnar Auran. "Privacy-Preserving Analytics, Processing and Data Management." In Big Data in Bioeconomy, 157–68. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-71069-9_12.

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AbstractTypically, data cannot be shared among competing organizations due to confidentiality or regulatory restrictions. We present several technological alternatives to solve the problem: secure multi-party computation (MPC), trusted execution environments (TEE) and multi-key fully homomorphic encryption (MKFHE). We compare these privacy-enhancing technologies from deployment and performance point of view and explain how we selected technology and machine learning methods. We introduce a demonstrator built in the DataBio project for securely combining private and public data for planning of fisheries. The secure machine learning of best catch locations is a web solution utilizing Intel® Software Guard Extensions (Intel® SGX)-based TEE and built with the Sharemind HI (Hardware Isolation) development tools. Knowing where to go fishing is a competitive advantage that a fishery is not interested to share with competitors. Therefore, joint intelligence from public and private sector data while protecting secrets of each contributing organization is an important enabler. Finally, we discuss the wider business impact of secure machine learning in situations where data confidentiality is a concern.
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Belous, Anatoly, and Vitali Saladukha. "Information Weapon: Concepts, Means, Methods, and Examples of Application." In Viruses, Hardware and Software Trojans, 1–99. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-47218-4_1.

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Conference papers on the topic "Software and hardware protection methods"

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Popov, S. O., P. S. Vorona, and M. V. Gushin. "The Method of Creating Diagnostic Stands for Monitoring and Control Tools Using Software and Hardware Modeling." In 2018 International Youth Scientific and Technical Conference Relay Protection and Automation (RPA). IEEE, 2018. http://dx.doi.org/10.1109/rpa.2018.8537200.

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Xiong, Huasheng, Duo Li, and Liangju Zhang. "Test Facility Design for Integrated Digital Nuclear Reactor Protection System." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29286.

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Reactor protection system is one of the most important safety systems in nuclear power plant and shall be designed with very high reliability. Digital computer-based Reactor Protection System (RPS) takes great advantages over its conventional counterpart based on analog technique and faces the issues how to effectively demonstrate and confirm the completeness and correctness of the software that performs reactor safety functions in the same time. It is commonly accepted that the essential way to solve safety software issues in a digital RPS is to pass a strict and independent Verification and Validation (V&V) process, in which integrated RPS testing play an important role to form a part of the overall system validation. Integrated RPS testing must be carried out rigorously before the system is delivered to nuclear power plant. The integrated testing are often combined with the factory acceptance test (FAT) to form a single testing activity, during which the RPS is excited by emulated static and dynamic input signals. The integration testing should simulate normal operation, anticipated operational occurrences and accident conditions, as well as anticipated faults on the inputs to the DRPS such as sensors out of range or ambiguous input readings. All safety function requirements of digital RPS should be confirmed by representative testing. The design and development of a test facility to carry out the integrated RPS testing are covered in this paper, which is merged in the research on a digital RPS engineering prototype for a nuclear power plant. The test facility is based on PXI platform and LabVIEW software development environment and its architecture design also takes into account the test functions future extensions such as hardware upgrades and software modules enhancement. The test facility provides the digital RPS with redundant, synchronized and multi-channel emulated signals that are produced to emulate all protection signals from 1E class sensors and transmitters with time varied value within their possible ranges, which would put integrated RPS testing into practice to confirm the digital RPS has fully met its predefined safety functionality requirements. The designed test facility can provide an independent verification and validation process for the research of digital RPS with scientific methods and authentic data to evaluate the RPS performance thoroughly and effectively, such as measuring threshold precision and trip response time, analyzing system statistical reliability and so on.
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Zhuo, Chen, Zhao Bo, Yang Jian, and Sun Jin-long. "Research on the Reliability of Digital Instrumentation and Control System of Nuclear Power Plant Based on Dynamic Flowgraph Methodology." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-67719.

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With the development of information and computer technology, the Digital Instrumentation and Control (I&C) System has been widely used in nuclear power plants, which leads the tendency of NPPS’ construction and rebuilding on digital I&C system. As an approximate approach, conventional fault tree approach has been used quite often in the analysis of nuclear power plants’ Probability Safety Assessment (PSA), which combine with system components’ failure modes in order to modeling the digital system’s failure. However, for the reason that conventional fault tree approach has a great disadvantage on analyzing the reliability of digital I&C system, which may not be able to fully describe the dynamic behavior of digital I&C system with significant hardware/software/human action process interaction, multi-failure modes and logic loops, it cannot carry on effective modeling and evaluation of digital I&C system. Therefore it is necessary to establish some dynamic approaches to modeling digital I&C system. As a new probability safety analysis method, Dynamic Flowgraph Methodology (DFM) can model the relationship between time sequence and system variables because of its dynamic property. Therefore, DFM can be used to analyze the impact of software failure, hardware failure and external environment, which are closely related to the reliability of the whole system. In the first place, this paper introduces the theoretical basis, model elements and the modeling procedures of DFM and demonstrates how Dynamic Flowgraph Methodology (DFM) can be applied to Reactor Protection System with interactions between hardware/software and physical properties of a controlled process. Meanwhile, in this case, DFM and fault tree methodologies are both used to conduct the PSA for the same top event by calculating the probability of it and finding out the prime implicants of DFM and minimal cutsets of conventional fault tree. During the process of analysis, we mainly evaluate the reliability of reactor trip function of Reactor Protection System (RPS) by using DFM and conventional fault tree approach and mainly focus on modeling the four-way-redundant voting logic and the reactor trip breaker logic. Finally, through the comparison of this two methods and model results, it is concluded that there is a distinct advantage of DFM over conventional fault tree approach by using multi-logic to fully display the fault mode and utilizing decision table to describe the interaction between software and hardware. In general, conclusion can be drawn that, as a dynamic approach, Dynamic Flowgraph Methodology could be more accuracy and effective than conventional fault tree approach in analysis, ensuring the reliability and safety of the whole digital I&C system.
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Geddes, Bruce, and Ray Torok. "Digital I&C Operating Experience in the US." In 16th International Conference on Nuclear Engineering. ASMEDC, 2008. http://dx.doi.org/10.1115/icone16-48862.

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The Electric Power Research Institute (EPRI) is conducting research in cooperation with the Nuclear Energy Institute (NEI) regarding Operating Experience of digital Instrumentation and Control (I&C) systems in US nuclear power plants. The primary objective of this work is to extract insights from US nuclear power plant Operating Experience (OE) reports that can be applied to improve Diversity and Defense in Depth (D3) evaluations and methods for protecting nuclear plants against I&C related Common Cause Failures (CCF) that could disable safety functions and thereby degrade plant safety. Between 1987 and 2007, over 500 OE events involving digital equipment in US nuclear power plants were reported through various channels. OE reports for 324 of these events were found in databases maintained by the Nuclear Regulatory Commission (NRC) and the Institute of Nuclear Power Operations (INPO). A database was prepared for capturing the characteristics of each of the 324 events in terms of when, where, how, and why the event occurred, what steps were taken to correct the deficiency that caused the event, and what defensive measures could have been employed to prevent recurrence of these events. The database also captures the plant system type, its safety classification, and whether or not the event involved a common cause failure. This work has revealed the following results and insights: - 82 of the 324 “digital” events did not actually involve a digital failure. Of these 82 non-digital events, 34 might have been prevented by making full use of digital system fault tolerance features. - 242 of the 324 events did involve failures in digital systems. The leading contributors to the 242 digital failures were hardware failure modes. Software change appears as a corrective action twice as often as it appears as an event root cause. This suggests that software features are being added to avoid recurrence of hardware failures, and that adequately designed software is a strong defensive measure against hardware failure modes, preventing them from propagating into system failures and ultimately plant events. 54 of the 242 digital failures involved a Common Cause Failure (CCF). - 13 of the 54 CCF events affected safety (1E) systems, and only 2 of those were due to Inadequate Software Design. This finding suggests that software related CCFs on 1E systems are no more prevalent than other CCF mechanisms for which adherence to various regulations and standards is considered to provide adequate protection against CCF. This research provides an extensive data set that is being used to investigate many different questions related to failure modes, causes, corrective actions, and other event attributes that can be compared and contrasted to reveal useful insights. Specific considerations in this study included comparison of 1E vs. non-1E systems, active vs. potential CCFs, and possible defensive measures to prevent these events. This paper documents the dominant attributes of the evaluated events and the associated insights that can be used to improve methods for protecting against digital I&C related CCFs, applying a test of reasonable assurance.
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Dalpasso, Marcello, Alessandro Bogliolo, and Luca Benini. "Hardware/software IP protection." In the 37th conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/337292.337588.

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Bao, Han, Tate Shorthill, and Hongbin Zhang. "Hazard Analysis of Digital Engineered Safety Features Actuation System in Advanced Nuclear Power Plants Using a Redundancy-Guided Approach." In 2020 International Conference on Nuclear Engineering collocated with the ASME 2020 Power Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/icone2020-16573.

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Abstract Replacing the existing aging analog instrumentation and control (I&C) systems with modern safety control and protection digital technology offers one of the foremost means of performance improvements and cost reductions for the existing nuclear power plants (NPPs). However, the qualification of digital I&C systems remains a challenge, especially considering the issue of software common-cause failures (CCFs), which are difficult to address. With the application and upgrades of advanced digital I&C systems, software CCFs have become a potential threat to plant safety because most redundant designs use similar digital platforms or software in the operating and application systems. With complex designs of multilayer redundancy to meet the single-failure criterion, digital I&C safety systems (e.g., engineered safety-features actuation system [ESFAS]) are of a particular concern in the U.S. Nuclear Regulatory Commission (NRC) licensing procedures. This paper applies a modularized approach to conduct redundancy-guided systems-theoretic hazard analysis for an advanced digital ESFAS with multilevel redundancy designs. Systematic methods and risk-informed tools are incorporated to address both hardware and software CCFs, which provide guidance to eliminate the triggers of potential single points of failure in the design of digital safety systems in advanced plant designs.
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Sheng, Xin, Xiaojin Huang, Zhencai An, and Yin Guo. "Study on an Optimization Algorithm of Generating Test Vectors for Digital Reactor Protection System Testing." In 16th International Conference on Nuclear Engineering. ASMEDC, 2008. http://dx.doi.org/10.1115/icone16-48098.

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As a safety-critical system for the NPP, the digital Reactor Protection System (RPS) has replaced the traditional analog Reactor Protection System in the most newly-built NPPs. A new type digital RPS developed by INET, Tsinghua University, must pass the hardware qualification and software Verification & Validation (V&V) to satisfy the requirements of quality criterion and safety laws. The stimulation/response testing method is always used in the integration testing phase of software V&V. The test vectors group would be very large if the digital RPS has many input variables. Therefore, In order to find out all of the failure of software, the less testing vectors would be benefit to limit the testing time and cost. A black box model is always be used for those systems with few known information for the Conner. All testing vectors would be generated by nature sequence. The black box model has good features. It does not rely on any prior knowledge about the objective system. However, the black box model may increase the average number of test vectors and average time to find out all of the failure. If a grey box model can be adopted in the testing process, a lot of known information of the objective system can be used and the test time would be saved prominently. As independent developed digital RPS by INET, there is enough information of the testing objects, which can be used to apply the grey box model on the digital RPS testing procedure and to generate the test vectors. An optimization algorithm of test vectors generating is as follows: a) Firstly, a different weight factors would be set to different combination of input variables by expert knowledge and logic design rules; b) Secondly, a particle movement algorithm is used to optimize, compare and select random test vectors by weight factors. The primary simulation results indicate that the average testing time and the number of test vectors are both less than the normal test strategy which based on the black box model. The optimization algorithm of test vectors generating based on the particle movement may be more efficient to find out all of the failure. Therefore, the testing cost and time would be saved in consequence.
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McDonald, J., Ramya Manikyam, Sébastien Bardin, Richard Bonichon, and Todd Andel. "Program Protection through Software-based Hardware Abstraction." In 18th International Conference on Security and Cryptography. SCITEPRESS - Science and Technology Publications, 2021. http://dx.doi.org/10.5220/0010557502470258.

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McDonald, J., Ramya Manikyam, Sébastien Bardin, Richard Bonichon, and Todd Andel. "Program Protection through Software-based Hardware Abstraction." In 18th International Conference on Security and Cryptography. SCITEPRESS - Science and Technology Publications, 2021. http://dx.doi.org/10.5220/0010557500002998.

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Zhang, Yu, Shijiu Jin, Shili Chen, Dongjie Tan, and Likun Wang. "Design of Fast Portable Detection Instrument for Buried Pipeline Coating Defects." In 2006 International Pipeline Conference. ASMEDC, 2006. http://dx.doi.org/10.1115/ipc2006-10136.

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Due to large repair workload and cost, the detection of coating has a great guidance to a major overhaul of buried pipelines. Direct current voltage gradient (DCVG) and close interval potential survey (CIPS) techniques have already been widely used in this area and the theories are introduced in this paper. Based on the above two detection principles, a set of detection instrument for coating defects of buried pipelines is developed, and the detailed hardware and software designs of the instrument is also provided. In this instrument, pipe/soil potential is used to detect coating defects and IR drop (the product of soil current and resistance) is eliminated during potential measurement using instantaneous CP (cathode protection) current cut method. The detection results saved in Flash can be displayed on LCD of the instrument or transferred to the computer for graph plotting. Through the field application examples, it is indicated that the device designed in this article has a very high precision in defects positioning and a broad prospect of application.
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Reports on the topic "Software and hardware protection methods"

1

Miller, A. C. Jr, and E. B. Grann. Advanced hardware and software methods for thread and gear dimensional metrology. CRADA final report. Office of Scientific and Technical Information (OSTI), March 1997. http://dx.doi.org/10.2172/594452.

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Hatcher, Donald J., Terry L. DeVietti, and John A. D'Andrea. Computer Software and Hardware to Determine Contrast Sensitivity Using Three Methods: Tracking, Limits, and Constant Stimuli. Fort Belvoir, VA: Defense Technical Information Center, December 1992. http://dx.doi.org/10.21236/ada265168.

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Feller, D. F. The MSRC Ab Initio Methods Benchmark Suite: A measurement of hardware and software performance in the area of electronic structure methods. Office of Scientific and Technical Information (OSTI), July 1993. http://dx.doi.org/10.2172/10121145.

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Klymenko, Mykola V., and Andrii M. Striuk. Development of software and hardware complex of GPS-tracking. CEUR Workshop Proceedings, March 2021. http://dx.doi.org/10.31812/123456789/4430.

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The paper considers the typical technical features of GPS-tracking systems and their development, as well as an analysis of existing solutions to the problem. Mathematical models for the operation of hardware and software of this complex have been created. An adaptive user interface has been developed that allows you to use this complex from a smartphone or personal computer. Methods for displaying the distance traveled by a moving object on an electronic map have been developed. Atmega162-16PU microcontroller software for GSM module and GPS receiver control has been developed. A method of data transfer from a GPS tracker to a web server has been developed. Two valid experimental samples of GPS-trackers were made and tested in uncertain conditions. The GPS-tracking software and hardware can be used to monitor the movement of moving objects that are within the coverage of GSM cellular networks.
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Vakaliuk, Tetiana A., Valerii V. Kontsedailo, Dmytro S. Antoniuk, Olha V. Korotun, Iryna S. Mintii, and Andrey V. Pikilnyak. Using game simulator Software Inc in the Software Engineering education. [б. в.], February 2020. http://dx.doi.org/10.31812/123456789/3762.

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The article presents the possibilities of using game simulator Sotware Inc in the training of future software engineer in higher education. Attention is drawn to some specific settings that need to be taken into account when training in the course of training future software engineers. More and more educational institutions are introducing new teaching methods, which result in the use of engineering students, in particular, future software engineers, to deal with real professional situations in the learning process. The use of modern ICT, including game simulators, in the educational process, allows to improve the quality of educational material and to enhance the educational effects from the use of innovative pedagogical programs and methods, as it gives teachers additional opportunities for constructing individual educational trajectories of students. The use of ICT allows for a differentiated approach to students with different levels of readiness to study. A feature of any software engineer is the need to understand the related subject area for which the software is being developed. An important condition for the preparation of a highly qualified specialist is the independent fulfillment by the student of scientific research, the generation, and implementation of his idea into a finished commercial product. In the process of research, students gain knowledge, skills of the future IT specialist and competences of the legal protection of the results of intellectual activity, technological audit, marketing, product realization in the market of innovations. Note that when the real-world practice is impossible for students, game simulators that simulate real software development processes are an alternative.
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6

Varina, Hanna B., Viacheslav V. Osadchyi, Kateryna P. Osadcha, Svetlana V. Shevchenko, and Svitlana H. Lytvynova. Peculiarities of cloud computing use in the process of the first-year students' adaptive potential development. [б. в.], June 2021. http://dx.doi.org/10.31812/123456789/4453.

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Technologies based on cloud computing is one of the demanded and actively developing areas of the modern information world. Cloud computing refers to an innovative technology that allows you to combine IT resources of various hardware platforms into a single whole and provide the user with access to them via a local network or the global Internet. Cloud services from various providers offer users access to their resources via the Internet via free or shareware cloud applications, the hardware and software requirements of which do not imply that the user has high-performance and resource-consuming computers. Cloud technologies represent a new way of organizing the educational process and offers an alternative to traditional methods of organizing the educational process, creates an opportunity for personal learning, collective teaching, interactive classes, and the organization of psychological support. The scientific article is devoted to the problem of integrating cloud technologies not only in the process of training highly qualified specialists, but also in the formation of professionally important personality traits. The article describes the experience of introducing cloud technologies into the process of forming the adaptive potential of students in conditions of social constraints caused by the COVID-19 pandemic.
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Modlo, Yevhenii O., Serhiy O. Semerikov, Stanislav L. Bondarevskyi, Stanislav T. Tolmachev, Oksana M. Markova, and Pavlo P. Nechypurenko. Methods of using mobile Internet devices in the formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects. [б. в.], February 2020. http://dx.doi.org/10.31812/123456789/3677.

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An analysis of the experience of professional training bachelors of electromechanics in Ukraine and abroad made it possible to determine that one of the leading trends in its modernization is the synergistic integration of various engineering branches (mechanical, electrical, electronic engineering and automation) in mechatronics for the purpose of design, manufacture, operation and maintenance electromechanical equipment. Teaching mechatronics provides for the meaningful integration of various disciplines of professional and practical training bachelors of electromechanics based on the concept of modeling and technological integration of various organizational forms and teaching methods based on the concept of mobility. Within this approach, the leading learning tools of bachelors of electromechanics are mobile Internet devices (MID) – a multimedia mobile devices that provide wireless access to information and communication Internet services for collecting, organizing, storing, processing, transmitting, presenting all kinds of messages and data. The authors reveals the main possibilities of using MID in learning to ensure equal access to education, personalized learning, instant feedback and evaluating learning outcomes, mobile learning, productive use of time spent in classrooms, creating mobile learning communities, support situated learning, development of continuous seamless learning, ensuring the gap between formal and informal learning, minimize educational disruption in conflict and disaster areas, assist learners with disabilities, improve the quality of the communication and the management of institution, and maximize the cost-efficiency. Bachelor of electromechanics competency in modeling of technical objects is a personal and vocational ability, which includes a system of knowledge, skills, experience in learning and research activities on modeling mechatronic systems and a positive value attitude towards it; bachelor of electromechanics should be ready and able to use methods and software/hardware modeling tools for processes analyzes, systems synthesis, evaluating their reliability and effectiveness for solving practical problems in professional field. The competency structure of the bachelor of electromechanics in the modeling of technical objects is reflected in three groups of competencies: general scientific, general professional and specialized professional. The implementation of the technique of using MID in learning bachelors of electromechanics in modeling of technical objects is the appropriate methodic of using, the component of which is partial methods for using MID in the formation of the general scientific component of the bachelor of electromechanics competency in modeling of technical objects, are disclosed by example academic disciplines “Higher mathematics”, “Computers and programming”, “Engineering mechanics”, “Electrical machines”. The leading tools of formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects are augmented reality mobile tools (to visualize the objects’ structure and modeling results), mobile computer mathematical systems (universal tools used at all stages of modeling learning), cloud based spreadsheets (as modeling tools) and text editors (to make the program description of model), mobile computer-aided design systems (to create and view the physical properties of models of technical objects) and mobile communication tools (to organize a joint activity in modeling).
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Lavrentieva, Olena O., Ihor O. Arkhypov, Olexander I. Kuchma, and Aleksandr D. Uchitel. Use of simulators together with virtual and augmented reality in the system of welders’ vocational training: past, present, and future. [б. в.], February 2020. http://dx.doi.org/10.31812/123456789/3748.

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The article discusses the theory and methods of simulation training, its significance in the context of training specialists for areas where the lack of primary qualification is critical. The most widespread hardware and software solutions for the organization welders' simulation training that use VR- and AR- technologies have been analyzed. A review of the technological infrastructure and software tools for the virtual teaching-and-production laboratory of electric welding has been made on the example of the achievements of Fronius, MIMBUS, Seabery. The features of creating a virtual simulation of the welding process using modern equipment based on studies of the behavioral reactions of the welder have been shown. It is found the simulators allow not only training, but also one can build neuro-fuzzy logic and design automated and robotized welding systems. The functioning peculiarities of welding's simulators with AR have been revealed. It is shown they make it possible to ensure the forming basic qualities of a future specialist, such as concentration, accuracy and agility. The psychological and technical aspects of the coaching programs for the training and retraining of qualified welders have been illustrated. The conclusions about the significant advantages of VR- and AR-technologies in comparison with traditional ones have been made. Possible directions of the development of simulation training for welders have been revealed. Among them the AR-technologies have been presented as such that gaining wide popularity as allow to realize the idea of mass training in basic professional skills.
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Martyniuk, Oleksandr O., Oleksandr S. Martyniuk, and Ivan O. Muzyka. Formation of informational and digital competence of secondary school students in laboratory work in physics. [б. в.], June 2021. http://dx.doi.org/10.31812/123456789/4446.

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The article deals with the formation of informational and digital competence of high school students. First and foremost, the existing digitalization strategies for society already approved in the world and in Ukraine, including the implementation of STEM education and the Digital Agenda, are considered. On the other hand, attention is paid to the inconsistency of the level of ownership and frequency of use of digital technologies with the requirements of these initiatives. The concept of informational and digital competence is analyzed in detail. Existing publications identify key components, skills and competencies required to achieve this competence. A survey is conducted to better understand the current situation. One of the tasks is to determine the level of use of digital information in the classroom by teachers and in students’ preparation at home. The second task was to show how developing students’ informational and digital competence can be done by active introduction of existing software and hardware in the educational process in physics, in particular, a laboratory workshop. The example of laboratory work carried out in educational institutions shows how modern software can be used to analyze the movement of bodies and determine the physical characteristics of this movement. The concrete ways of performing laboratory work, analyzing its results and drawing conclusions are given. It is in the combination of existing teaching practices with modern gadgets, specialized and general programs that the basic way of forming informational and digital competence is seen. Further ways of modernization and improvement of described methods for increasing the level of information and digital competence are proposed.
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