Relevant bibliographies by topics / Software acceleration

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Software acceleration'

Author: Grafiati
Published: 25 May 2024

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Journal articles on the topic "Software acceleration"

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Long, Gary. "Acceleration Characteristics of Starting Vehicles." Transportation Research Record: Journal of the Transportation Research Board 1737, no. 1 (January 2000): 58–70. http://dx.doi.org/10.3141/1737-08.

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Acceleration characteristics of starting vehicles are needed for many transportation analysis and design purposes involving driveways, turning bays, intersecting streets, traffic signals, railroad crossings, simulation software, and so forth. Constant acceleration is sometimes assumed, or AASHTO Green Book values based on piecewise-constant accelerations are sometimes adopted. However, continuing research has shown that linearly decreasing acceleration rates better represent both maximum vehicle acceleration capabilities and actual motorist behavior. It is not acceleration that usually is constant during speed changes; it is the rate of change in acceleration. The evolution of AASHTO acceleration values for design is traced, and the literature is reviewed for pertinent field observations. Linearly decreasing acceleration (and some deceleration) model parameters are calibrated for various sets of observational and design data. Despite published results from thousands of field measurements, the values selected for design were found to be based mostly on vehicle performance capabilities, with conjecture about how many of these capabilities are normally used by drivers. Design accelerations were found to deviate substantially from observed accelerations. At the start of motion, observed accelerations were about 15 percent faster for passenger cars and 45 percent faster for SU (single unit) trucks than design accelerations. As speed increased, observed accelerations dropped three to four times faster than design accelerations for these vehicles. Observed accelerations for WB-15 trucks began 40 percent to 75 percent slower than design accelerations, and they were considerably slower than the values in the Green Book for trucks at railroad crossings. Voids in the available information base are identified. Linearly decreasing design acceleration rates for motorists operating different classes of vehicles in different design situations are recommended, and revisions for Green Book parameters and charts are suggested. The recommended acceleration model greatly simplifies acceleration parameters but implies using different acceleration relationships for different design speeds instead of one for all.
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An, Xiao Xue, Xiao Dong Chai, Wen Fa Zhu, and Xiao Wei Xu. "Software Design of the Track State Inspection System Based on LabVIEW." Advanced Materials Research 546-547 (July 2012): 1323–28. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.1323.

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This paper describes the software of the track state inspection system based on LABVIEW, which includes serial communication, data extraction, strap-down algorithm, acceleration integral and saving the results. Serial communication module uses VISA to program in order to realize communication between the IMU (inertial measurement unit)and upper computer. According to the output data format, data extraction module separates the signal of three axes’ accelerations and angular-rates by Match Pattern Function. Strap-down algorithm and acceleration integral modules are programmed by Math Script. The measurement results are saved by Write to Spreadsheet File Function. Finally, it’s to design a convenient humanized operation interface.
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Edwards, M. D., and J. Forrest. "Software acceleration using programmable hardware devices." IEE Proceedings - Computers and Digital Techniques 143, no. 1 (1996): 55. http://dx.doi.org/10.1049/ip-cdt:19960066.

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Boroushak, Neda, Hasan Khoshnoodi, and Mostafa Rostami. "Investigation of the Head’s Dynamic Response to Boxing Punch Using Computer Simulation." Montenegrin Journal of Sports Science and Medicine 10, no. 1 (March 1, 2021): 31–35. http://dx.doi.org/10.26773/mjssm.210305.

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Head injuries are dangerous injuries that are common in combat sports. Nevertheless, the mechanisms of concussion in sport have are not precisely known. Thus, this study aimed to investigate the dynamic response of the head based on linear and rotational accelerations in boxing using computer simulation. The ADAMS software model was used to determine the linear and rotational acceleration of boxing’s straight punch. The peak linear acceleration, average linear acceleration, peak rotational acceleration, and average rotational acceleration resulted from the straight punch to head were obtained: 75 g, 20 g, 4036 rad/s², 1140 rad/s², respectively; the impact times were 30 ms and 3 ms, respectively. The comparison of acceleration tolerance thresholds of head injury and obtained results of this study showed the rotational acceleration only leads to head injury. Furthermore, it is biomechanically improbable that the head would be moved only translationally or rotationally as a result of a straight punch. Therefore, both rotational and linear accelerations should be observed together for future studies.
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Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (October 18, 2018): 122. http://dx.doi.org/10.3390/jimaging4100122.

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Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images.
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Manor, Erez, Avrech Ben-David, and Shlomo Greenberg. "CORDIC Hardware Acceleration Using DMA-Based ISA Extension." Journal of Low Power Electronics and Applications 12, no. 1 (January 15, 2022): 4. http://dx.doi.org/10.3390/jlpea12010004.

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The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator.
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Edwards, M. D., J. Forrest, and A. E. Whelan. "Acceleration of software algorithms using hardware/software co-design techniques." Journal of Systems Architecture 42, no. 9-10 (February 1997): 697–707. http://dx.doi.org/10.1016/s1383-7621(96)00071-9.

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Thompson, David L. "Time, Speed and Acceleration—a software package." Electronic Systems News 1988, no. 3 (1988): 28. http://dx.doi.org/10.1049/esn.1988.0064.

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Tang, Wenkai, and Peiyong Zhang. "GPGCN: A General-Purpose Graph Convolution Neural Network Accelerator Based on RISC-V ISA Extension." Electronics 11, no. 22 (November 21, 2022): 3833. http://dx.doi.org/10.3390/electronics11223833.

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In the past two years, various graph convolution neural networks (GCNs) accelerators have emerged, each with their own characteristics, but their common disadvantage is that the hardware architecture is not programmable and it is optimized for a specific network and dataset. They may not support acceleration for different GCNs and may not achieve optimal hardware resource utilization for datasets of different sizes. Therefore, given the above shortcomings, and according to the development trend of traditional neural network accelerators, this paper proposes and implements GPGCN: a general-purpose GCNs accelerator architecture based on RISC-V instruction set extension, providing the software programming freedom to support acceleration for various GCNs, and achieving the best acceleration efficiency for different GCNs with different datasets. Compared with traditional CPU, and traditional CPU with vector expansion, GPGCN achieves above 1001×, 267× speedup for GCN with the Cora dataset. Compared with dedicated accelerators, GPGCN has software programmability and supports the acceleration of more GCNs.
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Farouk, Yasmeen, and Sherine Rady. "Optimizing MRI Registration using Software/Hardware Co-Design Model on FPGA." International Journal of Innovative Technology and Exploring Engineering 10, no. 2 (December 10, 2020): 128–37. http://dx.doi.org/10.35940/ijitee.b8300.1210220.

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The correct localization of brain tissue deformation and determination of the tumor growth relies majorly on the accuracy of the process known by image registration. Poor registration may lead to misclassified diseases and highly affect image-guided surgery and radiation therapies. Voxel-based morphometry (VBM) is an image analytical technique encompassing accurate registration but suffers from intensive time computations, similar to most of image registration techniques. Achieving the compromise between accuracy and computations is a challenging mission. Field programmable gate arrays have fast-evolving and customizable hardware acceleration capabilities that promise to help speed up computational tasks. This paper presents a software/hardware co-design model for accelerating the implementation of the diffeomorphic image registration algorithm ‘DARTEL’ as a part of VBM that analyzes MRI images. An optimized and pipelined hardware architecture is proposed and integrated into the Statistical Parametric Mapping (SPM) software tool that runs the DARTEL. Acceleration of the DARTEL registration algorithm resulted in a speedup factor of 114x on function-level, compared to the CPU with a contribution of 8x faster for the overall performance in the registration process of the SPM. The proposed model is successfully validated for the identification of Alzheimer’s disease based on T1-weighted MRI. A proposed software/hardware co-design model for VBM achieves remarkable acceleration while maintaining classification accuracy and proving proficiency against other CPU and GPU implementations.
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Dissertations / Theses on the topic "Software acceleration"

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Borgström, Fredrik. "Acceleration of FreeRTOS withSierra RTOS accelerator : Implementation of a FreeRTOS software layer onSierra RTOS accelerator." Thesis, KTH, Data- och elektroteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188518.

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Today, the effect of the most common ways to improve the performance of embedded systems and real-time operating systems is stagnating. Therefore it is interesting to examine new ways to push the performance boundaries of embedded systems and real-time operating systems even further. It has previously been demonstrated that the hardware-based real-time operating system, Sierra, has better performance than the software-based real-time operating system, FreeRTOS. These real-time operating systems have also been shown to be similar in many aspects, which mean that it is possible for Sierra to accelerate FreeRTOS. In this thesis an implementation of such acceleration has been carried out. Because existing real-time operating systems are constantly in development combined with that it was several years since an earlier comparison between the two real-time operating systems was per-formed, FreeRTOS and Sierra were compared in terms of functionality and architecture also in this thesis. This comparison showed that FreeRTOS and Sierra share the most fundamental functions of a real-time operating system, and thus can be accelerated by Sierra, but that FreeRTOS also has a number of exclusive functions to facilitate the use of that real-time operating system. The infor-mation obtained by this comparison was the very essence of how the acceleration would be imple-mented. After a number of performance tests it could be concluded that all of the implemented functions, with the exception of a few, had shorter execution time than the corresponding functions in the original version of FreeRTOS.
Idag är effekten av de vanligaste åtgärderna för att förbättra prestandan av inbyggda system och realtidsoperativsystem väldigt liten. På grund av detta är det intressant att undersöka nya åtgärder för att tänja prestandagränserna av inbyggda system och realtidsoperativsystem ytterliggare. Det har tidigare påvisats att det hårdvarubaseraderealtidsoperativsystemet, Sierra, har bättre prestanda än det mjukvarubaseraderealtidsoperativsystemet, FreeRTOS. Dessa realtidsoperativsystem har även visats vara lika i flera aspekter, vilket betyder att det är möjligt för Sierra att accelererera FreeRTOS. I detta examensarbete har en implementering av en sådan acceleration genomförts. Eftersom befintliga realtidsoperativsystem ständigtär i utveckling i kombination med att det är flera år sedan som en tidigare jämförelse mellan de båda systemen utfördes, så jämfördes FreeRTOS och Sierra i fråga om funktionalitet och uppbyggnad även i detta examensarbete.Denna jämförelse visade att FreeRTOS och Sierra delar de mest grundläggande funktionerna av ett realtidsoperativsystem, och som därmed kan accelereras av Sierra, men att FreeRTOS även har ett antal exklusiva funktioner för att underlätta användningen av det realtidsoperativsystemet. Informationen som erhölls av denna jämförelse var sedan grunden för hur själva accelerationen skulle implementeras. Efter ett antal prestandatesterkunde det konstateras att alla implementerade funktioner, med undantag för ett fåtal, hade kortare exekveringstid än motsvarande funktioner i ursprungsversionen av FreeRTOS.
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Kulkarni, Pallavi Anil. "Hardware acceleration of software library string functions." Ann Arbor, Mich. : ProQuest, 2007. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1447245.

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Thesis (M.S. in Computer Engineering)--S.M.U., 2007.
Title from PDF title page (viewed Nov. 19, 2009). Source: Masters Abstracts International, Volume: 46-03, page: 1577. Adviser: Mitch Thornton. Includes bibliographical references.
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Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.

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The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by migration systems to accelerate RTL simulation. In this dissertation, process migration is first formally modeled using Finite State Machines (FSMs). Upon FSMs are built programs, processes, migration realms, and the migration of process state within a realm. From this model, a taxonomy of migration realms is developed. Second, process migration is applied to the RTL simulation of digital circuits. The canonical form of an RTL process is defined, and transformations of HDL code are justified and demonstrated. These transformations allow a simulator to identify basic active units within the simulation and combine them to balance the load across a set of processors. Through the use of input monitors, executive locality of reference is identified and demonstrated on a set of six RTL designs. Finally, the implementation of a migration system is described which utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and algorithmic models are developed from the data collected from the implementation to evaluate the effect of optimizations and migration algorithms.
Ph. D.
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Samothrakis, Stavros Nikolaou. "Acceleration techniques in ray tracing for dynamic scenes." Thesis, University of Sussex, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241671.

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Singh, Ajeet. "GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/34264.

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Hardware-acceleration techniques continue to be used to boost the performance of scientific codes. To do so, software developers identify portions of these codes that are amenable for offloading and map them to hardware accelerators. However, offloading such tasks to specialized hardware accelerators is non-trivial. Furthermore, these accelerators can add significant cost to a computing system.

Consequently, this thesis proposes a framework called GePSeA (General Purpose Software Acceleration Framework), which uses a small fraction of the computational power on multi-core architectures to offload complex application-specific tasks. Specifically, GePSeA provides a lightweight process that acts as a helper agent to the application by executing application-specific tasks asynchronously and efficiently. GePSeA is not meant to replace hardware accelerators but to extend them. GePSeA provide several utilities called core components that offload tasks on to the core or to the special-purpose hardware when available in a way that is transparent to the application. Examples of such core components include reliable communication service, distributed lock management, global memory management, dynamic load distribution and network protocol processing. We then apply the GePSeA framework to two applications, namely mpiBLAST, an open-source computational biology application and Reliable Blast UDP (RBUDP) based file transfer application. We observe significant speed-up for both applications.
Master of Science

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Zhu, Huanzhou. "Developing graph-based co-scheduling algorithms with GPU acceleration." Thesis, University of Warwick, 2016. http://wrap.warwick.ac.uk/92000/.

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On-chip cache is often shared between processes that run concurrently on different cores of the same processor. Resource contention of this type causes the performance degradation to the co-running processes. Contention-aware co-scheduling refers to the class of scheduling techniques to reduce the performance degradation. Most existing contention-aware co-schedulers only consider serial jobs. However, there often exist both parallel and serial jobs in computing systems. This thesis aims to tackle these issues. We start with modelling the problem of co-scheduling the mix of serial and parallel jobs as an Integer Programming (IP) problem. Then we construct a co-scheduling graph to model the problem, and a set of algorithms are developed to find both optimal and near-optimal solutions. The results show that the proposed algorithms can find the optimal co-scheduling solution and that the proposed approximation technique is able to find the near optimal solutions. In order to improve the scalability of the algorithms, we use GPU to accelerate the solving process. A graph processing framework, called WolfPath, is proposed in this thesis. By taking advantage of the co-scheduling graph, WolfPath achieves significant performance improvement. Due to the long preprocessing time of WolfPath, we developed WolfGraph, a GPU-based graph processing framework that features minimal preprocessing time and uses the hard disk as a memory extension to solve large-scale graphs on a single machine equipped with a GPU device. Comparing with existing GPU-based graph processing frameworks, WolfGraph can achieve similar execution time but with minimal preprocessing time.
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Yalim, Hacer. "Acceleration Of Direct Volume Rendering With Texture Slabs On Programmable Graphics Hardware." Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/12606195/index.pdf.

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This thesis proposes an efficient method to accelerate ray based volume rendering with texture slabs using programmable graphics hardware. In this method, empty space skipping and early ray termination are utilized without performing any preprocessing on CPU side. The acceleration structure is created on the fly by making use of depth buffer efficiently on Graphics Processing Unit (GPU) side. In the proposed method, texture slices are grouped together to form a texture slab. Rendering all the slabs from front to back viewing order in multiple rendering passes generates the resulting volume image. Slab silhouette maps (SSM) are created to identify and skip empty spaces along the ray direction at pixel level. These maps are created from the alpha component of the slab and stored in the depth buffer. In addition to the empty region information, SSM also contains information about the terminated rays. The method relies on hardware z-occlusion culling that is realized by means of SSMs to accelerate ray traversals. The cost of generating this acceleration data structure is very small compared to the total rendering time.
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Sherban, V. Yu. "Software components of the system for the kinematic and dynamic analysis of machines for sewing, textile and shoe industries." Thesis, Київський національний університет технологій та дизайну, 2017. https://er.knutd.edu.ua/handle/123456789/6655.

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Wang, Tsu-Han. "Real-time Software Architectures and Performance Evaluation Methods for 5G Radio Systems." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS362.pdf.

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La thèse porte sur les architectures temps réel pour la radio-logicielle 5G. Afin de répondre aux exigences de performances de la 5G, une accélération des procédés critiques combinée à des méthodes d’ordonnancement de processus temps réels sont nécessaires. Dans les systèmes embarqués 5G, l'accélération équivaut à une combinaison judicieuse d'unités matérielles supplémentaires pour les fonctions les plus coûteuses en termes de calcul avec des composants logiciels pour des procédures de contrôle complexe ainsi que l’arithmétique simples. Des solutions entièrement logicielles apparaissent également pour certaines applications, notamment dans l'écosystème dit Open Radio-Access Network (openRAN). Les contributions de cette thèse résident dans des méthodes d'accélération purement logicielles et de contrôle en temps réel d'interfaces dit « fronthaul » à faible latence. Étant donné que la 5G a des exigences de latence strictes et prend en charge le trafic de données à très haut débit, les méthodes d’ordonnancement du traitement en bande de base doivent être adaptées aux spécificités de l'interface radio. Plus précisément, nous proposons une décomposition fonctionnelle de l'interface-air 5G qui se prête à des implémentations logicielles multicœurs ciblant des serveurs haut de gamme exploitant l'accélération de données multiples à instruction unique (SIMD). De plus, nous fournissons quelques pistes pour le traitement multithread via le pipelining et l'utilisation de pools de threads. Nous mettons en évidence les méthodes et la caractérisation de leur performances qui ont été exploitées lors du développement de l'implémentation OpenAirInterface 5G
The thesis deals with 5G real-time Software Defined Radio architectures. In order to match 5G performance requirements, computational acceleration combined with real-time process scheduling methods are required. In 5G embedded systems acceleration amounts to a judicious combination additional hardware units for the most computationally costly functions with software for simpler arithmetic and complex control procedures. Fully software-based solutions are also appearing for certain applications, in particular in the so-called Open Radio-Access Network (openRAN) ecosystem. The contributions of this thesis lie in methods for purely software-based acceleration and real-time control of low-latency fronthaul interfaces. Since 5G has stringent latency requirements and support for very high-speed data traffic, methods for scheduling baseband processing need to be tailored to the specifics of the air-interface. Specifically, we propose a functional decomposition of the 5G air interface which is amenable to multi-core software implementations targeting high-end servers exploiting single-instruction multiple-data (SIMD) acceleration. Moreover, we provide some avenues for multi-threaded processing through pipelining and the use of thread pools. We highlight the methods and their performance evaluation that have been exploited during the development of the OpenAirInterface 5G implementation
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Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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Books on the topic "Software acceleration"

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Mourelle, Luiza de Macedo. Hardware/Software interfacing in a software acceleration environment. Manchester: UMIST, 1997.

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Nikkhah, B. A hardware/software partitioning scheme for software acceleration. Manchestr: UMIST, 1997.

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Mizrakian, V. Software acceleration of image processing algorithms using hardware implementation. Manchester: UMIST, 1997.

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Mizrakian, V. Software acceleration of image processing algorithms using hardware implementation. Manchester: UMIST, 1997.

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Luigi, Carro, ed. Dynamic reconfigurable architectures and transparent optimization techniques: Automatic acceleration of software execution. Dordrecht: Springer, 2010.

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1970-, Ratliff Bud, ed. Microsoft Internet security and acceleration (ISA) server 2000. Redmond, Wash: Microsoft Press, 2003.

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1973-, Thomas Orin, and Microsoft Corporation, eds. MCSA/MCSE self-paced training kit (exam 70-350): Implementing Microsoft internet security and acceleration server 2004. Redmond, Wash: Microsoft Press, 2005.

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Tin, Michael Yu Chak. ExamInsightfor MCP/MCSE certification: Microsoft internet security and acceleration (ISA) server 2000, enterprise edition exam 70-227. Friendswood, Tex: TotalRecall Publications, 2003.

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Tin, Michael Yu Chak. ExamWise for MCP/MCSE certification: Microsoft internet security and acceleration (ISA) server 2000, enterprise edition exam 70-227. Friendswood, Tex: TotalRecall Publications, 2003.

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United States. National Aeronautics and Space Administration., ed. A method to determine the kinematics of the lower limbs of a subject pedaling a bicycle using encoders and accelerometers. [Washington, D.C.]: National Aeronautics and Space Administration, 1994.

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Book chapters on the topic "Software acceleration"

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Cattaruzza, Dario, Alessandro Abate, Peter Schrammel, and Daniel Kroening. "Sound Numerical Computations in Abstract Acceleration." In Numerical Software Verification, 38–60. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-63501-9_4.

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Gulati, Kanupriya, and Sunil P. Khatri. "Automated Approach for Graphics Processor Based Software Acceleration." In Hardware Acceleration of EDA Algorithms, 169–80. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-0944-2_11.

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Schmid, Moritz, Christian Schmitt, Frank Hannig, Gorker Alp Malazgirt, Nehir Sonmez, Arda Yurdakul, and Adrian Cristal. "Big Data and HPC Acceleration with Vivado HLS." In FPGAs for Software Programmers, 115–36. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-26408-0_7.

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Leroux, Jérôme, and Grégoire Sutre. "Acceleration in Convex Data-Flow Analysis." In FSTTCS 2007: Foundations of Software Technology and Theoretical Computer Science, 520–31. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-77050-3_43.

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Beevi, F. H. Aysha, C. F. Pedersen, S. Wagner, and S. Hallerstede. "Lateral Fall Detection via Events in Linear Prediction Residual of Acceleration." In Ambient Intelligence - Software and Applications, 201–8. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07596-9_22.

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Šimková, Marcela, and Ondřej Lengál. "Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures." In Hardware and Software: Verification and Testing, 266–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3_25.

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Liu, Yang, and Liang Deng. "Acceleration of CFD Engineering Software on GPU and MIC." In Algorithms and Architectures for Parallel Processing, 835–48. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-27161-3_77.

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Wang, Yanwei, Bingbing Li, Lu Lu, Jiangwei Wang, Rengang Li, and Hongwei Kan. "Hardware-Software Co-design for Deep Neural Network Acceleration." In Communications in Computer and Information Science, 221–30. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-4402-6_16.

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Yan, Jiong, Ji Wang, and Huo-wang Chen. "UML Based Statistical Testing Acceleration of Distributed Safety-Critical Software." In Parallel and Distributed Processing and Applications, 433–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30566-8_52.

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Saremi, Razieh, Ye Yang, and Abdullah Khanfor. "Ant Colony Optimization to Reduce Schedule Acceleration in Crowdsourcing Software Development." In Human Interface and the Management of Information. Information in Intelligent Systems, 286–300. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-22649-7_23.

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Conference papers on the topic "Software acceleration"

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Wu, Shengfeng, Yue Wu, and Shiyi Xu. "Acceleration of Random Testing for Software." In 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing (PRDC). IEEE, 2013. http://dx.doi.org/10.1109/prdc.2013.15.

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Sredojevic, Ranko, Andrew Wright, and Vladimir Stojanovic. "Hardware-Software Codesign for Embedded Numerical Acceleration." In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2013. http://dx.doi.org/10.1109/fccm.2013.27.

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Turan, Furkan, Ruan de Clercq, Pieter Maene, Oscar Reparaz, and Ingrid Verbauwhede. "Hardware acceleration of a software-based VPN." In 2016 26th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2016. http://dx.doi.org/10.1109/fpl.2016.7577321.

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Wei, Tianrui, Nazerke Turtayeva, Marcelo Orenes-Vera, Omkar Lonkar, and Jonathan Balkind. "Cohort: Software-Oriented Acceleration for Heterogeneous SoCs." In ASPLOS '23: 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3. New York, NY, USA: ACM, 2023. http://dx.doi.org/10.1145/3582016.3582059.

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Yaneva, Vanya. "Compiler-assisted test acceleration using GPUs." In ICSE '18: 40th International Conference on Software Engineering. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3183440.3190337.

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Bonelli, Nicola, Gregorio Procissi, Davide Sanvito, and Roberto Bifulco. "The acceleration of OfSoftSwitch." In 2017 IEEE Conference on Network Function Virtualization and Software-Defined Networks (NFV-SDN). IEEE, 2017. http://dx.doi.org/10.1109/nfv-sdn.2017.8169842.

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Ghis, Abdelkader, Kamel Smiri, and Abderezzak Jemai. "Mixed Software/Hardware based Neural Network Learning Acceleration." In 16th International Conference on Software Technologies. SCITEPRESS - Science and Technology Publications, 2021. http://dx.doi.org/10.5220/0010606104170425.

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Ghis, Abdelkader, Kamel Smiri, and Abderezzak Jemai. "Mixed Software/Hardware based Neural Network Learning Acceleration." In 16th International Conference on Software Technologies. SCITEPRESS - Science and Technology Publications, 2021. http://dx.doi.org/10.5220/0010606100002992.

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Atoofian, Ehsan. "Acceleration of Software Transactional Memory through Hardware Clock." In International Workshop. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2613908.2613912.

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Jin, Qiwei, David B. Thomas, and Wayne Luk. "Automated application acceleration using software to hardware transformation." In 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. http://dx.doi.org/10.1109/fpt.2009.5377693.

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Reports on the topic "Software acceleration"

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Olsen, B. Accelerator Production of Tritium Software Management Plan. Office of Scientific and Technical Information (OSTI), June 1998. http://dx.doi.org/10.2172/763183.

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Razdan, Rahul. Unsettled Issues Regarding Autonomous Vehicles and Open-source Software. SAE International, April 2021. http://dx.doi.org/10.4271/epr2021009.

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As automobiles morph from stand-alone mechanical objects to highly connected, autonomous systems with increasing amounts of electronic components. To manage these complex systems, some semblance of in-car decision-making is also being built and networked to a cloud architecture. This cloud can also enable even deeper capabilities within the broader automotive ecosystem. Unsettled Issues Regarding Autonomous Vehicles and Open-source Software introduces the impact of software in advanced automotive applications, the role of open-source communities in accelerating innovation, and the important topic of safety and cybersecurity. As electronic functionality is captured in software and a bigger percentage of that software is open-source code, some critical challenges arise concerning security and validation.
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Heuring, Vincent P., and William M. Waite. Accelerating the Transfer of Technology for Implementing Domain Specific Software Architectures. Fort Belvoir, VA: Defense Technical Information Center, April 1993. http://dx.doi.org/10.21236/ada264017.

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Waraniak, John. Unsettled Issues on Sensor Calibration for Automotive Aftermarket Advanced Driver-Assistance Systems. SAE International, March 2021. http://dx.doi.org/10.4271/epr2021008.

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Many automotive industry safety advocates have been pushing for greater market penetration for active safety and advanced driver-assistance systems (ADAS), with the goal of ending deaths due to car crashes. However, there are far-reaching implications for the collision repair, specialty equipment, and performance aftermarket sectors—after a collision or modification, the ADAS system functionality must be preserved to maintain, driver, passenger, and road user safety. To do this, sensor recalibration and ADAS functional safety validation and documentation after repair, modification, or accessorizing are necessary. Unsettled Issues on Sensor Calibration for Automotive Aftermarket ADAS tackles the challenges of accelerating the pace of ADAS implementation; increasing industry understanding of systems, sensors, software, controllers; and minimizing the overwhelming variety of sensor calibration procedures and automaker targets. Additionally, this report addresses the liability concerns that are challenging the industry as it seeks to move forward safely.
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Kerrigan, Susan, Phillip McIntyre, and Marion McCutcheon. Australian Cultural and Creative Activity: A Population and Hotspot Analysis: Bendigo. Queensland University of Technology, 2020. http://dx.doi.org/10.5204/rep.eprints.206968.

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Bendigo, where the traditional owners are the Dja Dja Wurrung people, has capitalised on its European historical roots. Its striking architecture owes much to its Gold Rush past which has also given it a diverse cultural heritage. The creative industries, while not well recognised as such, contribute well to the local economy. The many festivals, museums and library exhibitions attract visitors from the metropolitan centre of Victoria especially. The Bendigo Creative Industries Hub was a local council initiative while the Ulumbarra Theatre is located within the City’s 1860’s Sandhurst Gaol. Many festivals keep the city culturally active and are supported by organisations such as Bendigo Bank. The Bendigo Writers Festival, the Bendigo Queer Film Festival, The Bendigo Invention & Innovation Festival, Groovin the Moo and the Bendigo Blues and Roots Music Festival are well established within the community. A regional accelerator and Tech School at La Trobe University are touted as models for other regional Victorian cities. The city has a range of high quality design agencies, while the software and digital content sector is growing with embeddeds working in agriculture and information management systems. Employment in Film, TV and Radio and Visual Arts has remained steady in Bendigo for a decade while the Music and Performing Arts sector grew quite well over the same period.
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Tao, Yang, Amos Mizrach, Victor Alchanatis, Nachshon Shamir, and Tom Porter. Automated imaging broiler chicksexing for gender-specific and efficient production. United States Department of Agriculture, December 2014. http://dx.doi.org/10.32747/2014.7594391.bard.

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Extending the previous two years of research results (Mizarch, et al, 2012, Tao, 2011, 2012), the third year’s efforts in both Maryland and Israel were directed towards the engineering of the system. The activities included the robust chick handling and its conveyor system development, optical system improvement, online dynamic motion imaging of chicks, multi-image sequence optimal feather extraction and detection, and pattern recognition. Mechanical System Engineering The third model of the mechanical chick handling system with high-speed imaging system was built as shown in Fig. 1. This system has the improved chick holding cups and motion mechanisms that enable chicks to open wings through the view section. The mechanical system has achieved the speed of 4 chicks per second which exceeds the design specs of 3 chicks per second. In the center of the conveyor, a high-speed camera with UV sensitive optical system, shown in Fig.2, was installed that captures chick images at multiple frames (45 images and system selectable) when the chick passing through the view area. Through intensive discussions and efforts, the PIs of Maryland and ARO have created the protocol of joint hardware and software that uses sequential images of chick in its fall motion to capture opening wings and extract the optimal opening positions. This approached enables the reliable feather feature extraction in dynamic motion and pattern recognition. Improving of Chick Wing Deployment The mechanical system for chick conveying and especially the section that cause chicks to deploy their wings wide open under the fast video camera and the UV light was investigated along the third study year. As a natural behavior, chicks tend to deploy their wings as a mean of balancing their body when a sudden change in the vertical movement was applied. In the latest two years, this was achieved by causing the chicks to move in a free fall, in the earth gravity (g) along short vertical distance. The chicks have always tended to deploy their wing but not always in wide horizontal open situation. Such position is requested in order to get successful image under the video camera. Besides, the cells with checks bumped suddenly at the end of the free falling path. That caused the chicks legs to collapse inside the cells and the image of wing become bluer. For improving the movement and preventing the chick legs from collapsing, a slowing down mechanism was design and tested. This was done by installing of plastic block, that was printed in a predesign variable slope (Fig. 3) at the end of the path of falling cells (Fig.4). The cells are moving down in variable velocity according the block slope and achieve zero velocity at the end of the path. The slop was design in a way that the deacceleration become 0.8g instead the free fall gravity (g) without presence of the block. The tests showed better deployment and wider chick's wing opening as well as better balance along the movement. Design of additional sizes of block slops is under investigation. Slops that create accelerations of 0.7g, 0.9g, and variable accelerations are designed for improving movement path and images.
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