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Journal articles on the topic 'Single-bit sigma-delta modulator'

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Published: 4 June 2021

Last updated: 4 February 2022

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1

Haimeng, Sun, R. Kochan, O. Kochan, and Su Jun. "INTEGRAL NONLINEARITY OF SECOND-ORDER SINGLE-BIT SIGMA-DELTA MODULATOR." Tekhnichna Elektrodynamika 2016, no. 6 (September 29, 2016): 63–68. http://dx.doi.org/10.15407/techned2016.06.063.

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2

NERURKAR, SHAILESH B., and KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

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3

Reyhani, S. Z., and O. Hashemipour. "SAR‐based delta–sigma modulator using single‐bit shared‐DAC." Electronics Letters 50, no. 3 (January 2014): 156–58. http://dx.doi.org/10.1049/el.2013.3589.

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4

Thompson, A. C., P. O'Shea, Z. M. Hussain, and B. R. Steele. "Efficient Single-Bit Ternary Digital Filtering Using Sigma-Delta Modulator." IEEE Signal Processing Letters 11, no. 2 (February 2004): 164–66. http://dx.doi.org/10.1109/lsp.2003.821734.

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5

Shao, Qi, Qiu Ye Lv, Hao Meng, Qiang Fu, and Xiao Wei Liu. "A Feed-Forward Sigma-Delta Modulator Applied in Silicon Gyroscope." Key Engineering Materials 645-646 (May 2015): 657–61. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.657.

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Aiming to be applied in silicon gyroscope, a three-order single loop feedforward modulator with three-bit quantizer and local feedback is designed in this paper. Signal band is 200 KHz, sampling rate is 25.6 MHz, OSR is 64. Ideal modulator is then designed and simulated in MATLAB, getting SNR 125dB. Non-ideal factors are also added to ideal model, DWA technology is adopted to restrain the nonlinearity of multi-bit quantizer, getting SNR 104dB. Finally, transistor-level full-difference modulator is designed and simulated in Cadence, fetting SNR 101.3dB.

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6

Guo, Min, Hong Hui Deng, Bo Wen Ding, and Yong Sheng Yin. "Design of a Second-Order Sigma-Delta Modulator." Applied Mechanics and Materials 644-650 (September 2014): 3797–801. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3797.

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A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

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7

Qian, Ying Qi, Chang Chun Zhang, Zhong Chao Liu, Lei Lei Liu, Yu Rong Luan, Yu Ming Fang, and Yu Feng Guo. "A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology." Applied Mechanics and Materials 519-520 (February 2014): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1085.

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Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

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8

Zhai, Huishan, and Bingo Wing-Kuen Ling. "Implementation and Performance Evaluation of the Frequency-Domain-Based Bit Flipping Controller for Stabilizing the Single-Bit High-Order Interpolative Sigma Delta Modulators." Applied Sciences 10, no. 17 (August 21, 2020): 5785. http://dx.doi.org/10.3390/app10175785.

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This paper is an extension of the existing works on the frequency-domain-based bit flipping control strategy for stabilizing the single-bit high-order interpolative sigma delta modulator. In particular, this paper proposes the implementation and performs the performance evaluation of the control strategy. For the implementation, a frequency detector is used to detect the resonance frequencies of the input sequence of the sigma delta modulator. Then, a neural-network-based controller is used for finding the solution of the integer programming problem. Finally, the buffers and the combinational logic gates as well as an inverter are used for implementing the proposed control strategy. For the performance evaluation, the stability region in terms of the input dynamical range is evaluated. It is found that the control strategy can significantly increase the input dynamical range from 0.24 to 0.58. Besides, the control strategy can be applied to a wider class of the input signals compared to the clipping method.

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9

Huang, Fu Xiang, Zhi Qiang Gao, and Xiao Wei Liu. "Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope." Key Engineering Materials 645-646 (May 2015): 548–54. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.548.

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Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

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10

Li, Haolin, Laurens Breyne, Joris Van Kerrebrouck, Michiel Verplaetse, Chia-Yi Wu, Piet Demeester, and Guy Torfs. "A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 3 (March 2019): 482–86. http://dx.doi.org/10.1109/tcsii.2018.2855962.

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11

Li, Hongyi, Yuan Wang, Song Jia, and Xing Zhang. "Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM." IEICE Electronics Express 8, no. 24 (2011): 2041–47. http://dx.doi.org/10.1587/elex.8.2041.

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12

Hatami, Safar, Mohamed Helaoui, Fadhel M. Ghannouchi, and Massoud Pedram. "Single-Bit Pseudoparallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for SDR Wireless Transmitters." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 4 (April 2014): 922–31. http://dx.doi.org/10.1109/tvlsi.2013.2256808.

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13

Li, Di, Chunlong Fei, Qidong Zhang, Yani Li, and Yintang Yang. "A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs." Journal of Circuits, Systems and Computers 29, no. 07 (September 11, 2019): 2050108. http://dx.doi.org/10.1142/s021812662050108x.

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A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

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14

Lee, Han-Ul, Shi Dai, Tai-Kyung Yoo, Keon Lee, Kwang-Sub Yoon, and Sang-Min Lee. "Design of a CMOS Single Bit 3rd Order Delta-Sigma Modulator with Switched Operational Amplifier." Journal of Korea Information and Communications Society 37, no. 8A (August 31, 2012): 712–19. http://dx.doi.org/10.7840/kics.2012.37a.8.712.

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15

Cao, Guiping, and Ning Dong. "An 18-bit sigma –delta switched-capacitor modulator using 4-order single-loop CIFB architecture." Journal of Semiconductors 41, no. 6 (June 2020): 062404. http://dx.doi.org/10.1088/1674-4926/41/6/062404.

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16

Cho, Young-Kyun, and Kwang Chun Lee. "Noninverting Buck–Boost DC–DC Converter Using a Duobinary-Encoded Single-Bit Delta-Sigma Modulator." IEEE Transactions on Power Electronics 35, no. 1 (January 2020): 484–95. http://dx.doi.org/10.1109/tpel.2019.2913404.

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17

Sadik, Amin Z., Zahir M. Hussain, Xinghuo Yu, and Peter O'Shea. "An approach for stability analysis of a single-bit high-order digital sigma-delta modulator." Digital Signal Processing 17, no. 6 (November 2007): 1040–54. http://dx.doi.org/10.1016/j.dsp.2006.11.007.

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18

Di, Xin-Peng, Wei-Ping Chen, Liang Yin, and Xiao-Wei Liu. "A 99.7-dB DR fourth-order sigma–delta modulator for digital gyroscope sensor." Modern Physics Letters B 31, no. 09 (March 30, 2017): 1750097. http://dx.doi.org/10.1142/s021798491750097x.

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A fourth-order single-loop 1-bit sigma–delta [Formula: see text] modulator for digital gyroscope sensor interface circuit is presented in this paper. The effects caused by mismatch between parasite capacitors at the input of the operational transconductance amplifier (OTA) and the nonlinear on-resistance of the CMOS switch are analyzed. The chopping technique is adopted to eliminate the flick noise in low frequency. The modulator is fabricated in a standard CMOS 0.5-[Formula: see text] process and the effective area is 2 mm2. The power dissipation is 9.66 mW when the voltage is 5 V. The tested results show that a 93.7-dB peak signal-to-noise-and-distortion ratio (SNDR) and a 99.7-dB dynamic range (DR) are achievable at the sample frequency of 500 kHz for 2 kHz bandwidth. The optimization of the switches used in the first integrator and the parasite capacity is proved to be effective in the design of modulator.

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19

Lee, Song, and Roh. "A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications." Electronics 8, no. 10 (September 26, 2019): 1093. http://dx.doi.org/10.3390/electronics8101093.

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This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

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20

Yu, Shiang-Hwua, and Ming-Hung Tseng. "Extending the Stable Input Range of a Single-Bit Sigma-Delta Modulator with a Saturation Element." Journal of Automation and Control Engineering 1, no. 1 (2013): 45–48. http://dx.doi.org/10.12720/joace.1.1.45-48.

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21

Tang, Fang, Amine Bermak, Amira Abbes, and Mohieddine Amor Benammar. "Continuous-TimeΣΔADC with Implicit Variable Gain Amplifier for CMOS Image Sensor." Scientific World Journal 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/208540.

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This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

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22

Lee, Shuenn-Yuh, and Jia-Hua Hong. "A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator." International Journal of Software Science and Computational Intelligence 4, no. 4 (October 2012): 51–69. http://dx.doi.org/10.4018/jssci.2012100104.

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An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

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23

Sabouhi, Vahid, Esmaeil Najafi Aghdam, and Saeed Saeedi. "A single-bit continuous-time delta-sigma modulator using clock-jitter and inter-symbol-interference suppression technique." International Journal of Circuit Theory and Applications 45, no. 1 (May 19, 2016): 63–82. http://dx.doi.org/10.1002/cta.2224.

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24

Tao, Yonghong, Libin Yao, and Yong Lian. "A 1-V, 82-dB, 2.5-MS/s, single loop, single bit delta-sigma modulator in 0.13-μm CMOS technology." Analog Integrated Circuits and Signal Processing 71, no. 2 (August 6, 2011): 171–78. http://dx.doi.org/10.1007/s10470-011-9725-3.

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25

Karthaus, Udo, Stephan Ahles, Ahmed Elmaghraby, and Horst Wagner. "A 2-bit, 3.1 GS/s, band-pass DSM receiver for active antenna systems." International Journal of Microwave and Wireless Technologies 5, no. 3 (April 23, 2013): 329–34. http://dx.doi.org/10.1017/s1759078713000305.

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This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. It also provides an introduction to active antenna systems (AAS) for cellular infrastructure base stations, which is the target application for this RF integrated circuit (IC). The internal quantizer and feedback digital to analog converter (DAC) resolution of the CT BP DSM is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching being utilized, measured performance parameters include an SNR and SNDR in 35 MHz bandwidth of 56.7 and 53.7 dB, respectively. IIP3 and noise figure are −6.6 dBm and 10 dB, respectively. No image reception is noticeable within a measurement dynamic range of 83 dB. When driven by single-carrier and three-carrier W-CDMA signals, adjacent channel leakage ratio (ACLR) is −62.6 and −52.1 dB, respectively, making the design also suitable as a modulator for a class-S power amplifier.

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26

FEELY, ORLA, and LEON O. CHUA. "NONLINEAR DYNAMICS OF A CLASS OF ANALOG-TO-DIGITAL CONVERTERS." International Journal of Bifurcation and Chaos 02, no. 02 (June 1992): 325–40. http://dx.doi.org/10.1142/s021812749200032x.

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Oversampled sigma-delta modulators are finding widespread use in audio and other signal processing applications, due to their simple structure and robustness to circuit imperfections. Exact analyses of the system are complicated by the presence of a discontinuous nonlinear element—a one-bit quantizer. In this paper, we study the dynamics of the one-dimensional mapping which models the behavior of the single-loop modulator. This mapping has a discontinuity at the origin and constant slope at all other points. With slope one, the dynamics in the region of interest reduce to those of the rotation of the circle. With slope less than one, almost all system inputs give rise to globally asymptotically stable periodic orbits. We emphasize the case with slope greater than one, and explain the structure of the resultant bifurcation diagram. A symbolic dynamics based study allows us to explain the self-similarity of the dynamics and the nature of chaos in the system.

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27

Balagopal, Sakkarapani, Kehan Zhu, Xinyu Wu, and Vishal Saxena. "Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time $$\Delta \Sigma$$ Δ Σ modulator with 15 MHz bandwidth and 60 dB dynamic range." Analog Integrated Circuits and Signal Processing 90, no. 3 (September 16, 2016): 625–38. http://dx.doi.org/10.1007/s10470-016-0865-3.

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28

Brigati, S., F. Francesconi, P. Malcovati, and F. Maloberti. "A Fourth-Order Single-Bit Switched-Capacitor<tex>$Sigma$</tex>–<tex>$Delta$</tex>Modulator for Distributed Sensor Applications." IEEE Transactions on Instrumentation and Measurement 53, no. 2 (April 2004): 266–70. http://dx.doi.org/10.1109/tim.2003.822480.

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29

Su, Shiyu, and Mike Shuo-Wei Chen. "A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <−67-dBc IM3 Within DC to 6-GHz Tunable Passbands." IEEE Journal of Solid-State Circuits 53, no. 12 (December 2018): 3517–27. http://dx.doi.org/10.1109/jssc.2018.2871143.

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30

Memon, Tayab, Paul Beckett, and Amin Z. Sadik. "Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA." ISRN Electronics 2012 (November 14, 2012): 1–10. http://dx.doi.org/10.5402/2012/538597.

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In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs, synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based area-performance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system. This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in terms of area, power, and performance.

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31

Dunn, C., and M. Sandler. "Efficient linearisation of sigma-delta modulators using single-bit dither." Electronics Letters 31, no. 12 (June 8, 1995): 941–42. http://dx.doi.org/10.1049/el:19950687.

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32

Schreier, R. "An empirical study of high-order single-bit delta-sigma modulators." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40, no. 8 (1993): 461–66. http://dx.doi.org/10.1109/82.242348.

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33

Leslie, T. C., and B. Singh. "Sigma-delta modulators with multibit quantising elements and single-bit feedback." IEE Proceedings G Circuits, Devices and Systems 139, no. 3 (1992): 356. http://dx.doi.org/10.1049/ip-g-2.1992.0058.

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34

Deokhwan Hyun and G. Fischer. "Limit cycles and pattern noise in single-stage single-bit delta-sigma modulators." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 49, no. 5 (May 2002): 646–56. http://dx.doi.org/10.1109/tcsi.2002.1001954.

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35

Sotiriadis, Paul P. "Single-Bit All-Digital Frequency Synthesis Using Homodyne Sigma-Delta Modulation." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 64, no. 2 (February 2017): 463–74. http://dx.doi.org/10.1109/tuffc.2016.2615271.

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36

HO, CHARLOTTE YUK-FAN, BINGO WING-KUEN LING, JOSHUA D. REISS, and XINGHUO YU. "OCCURRENCE OF ELLIPTICAL FRACTAL PATTERNS IN MULTI-BIT BANDPASS SIGMA DELTA MODULATORS." International Journal of Bifurcation and Chaos 15, no. 10 (October 2005): 3377–80. http://dx.doi.org/10.1142/s0218127405013976.

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It has been established that the class of bandpass sigma delta modulators (SDMs) with single bit quantizers could exhibit state space dynamics represented by elliptic or fractal patterns confined within trapezoidal regions. In this letter, we find that elliptical fractal patterns may also occur in bandpass SDMs with multibit quantizers, even for the case when the saturation regions of the multibit quantizers are not activated and a large number of bits are used for the implementation of the quantizers. Moreover, the fractal pattern may occur for low bit quantizers, and the visual appearance of the phase portraits between the infinite state machine and the finite state machine with high bit quantizers is different. These phenomena are different from those previously reported for the digital filter with two's complement arithmetic. Furthermore, some interesting phenomena are found. A bit change of the quantizer can result in a dramatic change in the fractal patterns. When the trajectories of the corresponding linear systems converge to a fixed point, the regions of the elliptical fractal patterns diminish in size as the number of bits of the quantizers increases.

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37

Nam, Chang-Ho, and Sung-Woong Ra. "Performance and Jitter Effects Analysis of Single Bit Electro-Optical Sigma-Delta Modulators." Journal of Korean Institute of Electromagnetic Engineering and Science 23, no. 6 (June 30, 2012): 706–15. http://dx.doi.org/10.5515/kjkiees.2012.23.6.706.

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Yu, Shiang-Hwua, and Jwu-Sheng Hu. "Stability and Performance of Single-Bit Sigma-Delta Modulators Operated in Quasi-Sliding Mode." Circuits, Systems & Signal Processing 25, no. 5 (October 2006): 571–90. http://dx.doi.org/10.1007/s00034-004-1208-7.

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Shettigar, Pradeep, and Shanthi Pavan. "Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs." IEEE Journal of Solid-State Circuits 47, no. 12 (December 2012): 2865–79. http://dx.doi.org/10.1109/jssc.2012.2217871.

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Shiang-Hwua Yu. "Analysis and design of single-bit sigma-delta Modulators using the theory of sliding modes." IEEE Transactions on Control Systems Technology 14, no. 2 (March 2006): 336–45. http://dx.doi.org/10.1109/tcst.2005.863668.

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Hirata, Shinnosuke, Minoru K. Kurosawa, and Takashi Katagiri. "Sensor signal processing circuit for echolocation using a delta‐sigma modulated single‐bit digital signal." Journal of the Acoustical Society of America 120, no. 5 (November 2006): 3218. http://dx.doi.org/10.1121/1.4788171.

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42

Blythe, J. H. "Structure of round-off noise in single-bit second-order sigma-delta modulators with zero input." IEE Proceedings - Vision, Image, and Signal Processing 141, no. 2 (1994): 107. http://dx.doi.org/10.1049/ip-vis:19941016.

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Pamarti, Sudhakar, Jared Welz, and Ian Galton. "Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 3 (March 2007): 492–503. http://dx.doi.org/10.1109/tcsi.2006.887616.

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Bourdopoulos, G. I. "Adaptive Order Reduction Scheme for High-Order Single-Bit<tex>$ Delta Sigma $</tex>Modulators." IEEE Transactions on Circuits and Systems II: Express Briefs 51, no. 5 (May 2004): 213–16. http://dx.doi.org/10.1109/tcsii.2004.827549.

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Chen, Dongliang, Xiaowei Liu, Liang Yin, Yinhang Wang, Zhaohe Shi, and Guorui Zhang. "A ΣΔ Closed-Loop Interface for a MEMS Accelerometer with Digital Built-In Self-Test Function." Micromachines 9, no. 9 (September 6, 2018): 444. http://dx.doi.org/10.3390/mi9090444.

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Sigma-delta (ΣΔ) closed-loop operation is the best candidate for realizing the interface circuit of MEMS accelerometers. However, stability and reliability problems are still the main obstacles hindering its further development for high-end applications. In situ self-testing and calibration is an alternative way to solve these problems in the current process condition, and thus, has received a lot of attention in recent years. However, circuit methods for self-testing of ΣΔ closed-loop accelerometers are rarely reported. In this paper, we propose a fifth-order ΣΔ closed-loop interface for a capacitive MEMS accelerometer. The nonlinearity problem of the system is detailed discussed, the source of it is analyzed, and the solutions are given. Furthermore, a built-in self-test (BIST) unit is integrated on-chip for in situ self-testing of the loop distortion. In BIST mode, a digital electrostatic excitation is generated by an on-chip digital resonator, which is also ΣΔ modulated. By single-bit ΣΔ-modulation, the noise and linearity of excitation is effectively improved, and a higher detection level for distortion is easily achieved, as opposed to the physical excitation generated by the motion of laboratory equipment.

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Lahouli, Rihab, Manel Ben-Romdhane, Chiheb Rebai, and Dominique Dallet. "Mixed baseband architecture based on FBD ΣΔ–based ADC for multistandard receivers." ACTA IMEKO 4, no. 3 (September 27, 2015): 14. http://dx.doi.org/10.21014/acta_imeko.v4i3.258.

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<p>This paper presents the design and simulation results of a novel mixed baseband stage for a frequency band decomposition (FBD) analog-to-digital converter (ADC) in a multistandard receiver. The proposed FBD-based ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4<sup>th</sup> order single-bit Sigma-Delta modulators. The mixed baseband architecture uses a single non-programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that the proposed FBD architecture satisfies design specifications of the software defined radio (SDR) receiver. In this paper, the authors focus on the Butterworth AAF filter design for a multistandard receiver. Besides, theoretical analysis of the reconstruction stage for UMTS test case is discussed. It leads to a complicated system of equations and high digital filter orders. To reduce the digital reconstruction stage complexity, the authors propose an optimized digital reconstruction stage architecture design. The demodulation-based digital reconstruction stage using two decimation stages has been implemented using MATLAB/SIMULINK. Technical choices and performances are discussed. The computed signal-to-noise ratio (SNR) of the MATLAB/SIMULINK FBD ADC model is equal to at least 75 dB which satisfies the dynamic range required for UMTS signals. Next to hardware implementation with quantized filters coefficients, the authors implemented their proposition in VHDL in a SysGen environment. The measured SNR of the hardware implementation is equal to 74.08 dB which satisfies the required dynamic range of UMTS signals.</p>

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Bourdopoulos, G. I., A. G. Pnevmatikakis, and T. L. Deliyannis. "Numerical Method for Determining the Quantization Error PDF of Single-Bit<tex>$Sigma Delta$</tex>Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 4 (April 2004): 718–31. http://dx.doi.org/10.1109/tcsi.2004.826195.

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Memon, TD, and P. Beckett. "Stability analysis of a single-bit infinite impulse response sigma-delta modulator." Australian Journal of Electrical & Electronics Engineering 11, no. 1 (2014). http://dx.doi.org/10.7158/e12-076.2014.11.1.

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Ocampo-Hidalgo, Juan J., Javier Alducin-Castillo, and Jesus E. Molinar-Solis. "Processing Electrocardiographic Signals using a Custom Designed Sigma-Delta Modulator." Journal of Circuits, Systems and Computers, August 28, 2021, 2250040. http://dx.doi.org/10.1142/s0218126622500402.

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This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator’s output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66[Formula: see text]dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5[Formula: see text]V, exhibits a power consumption of 38[Formula: see text][Formula: see text]W, and uses a silicon area of 0.052[Formula: see text]mm2, it is suitable for single battery-operated systems on a chip.

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S., Vamsee Krishna, Sudhakara Reddy P., and Chandra Mohan Reddy S. "Single-loop sigma delta modulator design and verification for cognitive IoT applications." International Journal of Pervasive Computing and Communications ahead-of-print, ahead-of-print (July 27, 2020). http://dx.doi.org/10.1108/ijpcc-04-2020-0026.

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Purpose A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz. Design/methodology/approach This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications. Findings The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping. Originality/value This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

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