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Journal articles on the topic 'Simulation – Hardware – Software'

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Published: 29 June 2021
Last updated: 9 February 2022

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1

Wang, Shihao. "Software Simulation for Hardware/Software Co-Verification." Journal of Computer Research and Development 42, no. 3 (2005): 514. http://dx.doi.org/10.1360/crad20050322.

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2

Grierson, W. O. "Perspectives in Simulation Hardware and Software Architecture." Modeling, Identification and Control: A Norwegian Research Bulletin 6, no. 4 (1985): 249–55. http://dx.doi.org/10.4173/mic.1985.4.5.

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3

Milik, Adam, and Edward Hrynkiewicz. "Accelerated Co-Simulation of Hardware-Software System Based on Configurable Hardware Accelertor and Selective Simulation." IFAC Proceedings Volumes 36, no. 1 (February 2003): 31–36. http://dx.doi.org/10.1016/s1474-6670(17)33710-2.

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4

Grycel, Jacob, and Patrick Schaumont. "SimpliFI: Hardware Simulation of Embedded Software Fault Attacks." Cryptography 5, no. 2 (June 7, 2021): 15. http://dx.doi.org/10.3390/cryptography5020015.

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Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities. These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor microarchitecture. We present SimpliFI, a simulation methodology to test fault attacks on embedded software using a hardware simulation of the processor running the software. We explain the purpose and advantage of SimpliFI, describe automation of the simulation framework, and apply SimpliFI on a BRISC-V embedded processor running an AES application.
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5

Nahvi, M. "Design-oriented DSP courseware-hardware, software, and simulation." IEEE Signal Processing Magazine 9, no. 4 (October 1992): 30–35. http://dx.doi.org/10.1109/79.157328.

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6

Morris, D. "Simulating the Behaviour of Computer Systems: Co-simulation of Hardware/Software." Computer Journal 40, no. 10 (October 1, 1997): 617–29. http://dx.doi.org/10.1093/comjnl/40.10.617.

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7

AhmedAsifFuad, Kazi, and Shahriyar Masud Rizvi. "Hardware Software Co-Simulation of Canny Edge Detection Algorithm." International Journal of Computer Applications 122, no. 19 (July 18, 2015): 7–12. http://dx.doi.org/10.5120/21806-5124.

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8

Al-Haija, Qasem Abu, Hanan Al-Mubarak, and Abdulla Al-Humam. "Hardware Design and Software Simulation for Four Classical Cryptosystems." Procedia Computer Science 21 (2013): 500–505. http://dx.doi.org/10.1016/j.procs.2013.09.069.

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9

Vikram, K. N., and V. Vasudevan. "Hardware–software co-simulation of bus-based reconfigurable systems." Microprocessors and Microsystems 29, no. 4 (May 2005): 133–44. http://dx.doi.org/10.1016/j.micpro.2004.07.004.

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10

Olukotun, K. A., R. Helaihel, J. Levitt, and R. Ramirez. "A software-hardware cosynthesis approach to digital system simulation." IEEE Micro 14, no. 4 (August 1994): 48–58. http://dx.doi.org/10.1109/40.296157.

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11

Geng, Bo, and Qing Hua Cao. "Design and Realization of Simulation Environment of Embedded Software and Hardware Intergration Based on GEF." Advanced Materials Research 756-759 (September 2013): 2226–30. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.2226.

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Embedded software and hardware integration simulation platform is developed for simulating the embedded systems design process in current engineering system, which can facilitate finding various problems in system design process. For example, in the system scheme phase, the scheme and design verification are untimely and inadequate. In the early prototype phase, software development lags behind result in deferral of the overall progress of the system. And in the late prototype stage, the problem is lacking configuration item test environment. Embedded software and hardware integration simulation platform can provide verification of hardware and software integration and test development environment. Therefore, the quality of software development in embedded systems can be significantly improved and development cycle can be remarkably shortened by using this simulation platform.
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12

Ben Ayed, M., L. Zouari, and M. Abid. "Software In the Loop Simulation for Robot Manipulators." Engineering, Technology & Applied Science Research 7, no. 5 (October 19, 2017): 2017–21. http://dx.doi.org/10.48084/etasr.1285.

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In the last decades, the classical verification of robotic software component is postponed until the code is developed enough to function in real hardware. For this reason, the verification of code at early stages is essential to reduce development costs and necessary time for embedded systems such as robot manipulator. Therefore, Software In the Loop (SIL) simulation may be realized in the early stages of software development. It offers the possibility to execute tests before the hardware is available and thus detect errors. In this paper, we propose a Software In the Loop (SIL) test for robot manipulator driven by a Brushless DC Motor without a target system hardware. Simulation results prove the rapidity and the good performance of the developed code for the controller’s part by the validation of the behavior of robot manipulator software.
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13

Xu, Dong, Lei Zhang, Shan Ma, and Jin Xin Zhao. "Design of Semi Physical Simulation Platform for Autonomous Underwater Vehicle." Applied Mechanics and Materials 341-342 (July 2013): 1155–61. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.1155.

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To verify the system software logic of a newly designed autonomous underwater vehicle and the hardware architecture, data interface and reliability of the intelligent control system, the semi physical simulation platform was established by combining physical simulation of decision layer with virtual simulation of perception and behavior layer. The hardware and software architecture of the simulation platform were explained in detail. The virtual simulations of motion, sensors and physical simulation of intelligent control system were described. Finally, the obstacle avoidance simulation and long voyage simulation tests were conducted, and the platform is important for the success of sea experiments.
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14

Yang, Yi, Yong Jie Pang, and Lei Zhang. "Design of Semi Physical Simulation Platform for Autonomous Underwater Vehicle." Advanced Materials Research 765-767 (September 2013): 238–43. http://dx.doi.org/10.4028/www.scientific.net/amr.765-767.238.

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To verify the system software logic of a newly designed autonomous underwater vehicle and the hardware architecture, data interface and reliability of the intelligent control system, the semi physical simulation platform was established by combining physical simulation of decision layer with virtual simulation of perception and behavior layer. The hardware and software architecture of the simulation platform were explained in detail. The virtual simulations of motion, sensors and physical simulation of intelligent control system were described. Finally, the obstacle avoidance simulation and long voyage simulation tests were conducted, and the platform is important for the success of sea experiments.
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15

Teuben, Peter. "Simulation Software: Then, Now and Virtual Observatory." Symposium - International Astronomical Union 208 (2003): 359–68. http://dx.doi.org/10.1017/s0074180900207316.

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Like hardware, evolution of software has had a major impact on the field of particle simulations. This paper illustrates how simulation software has evolved, and where it can go. In addition, with the various ongoing Virtual Observatory efforts, producers of data should think more about sharing their data! Some examples are given of what we can do with our data and how to share it with our colleagues and observers. In the Appendix we summarize the findings of an informal data and software usage survey that we took during this conference.
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16

Holyaka, R. L., T. A. Marusenkova, and D. V. Fedasyuk. "LOGARITHMIC AMPLIFIERS FOR SOFTWARE HARDWARE MAGNETIC TRACKING SYSTEMS." ELECTRICAL AND COMPUTER SYSTEMS 33, no. 109 (December 22, 2020): 33–45. http://dx.doi.org/10.15276/eltecs.33.109.2020.4.

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The work deals with the problem of signal conversion in magnetic tracking devices. Magnetic tracking technology is based on computing the spatial position of an object being tracked upon measuring reference magnetic fields in low-frequency electromagnetic radiation spectrum. Magnetic tracking devices are key components of navigation sensors for virtual and augmented reality. It has been shown that the main problem one faces when developing sensory devices for magnetic tracking is the fact that signals should be measured in a wide measurement range. We have analyzed possible ways to solve the stated problem by digital and combined methods. The latter have proven to be more efficient. They consist in signal amplification due to analog compression, which is performed by logarithmic amplifiers whose negative feedback circuits contain components with non-linear volt-ampere characteristics (typically, diodes or bipo- lar transistors are used). It has been shown that the parameters of logarithmic signal compression can be controlled by modified circuits with auxiliary resistance dividers. The resistance dividers scale the logarithmic volt-ampere characteristics of emitter p-n junctions of bipolar n-p-n and p-n-p transistors. A substantial advantage of circuits with resistance dividers is that they provide the possibility to expand the range of the output voltage of logarithmic amplifiers and optimize the transition between the linear and logarithmic amplification regions. The work presents the results of simulation and experimental investigations into a logarithmic amplifier for a magnetic tracking system. Simulation was carried out using SPICE (Simulation Program with Integrated Circuit Emphasis) models. We applied an integrated approach,which provides collections of transient characteristics of logarithmic amplifiers at different sets of the parameters of resistance dividers. The simulation results have been verified using our own software- firmware magnetic tracking tools – Magnetic Tracking System Integrated Development Environment. The signal converter was built upon a programmable system-on-chip PSoC 5LP by Cypress Semiconductor.
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17

Júnior, José, Alisson Brito, and Tiago Nascimento. "Verification of Embedded System Designs through Hardware-Software Co-Simulation." International Journal of Information and Electronics Engineering 5, no. 1 (2015): 68–73. http://dx.doi.org/10.7763/ijiee.2015.v5.504.

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18

Qi, Dan, Mo Chen, Shaozhen Zhang, Dan Cheng, and Jun Mu. "Software and hardware co-simulation verification platform for navigation SoC." Journal of Physics: Conference Series 1735 (January 2021): 012010. http://dx.doi.org/10.1088/1742-6596/1735/1/012010.

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19

Díaz, Edel, Raúl Mateos, Emilio J. Bueno, and Rubén Nieto. "Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms." Electronics 10, no. 6 (March 23, 2021): 759. http://dx.doi.org/10.3390/electronics10060759.

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Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.
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20

Zhang,, Huisheng, Ming Su, and, and Shilie Weng. "Hardware-in-the-Loop Simulation Study on the Fuel Control Strategy of a Gas Turbine Engine." Journal of Engineering for Gas Turbines and Power 127, no. 3 (June 24, 2005): 693–95. http://dx.doi.org/10.1115/1.1805012.

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A hardware-in-the-loop simulation of a three-shaft gas turbine engine for ship propulsion was established. This system is composed of computers, actual hardware, measuring instruments, interfaces between actual hardware and computers, and a network for communication, as well as the relevant software, including mathematical models of the gas turbine engine. “Hardware-in-the-loop” and “volume inertia effects” are the two innovative features of this simulation system. In comparison to traditional methods for gas turbine simulation, the new simulation platform can be implemented in real time and also can test the physical hardware’s performance through their integration with the mathematical simulation model. A fuel control strategy for a three-shaft gas turbine engine, which can meet the requirement to the acceleration time and not exceeding surge line, was developed using this platform.
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21

Koschmieder, Lukas, Ralph Altenfeld, Janin Eiken, Bernd Böttger, and Georg J. Schmitz. "Cloud-Based ICME Software Training." Education Sciences 11, no. 1 (December 24, 2020): 5. http://dx.doi.org/10.3390/educsci11010005.

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Hands-on type training of Integrated Computational Materials Engineering (ICME) is characterized by assisted application and combination of multiple simulation software tools and data. In this paper, we present recent experiences in establishing a cloud-based infrastructure to enable remote use of dedicated commercial and open access simulation tools during an interactive online training event. In the first part, we summarize the hardware and software requirements and illustrate how these have been met using cloud hardware services, a simulation platform environment, a suitable communication channel, common workspaces, and more. The second part of the article focuses (i) on the requirements for suitable online hands-on training material and (ii) on details of some of the approaches taken. Eventually, the practical experiences gained during three consecutive online training courses held in September 2020 with 35 nominal participants each, are discussed in detail.
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22

Agrawal, P., and W. J. Dally. "A hardware logic simulation system." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 1 (1990): 19–29. http://dx.doi.org/10.1109/43.45853.

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23

Eder, Johannes, Sebastian Voss, Andreas Bayha, Alexandru Ipatiov, and Maged Khalil. "Hardware architecture exploration: automatic exploration of distributed automotive hardware architectures." Software and Systems Modeling 19, no. 4 (March 12, 2020): 911–34. http://dx.doi.org/10.1007/s10270-020-00786-6.

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24

Mekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.

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Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.
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25

Zhang, Qian. "GMSK Modulation Design in General Hardware-in-the-Loop Communication Simulator." Applied Mechanics and Materials 182-183 (June 2012): 602–5. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.602.

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Hardware-in-the-loop communication equipment simulation is an important step of the development about communications and electromagnetic environment simulation. Reference to the "software radio" design thinking, the source library is generated by the software and different communication signals are generated by the fixed hardware frame. The system achieves “versatility”. GMSK in wireless communications has been widely applied. It is one of the important signals generated by the simulator. Based on analysis of the structure, the paper introduces the design of the simulator. It also provides the software simulation of Matlab. It provides a reference simulation for communications equipment and electromagnetic environment simulation.
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26

Kamkin, A. S., and M. M. Chupilko. "Survey of modern technologies of simulation-based verification of hardware." Programming and Computer Software 37, no. 3 (May 2011): 147–52. http://dx.doi.org/10.1134/s0361768811030017.

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27

Simard, Stéphane, Rachid Beguenane, and Jean-Gabriel Mailloux. "Performance Evaluation of Rotor Flux-Oriented Control on FPGA for Advanced AC Drives." Journal of Robotics and Mechatronics 21, no. 1 (February 20, 2009): 113–20. http://dx.doi.org/10.20965/jrm.2009.p0113.

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Hardware implementation of mechatronic systems become more and more feasible with the constant development of simulation software tools and more performing computer hardware. The work presented here explains the use of Matlab/Simulink and Xilinx System Generator tools and FPGA hardware in designing, simulating and evaluating control laws for mechatronic systems. Particularly, this paper reports improved results for FPGA implementation and hardware/software co-simulation of a rotor flux-oriented control loop for three-phase AC induction motors. On FPGA, the computation time achieved for the complete control loop proves to be short enough that many enhancements proposed in theory become possible, including the use of neural networks, matrix calculations, on-line monitoring, advanced control of PWM inverter-fed AC machines, and multiple hybrid controls, without affecting system performance or sacrificing precision.
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28

Renaud, S., J. Tomas, N. Lewis, Y. Bornat, A. Daouzli, M. Rudolph, A. Destexhe, and S. Saïghi. "PAX: A mixed hardware/software simulation platform for spiking neural networks." Neural Networks 23, no. 7 (September 2010): 905–16. http://dx.doi.org/10.1016/j.neunet.2010.02.006.

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29

M Prasad, Thotamsetty. "Hardware/Software Co-Simulation of BPSK Modulator Using Xilinx System Generator." IOSR Journal of Engineering 02, no. 10 (October 2012): 54–58. http://dx.doi.org/10.9790/3021-021015458.

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30

Deicke, Markus, Wolfram Hardt, and Marcus Martinus. "Simulation of Hardware Specific Components of ECU Software in Virtual Verification." ATZelektronik worldwide 7, no. 3 (June 2012): 52–55. http://dx.doi.org/10.1365/s38314-012-0096-z.

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31

Ryckbosch, Frederick, Stijn Polfliet, and Lieven Eeckhout. "Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware." IEEE Micro 30, no. 6 (November 2010): 46–56. http://dx.doi.org/10.1109/mm.2010.95.

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32

Franco, Nuno, Eduardo Alves, and Nuno P. Barradas. "Hardware and Software Improvements in the Hotbird." Materials Science Forum 514-516 (May 2006): 1678–81. http://dx.doi.org/10.4028/www.scientific.net/msf.514-516.1678.

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The Hotbird is a state of the art X-ray laboratory for advanced materials characterisation, installed at ITN since 1999. Several major improvements in its capabilities have been implemented. On the one hand, new hardware developments have extended the applications that can be studied and on the other hand, new software has enabled both enhanced automated control of the system, and improved data analysis that leads to extraction of further precise information from the data. One improvement was the implementation of the x-ray reflectometry (XRR) technique, which is a major expansion of the Hotbird capabilities. XRR is well-suited to characterise film thickness and roughness with high resolution. Furthermore, several optics improvements, such as a Göbel mirror and monochromators were introduced. The combination of this optics allows one to use either a higher intensity beam (orders of magnitude better) or a higher resolution beam configuration. A new high-temperature chamber was developed, which allows one to perform in-situ experiments with excellent temperature control up to 800 °C, in all possible configurations. Data simulation/fitting analysis software for XRR was developed. Also, to control the diffractometer and perform experiments, a new user-friendly software package was developed. In order to illustrate the Hotbird capabilities improvements, several experimental examples will be described.
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33

Wójcikowski, Marek. "Transmission Protocol Simulation Framework For The Resource-Constrained Wireless Sensor Network." Metrology and Measurement Systems 22, no. 2 (June 1, 2015): 221–28. http://dx.doi.org/10.1515/mms-2015-0019.

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Abstract In this paper a prototype framework for simulation of wireless sensor network and its protocols are presented. The framework simulates operation of a sensor network with data transmission, which enables simultaneous development of the sensor network software, its hardware and the protocols for wireless data transmission. An advantage of using the framework is converging simulation with the real software. Instead of creating a model of the sensor network node, the same software is used in real sensor network nodes and in the simulation framework. Operation of the framework is illustrated with examples of simulations of selected transactions in the sensor network.
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34

Yu, Haiwang, Zhihua Dong, Kyle Knoepfel, Meifeng Lin, Brett Viren, and Kwangmin Yu. "Evaluation of Portable Acceleration Solutions for LArTPC Simulation Using Wire-Cell Toolkit." EPJ Web of Conferences 251 (2021): 03032. http://dx.doi.org/10.1051/epjconf/202125103032.

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The Liquid Argon Time Projection Chamber (LArTPC) technology plays an essential role in many current and future neutrino experiments. Accurate and fast simulation is critical to developing efficient analysis algorithms and precise physics model projections. The speed of simulation becomes more important as Deep Learning algorithms are getting more widely used in LArTPC analysis and their training requires a large simulated dataset. Heterogeneous computing is an efficient way to delegate computationally intensive tasks to specialized hardware. However, as the landscape of compute accelerators quickly evolves, it becomes increasingly difficult to manually adapt the code to the latest hardware or software environments. A solution which is portable to multiple hardware architectures without substantially compromising performance would thus be very beneficial, especially for long-term projects such as the LArTPC simulations. In search of a portable, scalable and maintainable software solution for LArTPC simulations, we have started to explore high-level portable programming frameworks that support several hardware backends. In this paper, we present our experience porting the LArTPC simulation code in the Wire-Cell Toolkit to NVIDIA GPUs, first with the CUDA programming model and then with a portable library called Kokkos. Preliminary performance results on NVIDIA V100 GPUs and multi-core CPUs are presented, followed by a discussion of the factors affiecting the performance and plans for future improvements.
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35

Herzog, Ulrich, and Jerry Rolia. "Performance validation tools for software/hardware systems." Performance Evaluation 45, no. 2-3 (July 2001): 125–46. http://dx.doi.org/10.1016/s0166-5316(01)00032-3.

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36

Talanov, M. V., and V. M. Talanov. "Software and hardware solution for digital signal processing algorithms testing." E3S Web of Conferences 124 (2019): 03006. http://dx.doi.org/10.1051/e3sconf/201912403006.

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The article describes the microprocessor system for various digital signal processing algorithms testing. The development of electric drive control systems is carried out with the usage of modeling systems such as, MATLAB/Simulink. Modern digital control systems are based on specialized digital signal microcontrollers. The present market offers evaluation boards, for example STM32F4DISCOVERY, which enables to connect a microcontroller to a personal computer. It makes possible to use the microcontroller as a part of the mathematical model of the control system. However, the designing of the control system simulation model and the program for the microprocessor is carried out in different programming environments. Thus, the software and hardware solution for testing programs for the microprocessor, which is a part of the control system, is relevant. This article deals with the designing of the modeling method in which the prototype program for the microprocessor is debugged as a part of the electric drive control system simulation model.
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37

Wojtowicz, Konrad, Wiesław Sobieraj, and Bartosz Brzozowski. "Simulation Method of UAV Avionics System Designing." Solid State Phenomena 198 (March 2013): 238–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.198.238.

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Avionics system software development is a sophisticated process depended on not fully specified factors. Therefore, essential steps in the development process are tests and verification. In this aim the virtual environment was constructed and prepared for the tests with the target software and the hardware to eliminate hardware defects and software bugs before first flight. The concept of virtual environment was established and developed after unsuccessful flights with long term prepared aircraft models. There was assumed that modelling methods applied separately to frame, engine and control system were not sufficient. There was requirement for complex simulation platform prepared to test whole aircraft in various environment conditions. In the first step the designing process was identified and milestones were placed inside (Fig. 1)
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38

Andalibi, Vafa, Henri Hokkanen, and Simo Vanni. "Controlling Complexity of Cerebral Cortex Simulations—I: CxSystem, a Flexible Cortical Simulation Framework." Neural Computation 31, no. 6 (June 2019): 1048–65. http://dx.doi.org/10.1162/neco_a_01120.

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Simulation of the cerebral cortex requires a combination of extensive domain-specific knowledge and efficient software. However, when the complexity of the biological system is combined with that of the software, the likelihood of coding errors increases, which slows model adjustments. Moreover, few life scientists are familiar with software engineering and would benefit from simplicity in form of a high-level abstraction of the biological model. Our primary aim was to build a scalable cortical simulation framework for personal computers. We isolated an adjustable part of the domain-specific knowledge from the software. Next, we designed a framework that reads the model parameters from comma-separated value files and creates the necessary code for Brian2 model simulation. This separation allows rapid exploration of complex cortical circuits while decreasing the likelihood of coding errors and automatically using efficient hardware devices. Next, we tested the system on a simplified version of the neocortical microcircuit proposed by Markram and colleagues ( 2015 ). Our results indicate that the framework can efficiently perform simulations using Python, C[Formula: see text], and GPU devices. The most efficient device varied with computer hardware and the duration and scale of the simulated system. The speed of Brian2 was retained despite an overlying layer of software. However, the Python and C[Formula: see text] devices inherited the single core limitation of Brian2. The CxSystem framework supports exploration of complex models on personal computers and thus has the potential to facilitate research on cortical networks and systems.
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Xiong, Chun Ru, and Fu Zhen Xie. "Application about Proteus Simulation on SCM Teaching." Applied Mechanics and Materials 556-562 (May 2014): 6496–99. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.6496.

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Principles and applications of electricity are involved in an important professional foundation courses. MCU development capabilities, including hardware design and software programming skills are basic capacity. This paper introduces an application of Proteus simulation on SCM teaching. Proteus breaks the space limitations of traditional training room with time and space constraints. The use of spare time, as long as there is a computer in a place, it can be single-chip hardware design and software programming exercises for students to improve SCM integrated development capability, practical spirit, the spirit of innovation culture to build a convenient and flexible platform.
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Zhao, Xiao Hua, Chen Chen, and Jian Rong. "Evaluation of Signal Control Strategy Based on Hardware-in-the-Loop." Applied Mechanics and Materials 505-506 (January 2014): 1122–26. http://dx.doi.org/10.4028/www.scientific.net/amm.505-506.1122.

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To evaluate the performance of different signal control strategies in intersection, based on the Hardware-In-The-Loop (HITL) simulation technology, a HITL system was established to perform experiment. In the system, microscopic traffic simulation software VISSIM created a virtual environment, in which the traffic flow can be controlled by the real signal controller. One type of intersection and four degrees of traffic volume were designed in the simulation program and three control strategies were set in the signal controller. Twelve simulations were performed in the system. The analysis of travel time and queuing length indicates that different strategies has remarkable influence on travel time, but no significant effect on queuing length.
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41

Zhang, Tao, Changfu Yang, and Xin Zhao. "Using Improved Brainstorm Optimization Algorithm for Hardware/Software Partitioning." Applied Sciences 9, no. 5 (February 28, 2019): 866. http://dx.doi.org/10.3390/app9050866.

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Today, more and more complex tasks are emerging. To finish these tasks within a reasonable time, using the complex embedded system which has multiple processing units is necessary. Hardware/software partitioning is one of the key technologies in designing complex embedded systems, it is usually taken as an optimization problem and be solved with different optimization methods. Among the optimization methods, swarm intelligent (SI) algorithms are easily applied and have the advantages of strong robustness and excellent global search ability. Due to the high complexity of hardware/software partitioning problems, the SI algorithms are ideal methods to solve the problems. In this paper, a new SI algorithm, called brainstorm optimization (BSO), is applied to hardware/software partitioning. In order to improve the performance of the BSO, we analyzed its optimization process when solving the hardware/software partitioning problem and found the disadvantages in terms of the clustering method and the updating strategy. Then we proposed the improved brainstorm optimization (IBSO) which ameliorated the original clustering method by setting the cluster points and improved the updating strategy by decreasing the number of updated individuals in each iteration. Based on the simulation methods which are usually used to evaluate the performance of the hardware/software partitioning algorithms, we generated eight benchmarks which represent tasks with different scales to test the performance of IBSO, BSO, four original heuristic algorithms and two improved BSO. Simulation results show that the IBSO algorithm can achieve the solutions with the highest quality within the shortest running time among these algorithms.
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42

Shanmugam, Ramalingam. "Software and hardware reliability books are reviewed." Journal of Statistical Computation and Simulation 79, no. 12 (October 27, 2009): 1491–95. http://dx.doi.org/10.1080/00949650802288981.

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43

Takasaki, S., T. Sasaki, N. Nomizu, N. Koike, and K. Ohmori. "Block-Level Hardware Logic Simulation Machine." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 1 (January 1987): 46–54. http://dx.doi.org/10.1109/tcad.1987.1270245.

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44

Brzozowski, Bartosz, Wiesław Sobieraj, and Konrad Wojtowicz. "UAV Avionics System Software Development Using Simulation Method." Solid State Phenomena 198 (March 2013): 260–65. http://dx.doi.org/10.4028/www.scientific.net/ssp.198.260.

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During last few years avionics system research platform was invented at the Military University of Technology. This modular simulator allows user to design and verify avionics system software using hardware-in-the-loop technique. Mathematical model of an airplane under tests is implemented on a high-performance computer which response to all control signals and environmental disturbances. Environment is simulated on a separate computer which can also visualize orientation and movement of the airplane. Plane structure and aerodynamic features as well as control data can be modified accordingly to user needs. The third PC is used as an interface unit between research platform and main computational unit of the avionics system. This device can send and receive information in real-time using various data protocols and interfaces depending on sensors and actuators that are planned to be used in real system. Those three computers work in a local area network and exchange data using Gigabit Ethernet standard. Possibility to simulate behavior of an UAV controlled by the developed avionics system implemented on an embedded computer working in hardware-in-the-loop mode on the platform, allows software developer to debug any part of the application in various environment conditions very close to reality. Research platform gives also the possibility to modify algorithm and adjust its parameters in real-time to verify suitability of the implemented avionics system software for the particular UAV. The avionics system software developed using this simulation method minimize expensive in-flight tests and assure failsafe performance after first successful flight
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45

Yin, Jiao, Hu Liu, Jun Wang, and Ke Li. "Control System Design of Pneumatic Conveying in Sand/Dust Environment Simulation Test." Applied Mechanics and Materials 442 (October 2013): 424–29. http://dx.doi.org/10.4028/www.scientific.net/amm.442.424.

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This paper focuses on the design of pneumatic conveying control system, including the design of both hardware and software part. The hardware part is mainly about building a test bed. Under certain wind conditions, by controlling the rotary feed valve to achieve the control of sand/dust concentration. The software part is to make the use of LabVIEW to develop a screen display program, which can achieve real-time data acquisition and control. The paper consists of three parts, the pneumatic control system hardware design, the pneumatic conveying control system software design and then Origin is used to linear fit the wind speed parameters collected back.
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46

Saldaña, Manuel, Emanuel Ramalho, and Paul Chow. "A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems." International Journal of Reconfigurable Computing 2009 (2009): 1–9. http://dx.doi.org/10.1155/2009/376232.

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High-performance reconfigurable computers (HPRCs) provide a mix of standard processors and FPGAs to collectively accelerate applications. This introduces new design challenges, such as the need for portable programming models across HPRCs and system-level verification tools. To address the need for cosimulating a complete heterogeneous application using both software and hardware in an HPRC, we have created a tool called the Message-passing Simulation Framework (MSF). We have used it to simulate and develop an interface enabling an MPI-based approach to exchange data between X86 processors and hardware engines inside FPGAs. The MSF can also be used as an application development tool that enables multiple FPGAs in simulation to exchange messages amongst themselves and with X86 processors. As an example, we simulate a LINPACK benchmark hardware core using an Intel-FSB-Xilinx-FPGA platform to quickly prototype the hardware, to test the communications. and to verify the benchmark results.
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47

Vikas, Basankar, Dr S. P. Metkar, Manoj Mane, and Bhuvaneshwar Kanade. "Integration of Application Code Simulations for Data exchange." Journal of University of Shanghai for Science and Technology 23, no. 07 (July 13, 2021): 659–66. http://dx.doi.org/10.51201/jusst/21/07189.

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In every product development industry, automation plays a key role in increasing the throughput of the company and providing better planning in product development and improved product quality. It is very necessary to find a solution to interdependencies during the product development process. During simulation-based analysis of a product, it is required that the need for actual hardware of the product is to be eliminated. Because of this, the functionality of the actual hardware can be analyzed by using software using simulations. If simulations of different products are running, the data is to be exchanged between different simulations effectively. It can be considered as simulating data exchange, as it is implemented in the hardware form. A proper and suitable method is to be used to have this goal achieved. This paper will address the integration approach for application code simulations or programs that are built to perform specific tasks.
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48

Nikodem, Maciej, and Krzysztof Kȩpa. "Hardware Accelerated Simulation of Crest Factor Reduction Block for Mobile Telecommunications." International Journal of Electronics and Telecommunications 58, no. 4 (December 1, 2012): 363–68. http://dx.doi.org/10.2478/v10177-012-0050-2.

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Abstract This paper reports results of the hardware accelerated simulations of the crest factor reduction (CFR) block which is a common element of the radio signal processing path in base stations for mobile telecommunications. Presented approach increases productivity of radio system architects by shortening the time of model architecture evaluation. This enables unprecedented scale of CFR parameter optimization which requires thousands of simulation runs. We use FPGA device and Xilinx System Generator for DSP technology in order to model CFR block in MATLAB/Simulink environment, implement the accelerator and use it for mixed hardware-software simulation. Reported approach reduces simulation time by 70%, provides straightforward use of fixed-point arithmetic and lowers power consumption by 73% at the cost of constant and relatively low overhead on model development.
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Uma, S., and P. Sakthivel. "Hardware Evaluation and Software Framework Construction for Performance Measurement of Embedded Processor." Journal of Computational and Theoretical Nanoscience 15, no. 2 (February 1, 2018): 586–94. http://dx.doi.org/10.1166/jctn.2018.7126.

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A frame work for analysing the capabilities and area of improvements for working of an embedded processor is constructed, and also a methodology for comparative study of simulation of processor on load and hardware results are explained in this paper. The processor can be modelled as a standalone processor or as a group of processors working together to take parallel program execution mode. The proposed frame work and simulation method uses the processor representation of current embedded processor model which is relevant in product design and devices modelling. This system utilizes the ARM processor model which consists of programs used for computing and standardizing the operational quality of a processor for any particular domain of applications. This paper presents steps for creating experimental framework which uses a simulation system running on a Linux based operating system along with kernel for running test applications on the target which is run in simulation mode. To evaluate the simulation with respect to the real hardware, this paper has made an observation of cache related performance of a typical embedded processor. The processor which is taken for the study is ARM926EJ-S processor. The future architectural components will be designed and simulated in the framework as continuation of this experiment. Their ARM9 technology equivalent design parameters for configurable modules of CPU in 1.8 micro-meter and experimental nano-meter level implementation would be calculated with architecture component design tools.
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Wu, Jigang, Thambipillai Srikanthan, and Ting Lei. "Efficient heuristic algorithms for path-based hardware/software partitioning." Mathematical and Computer Modelling 51, no. 7-8 (April 2010): 974–84. http://dx.doi.org/10.1016/j.mcm.2009.08.029.

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