Academic literature on the topic 'Silicon Nanoarrays'

We present the fabrication of large-scale two-dimensional periodic silicon nanoarrays using nanosphere lithography. The techniques start from a monolayer of self-assembled polystyrene (PS) spheres of 220 nm in diameter on water surface, which works as a mask to fabricate large-scale periodic silicon nanoarrays by direct plasmatherm reactive ion (RIE) etching. AFM images of the nanoarrays show that the patterns of PS templates are well transferred to the Si surface. The tips stand 50–80 nm high and the lateral size is around 150 nm. The optimum fabrication conditions can be chosen via the analysis of the experimental data.

This work describes the growth of silicon–silicon carbide nanoparticles (Si–SiC) and their self-assembly into worm-like 1D hybrid nanostructures at the interface of graphene oxide/silicon wafer (GO/Si) under Ar atmosphere at 1000 °C. Depending on GO film thickness, spread silicon nanoparticles apparently develop on GO layers, or GO-embedded Si–SiC nanoparticles self-assembled into some-micrometers-long worm-like nanowires. It was found that the nanoarrays show that carbon–silicon-based nanowires (CSNW) are standing on the Si wafer. It was assumed that Si nanoparticles originated from melted Si at the Si wafer surface and GO-induced nucleation. Additionally, a mechanism for the formation of CSNW is proposed.

Silicon carbide (SiC) nanostructure is a type of promising field emitter due to high breakdown field strength, high thermal conductivity, low electron affinity, and high electron mobility. However, the fabrication of the SiC nanotips array is difficult due to its chemical inertness. Here we report a simple, industry-familiar reactive ion etching to fabricate well-aligned, vertically orientated SiC nanoarrays on 4H-SiC wafers. The as-synthesized nanoarrays had tapered base angles >60°, and were vertically oriented with a high packing density >107 mm−2 and high-aspect ratios of approximately 35. As a result of its high geometry uniformity—5% length variation and 10% diameter variation, the field emitter array showed typical turn-on fields of 4.3 V μm−1 and a high field-enhancement factor of ~1260. The 8 h current emission stability displayed a mean current fluctuation of 1.9 ± 1%, revealing excellent current emission stability. The as-synthesized emitters demonstrate competitive emission performance that highlights their potential in a variety of vacuum electronics applications. This study provides a new route to realizing scalable field electron emitter production.

Human mesenchymal stem cells (hMSCs) respond to the characteristics of their surrounding microenvironment, i.e., their extracellular matrix (ECM). The possibility of mimicking the ECM offers the opportunity to elicit specific cell behaviors. The control of surface properties of a biomaterial at the scale level of the components of the ECM has the potential to effectively modulate cell response. Ordered nanoscale silicon pillar arrays were fabricated using reverse micelles of block copolymers on full wafers, with standard deviations lower than 15%. Bioactive synthetic peptides were covalently grafted on nanoarrays to evaluate possible synergies between chemistry and topography on osteogenic differentiation of hMSCs. Functionalization with RGD (Arg-Gly-Asp) and BMP-2 (bone morphogenetic protein-2) mimetic peptides lead to an enhancement of osteogenic differentiation. Bare nanopillar arrays of reduced pitch were found to promote faster hMSC differentiation. These findings highlight the relevance of investigating possibilities of engineering in vitro systems which can be fine-tuned according to the envisaged cell response.

Due to their extraordinary abilities to manipulate light propagation at the nanoscale, dielectric resonators that generate electric and magnetic Mie resonances for minimal optical loss have recently attracted great interest. Based on an all-dielectric metasurface, made of H-type silicon nanoarrays, this study proposed and constructed a visible-wavelength-range color filter, with high-quality Mie resonance and the ability to synthesize new colors. Using the finite-difference time-domain (FDTD) approach, we can create a larger color gamut by modifying the H-type array’s structural properties. The all-dielectric color filter suggested has a high color saturation and narrow bandwidth. The Mie resonance can be adjusted by manipulating the structural characteristics. By translating the reflectance spectrum into color coordinates and using the CIE1931 chromaticity diagram, a wide range of colors can be generated. This color filter offers a larger color range and saturation than other color filters. We produced color passband filters that span the visible spectrum using Mie resonator arrays, based on an H-type nanoresonator. This technology could have many applications, including high-resolution color printing, color-tunable switches, and sensing systems.

Complementary metal-oxide semiconductor (CMOS) technology has driven the electronic scenario for the last 40 years. The exponential grow of computing power implicates technological challenges, such as scaling transistor sizes, increasing clock frequency and reducing the power consumption. These goals raise dramatically the manufacturing cost with every new technology node. The projections of the ITRS roadmap report tell us that the scaling will be also influenced by fundamental physical limits. These observations have stimulated researchers from industry and academia to investigate possible feasible alternatives to CMOS technology. Since at the time of writing is difficult to find a clear winner, many possibilities are studied. They are based on different computational variables such as charge controlled (i.e. transistors) or magnetic field controlled devices. But, all of them have three aspects in common: i) the manufacturing process is still not mature, so they have to deal with a high defect rate; ii) the high density expected from these new devices arise problems related to the design automation field; iii) currently no tools, specifically targeted for emerging devices, are available on the market that allow researchers to investigate these technologies. In fact, it is rather difficult to find a toolchain of existing software able to provide a complete design flow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle emerging devices related constraints. This manuscript focuses on the development of a CAD tool for nanotechnologies, named ToPoliNano. It has the ability, starting from the VHDL description of the circuit, to automatically generate the physical layout choosing a target nanotechnology. At the time of writing two technologies are supported: silicon nanorrays and in-plane NanoMagnetic Logic. After the layout phase, the user can simulate the circuit behavior with an integrated simulation engine. In this work, three beyond CMOS technologies are investigated and analyzed from an architectural point of view. The first one is based on silicon nanoarrays, the last two come from the Quantum dot Cellular Automata (QCA) family, the in-plane Nano Magnetic Logic (iNML) and the perpendicular Nano Magnetic Logic (pNML). The aim of this thesis is to analyze the layout constrains of these emerging technologies making an architectural exploration. The investigation and the benchmarking is enabled thanks to ToPoliNano, which has been enriched, during my PhD, of a place and route engine and a fault injection mechanism to verify circuits robustness. These features implementation will be discussed more in detail respectively in part 2 and 1. After a brief technological background provided in the introduction, the thesis is divided in three main parts dedicated to the three technologies analyzed: silicon nanoarray, iNML and pNML. In part 1 the high defect rate of silicon nanoarray technology is discussed and analyzed in order to find a method to design more reliable circuits. A new methodology has been developed and tested through our CAD tool ToPoliNano. Fault tolerant circuits have been tested injecting different fault maps and evaluating the output error rate and yield. In part 2, the main working structure of the layout engine and the layout constraints of iNML technology are introduced. In part 2, first the main working principle and the layout constrains are presented to the reader. Then, a detailed description of the design flow implemented in ToPoliNano will be presented. The place and route engine implemented in ToPoliNano will be analyzed and described in detail with examples. The algorithms are compared and results are provided in the last part of this section. In the last part, the pNML technology will be analyzed. In particular, this work has been done in collaboration with the Lehrstuhl für Technische Elektronik (LTE) institute at the Technical University of Munich (TUM). Here, after a brief introduction about the up to date fabrication process, some experimental data are presented in order to extract useful information for developing a drawing tool. The idea is to design a drawing tool that enables the final user to design 3D pNML based circuits. The tool should embed data collected from experiments and it should able to automatically export the VHDL file that described the drawn architecture. In this way, the behavior and the correctness of the circuit can be verified using Modelsim simulator from Mentor Graphics. However, this part of the thesis in currently under development. Thus, only an overview of the whole flow will be provided.