Academic literature on the topic 'Silicon etching, self alignment, polymer deposition'

The aim of this study is to develop metallic nanodot arrays with controlled morphology and alignment. To produce gold nanodot arrays with high throughput, the authors propose a new efficient fabrication process based on the templated thermal dewetting method, using a nano-chemical stamping technique with a polymer mold. This process comprises four steps: sputter etching on a quartz glass substrate, patterning of micrometer size by printing with acetone on the substrate by stamping with a polymer film stamp, deposition of a thin Au film on the substrate, and self-organization of the metal nanodot arrays by thermal dewetting. A new method, using a cyclo-olefin polymer film mold for chemical patterning by nano-chemical stamping, was examined. Since the acetone stamped on the substrate reduces the surface energy and affects the contact angle of the gold nanodots, the gold nanodots are distributed along the stamped pattern. It is found that the pattern stamped with acetone on the substrate works as a template for the thermal dewetting process. The nano-chemical stamping technique is useful in controlling the size and distribution of the nanodots.

A new fabrication process of metal nanodot arrays using the thermal dewetting method was developed in this study. This process was comprised of three steps: thin Au film deposition on a quartz glass substrate, groove patterning by direct nanoimprinting, and self-organization of metal nanodot arrays by thermal dewetting. A new idea to utilize a polymer film mold for groove patterning by direct nanoimprinting was examined. The polymer film mold was prepared by hot-embossing groove patterns of a mother mold on a cyclo olefin polymer (COP) film. The mother mold was prepared from a silicon wafer. The polymer film mold was used for direct nanoimprinting on a metal film deposited on a quartz substrate. The experimental results revealed that the COP film mold can effectively form a micro groove pattern on the Au film despite the COP film mold being softer than the Au film. The micro groove on the Au film was also found to be effective in aligning the nanodots in lines. The micro groove patterning using the COP film mold was also confirmed to be useful in controlling the dot size and alignment during the thermal dewetting process.

ABSTRACTOptical waveguides are being explored for on-chip purposes to overcome the speed limitations of electrical interconnects. Passive optical components like waveguides and vertical outcouplers are important components in such schemes. In this study we fabricate planar waveguides with integrated vertical micro-mirrors using standard Back End of the Line silicon (BEOL) CMOS based processes. Around 1.6 μm of a hybrid alkoxy siloxane polymer with a refractive index of ∼ 1.50 at the intended wavelength of 830 nm is used as the core and plasma deposited silicon oxide with a refractive index of ∼ 1.46 is used as the cladding. The angular face in the polymer waveguide that would function as the mirror surface was fabricated by a pattern transfer method which involves transferring the angle in a template to the waveguide using anisotropic reactive ion etching. The sidewall angle realized in a positive resist on patterning was used as the angle template. Exposure and development conditions were adjusted for Shipley® S1813 photoresist to generate a sidewall angle of ∼ 65°. The anisotropic Reactive Ion Etching (RIE) was done using a CF4/O2 plasma chemistry. A gas composition of 50/50 CF4/O2 was chosen in order to minimize the etch related roughness of the polymer and the photoresist. The metallization of the mirror faces was done using a self-aligned maskless technique which ensures metal deposition only on the angular face and also eliminates a lithography step.

AbstractSilicon carbide is a semiconductor with desirable material properties, such as a wide bandgap and high thermal conductivity. It is an excellent material for constructing power switching devices operating in harsh environments where conventional semiconductors cannot adequately perform. One example of such a power device is a bipolar junction transistor (BJT). While the potential of the SiC BJT is recognized, appropriate techniques for producing devices is lacking due to its difficulty.For example, in order to achieve a high voltage 4H-SiC BJT switch with nanosecond switching time, the device must have a low base resistance. The simulation results indicate that for an emitter width of 2.0 μm and a base width of 1.2 μm the distance between the two should be 0.4 μm or less to meet the requirement for base resistance. To produce the above-described geometries and spacing, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. For this purpose, we developed a novel self-aligned process for SiC BJT devices, that enables the fabrication of the design with high yield, as standard silicon self-aligned technique are not applicable.The newly developed process starts with the deposition of the emitter contact metal, which provides the metal mask for the etching of the emitter ridges. Next, the wafer is planarized with photoresist and etched, so that only the emitter contacts are exposed. Electroless plating is then used to enlarge the contacts, and after removal of the resist, the plating provides an overhang, suitable for lift-off of the base contact metal. After the base contact metal deposition, the structure is planarized and etched, this time with a silicon dioxide layer, again exposing the plated emitter contacts and the lift-off step is the wet etching of the plated metal. The emitters are then all connected with a blanket wiring level, which also forms the base contact pad. This process is simpler and more robust than the process we developed to date. The main difference is the inclusion of a sacrificial lift-off overhang, created by electroless plating. It enables a well controlled overhang independent of steepness of the SiC ridge profile and the height of the emitter mesa. We successfully fabricated the overhang structure on 4H-SiC substrates.In conclusion, we report the demonstration of a new self-aligned process, which provides a self-aligned emitter contact, a self-aligned base contact and eliminates the need for via holes smaller than the emitter stripe widths. We consider this new process a major improvement over existing processes to fabricate SiC BJT devices.

AbstractBlock copolymers (BCPs) consist of two or more chemically distinct and incompatible polymer chains (or blocks) covalently bonded. Due to the incompatibility and connectivity constraints between the two blocks, diblock copolymers spontaneously self-assemble into microphase-separated nanoscale domains that exhibit ordered 0, 1, 2 or 3 dimensional morphologies at equilibrium. Commonly observed microdomain morphologies in bulk samples are periodic arrangements of lamellae, cylinders, or spheres. Block copolymer lithography refers to the use of these ordered structures in the form of thin films as templates for patterning through selective etching or deposition. The self-assembly and domain orientation of block copolymers on a given substrate is critical to realize block copolymer lithography as a tool for large throughput nanolithography applications. In this work, we survey the morphology of cylinder-forming block copolymers by atomic force microscopy (AFM). Three kind of block copolymers were studied: a) poly(styrene-block-ferrocenyldimethylsilane), PS-b-PFS b) poly(styrene-block-methylmethacrylate), PS-b-PMMA and c) poly(styrene-block-dimethylsiloxane) PS-b-PDMS. Block copolymers were dissolved in a neutral solvent for both blocks (toluene) in order to obtain solutions of various concentrations (1 and 1.5 wt %). From these solutions, films were prepared by spin casting on ultrananocrystalline diamond (UNCD) thin film substrates. Results indicate that PS-b-PFS exhibits chemical and morphological compatibility to the UNCD surface in terms of wetting and domain control. A systematic comparison of self-assembly of these polymers on silicon nitride substrates demonstrates that UNCD thin films would require pre-treatment to be considered as a substrate for BCP lithography.

The aim of this work was the development of a method for the generation of surface features on n-type silicon samples with deeply buried p-implants, in the form of heterogeneities aligned directly above the buried implants. This task was motivated by the realisation of a simpler process for the formation of superjunction transistors, which currently require the repeated creation of the same implantation structure over multiple steps of photolithography These lithography steps can be potentially replaced, if a suitable process for the self-alignment in accordance to the buried implants can be found. The work on this goal was separated into three parts: the analysis of samples for suitable surface properties, the generation of surface heterogeneities using such a property and the analysis of the mechanism for the used process of contrast generation. Within this doctoral thesis, a before unseen method of selective etching on silicon was discovered and investigated. Hence, the overall aim of this work was successfully achieved. • Samples containing buried p-implants inside a n-type silicon substrate were characterised with regard to various properties. Of these, the through-sample resistance showed a significant variation in accordance to the buried implants also through a homogeneous epitaxial layer. • Various methods aimed at the usage of the resistance variation in order to generate a surface heterogeneity through electrodeposition failed to enable a suitable process. Instead, another method was found, which enables the replication of the implant structure via selective etching. This novel process enables the lithography free patterning of the substrates through a simple alkaline etch process performed under illumination. This results in a surface heterogeneity as an alteration of the sample topography combined with a material contrast due to the formation of an in-situ SiO2 etch mask. This material variation can also be used for the selective deposition of polymers, enabling further processing of the etched samples. • For this new method, named Light Induced Selective Etching (LISE), a mechanism underlying the selectivity was proposed and through a number of experiments. In essence, the illumination during the etching process produces a flux of photogenerated electrons directed from the buried implants toward the surface, which increase the negative surface charge in the areas above these implants. The locally increased surface charge causes a local protection of the native silicon oxide layer against the alkaline etching, leading to the structuring of the substrate. In essence, this novel method allows for the previously unreported self-adjusted structuring of silicon based on deeply buried implant structures. In general, even the characterisation of such implant structures is difficult, whereas this method allows for structuring with regard to such buried structures with a very simple setup of only an etchant solution and a suitable light source. With regard to the introduction and motivation of this thesis, this process can possibly be applied for the intended purpose of creating a self-aligned resist in order to replace repeating lithography steps. This is the case in particular in combination with polymer deposition, as shown in the last part of the results. Certain limitations, such as the resolution limit and dimensional size increase exist, but can be circumvented by appropriate device design and further optimisation of the process parameters. Furthermore, the LISE process appears applicable for the manufacturing of MEMS and MOEMS devices, as the typical feature sizes in these cases fit well to the achieved resolution of the LISE process. For devices needing a certain implant structure in combination with a corresponding topography, the new method allows for the elimination of at least one lithography step, including the necessary substeps such as alignment and measurement. Accordingly, LISE has the potential of simplifying the manufacturing process, enabling better and cheaper devices.