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Journal articles on the topic 'Sigma-Delta quantization'

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Published: 4 June 2021
Last updated: 11 February 2022

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1

He, N., F. Kuhlmann, and A. Buzo. "Multiloop sigma-delta quantization." IEEE Transactions on Information Theory 38, no. 3 (May 1992): 1015–28. http://dx.doi.org/10.1109/18.135642.

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2

Benedetto, J. J., A. M. Powell, and O. Yilmaz. "Sigma-delta (/spl Sigma//spl Delta/) quantization and finite frames." IEEE Transactions on Information Theory 52, no. 5 (May 2006): 1990–2005. http://dx.doi.org/10.1109/tit.2006.872849.

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3

Hirai, Yusaku, Shinya Yano, and Toshimasa Matsuoka. "A Delta-Sigma ADC with Stochastic Quantization." IPSJ Transactions on System LSI Design Methodology 8 (2015): 123–30. http://dx.doi.org/10.2197/ipsjtsldm.8.123.

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4

Sidor, Tadeusz. "METROLOGICAL PROPERTIES OF A/D CONVERTERS UTILIZING HIGHER ORDER SIGMA–DELTA MODULATORS COMPARED WITH A/D CONVERTERS WITH MODULATORS OF FIRST ORDER." Metrology and Measurement Systems 21, no. 1 (March 1, 2014): 37–46. http://dx.doi.org/10.2478/mms-2014-0004.

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Abstract Time domain analysis is used to determine whether A/D converters that employ higher order sigma-delta modulators, widely used in digital acoustic systems, have superior performance over classical synchronous A/D converters with modulators of first order when taking into account their important metrological property which is the magnitude of the quantization error. It is shown that the quantization errors of delta-sigma A/D converters with higher order modulators are exactly on the same level as for converters with a first order modulator.
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5

Zierhofer, C. M. "Adaptive sigma-delta modulation with one-bit quantization." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 5 (May 2000): 408–15. http://dx.doi.org/10.1109/82.842109.

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6

Ostergaard, Jan, and Ram Zamir. "Multiple-Description Coding by Dithered Delta–Sigma Quantization." IEEE Transactions on Information Theory 55, no. 10 (October 2009): 4661–75. http://dx.doi.org/10.1109/tit.2009.2027528.

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7

Güntürk, C. Si̇nan. "One-bit sigma-delta quantization with exponential accuracy." Communications on Pure and Applied Mathematics 56, no. 11 (July 10, 2003): 1608–30. http://dx.doi.org/10.1002/cpa.3044.

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8

Lv, Bing Jun, Peng Fei Wang, Dong Bo Wang, Jun'an Liu, and Xiao Wei Liu. "A High-Performance Closed-Loop Fourth-Order Sigma-Delta Micro-Machined Accelerometer." Key Engineering Materials 503 (February 2012): 134–38. http://dx.doi.org/10.4028/www.scientific.net/kem.503.134.

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In this paper a high-performance closed-loop fourth-order sigma-delta (ΣΔ) micro-accelerometer is presented. After a introduction of sigma-delta accelerometer, system-level analysis and design of a fourth-order sigma-delta micro-accelerometer is given. The simulation result shows that an accelerometer with 107dB signal to noise ratio (SNR) and 17.5 bits effective number of bits (ENOB) is achieved. Through the root locus analysis, it is got that accelerometer is stable when quantization gain is bigger than 0.262. The accelerometer gets a good linearity and it becomes overload when input signal level is greater than -5dBFS.
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9

Callegari, Sergio, Federico Bizzarri, and Angelo Brambilla. "Optimal Coefficient Quantization in Optimal-NTF $\Delta \!\Sigma $ Modulators." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 5 (May 2018): 542–46. http://dx.doi.org/10.1109/tcsii.2018.2821368.

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10

De Maeyer, Jeroen, Pieter Rombouts, and Ludo Weyten. "Efficient Multibit Quantization in Continuous-Time $\Sigma \Delta$ Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 4 (April 2007): 757–67. http://dx.doi.org/10.1109/tcsi.2007.890607.

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11

Bodmann, Bernhard G., and Vern I. Paulsen. "Frame paths and error bounds for sigma–delta quantization." Applied and Computational Harmonic Analysis 22, no. 2 (March 2007): 176–97. http://dx.doi.org/10.1016/j.acha.2006.05.010.

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12

Blum, James, Mark Lammers, Alexander M. Powell, and Özgür Yılmaz. "Sobolev Duals in Frame Theory and Sigma-Delta Quantization." Journal of Fourier Analysis and Applications 16, no. 3 (October 15, 2009): 365–81. http://dx.doi.org/10.1007/s00041-009-9105-x.

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13

Wang, Yang. "Sigma–delta quantization errors and the traveling salesman problem." Advances in Computational Mathematics 28, no. 2 (March 28, 2007): 101–18. http://dx.doi.org/10.1007/s10444-006-9016-1.

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14

Zorn, C., T. Brückner, M. Ortmanns, and W. Mathis. "State scaling of continuous-time sigma-delta modulators." Advances in Radio Science 11 (July 4, 2013): 119–23. http://dx.doi.org/10.5194/ars-11-119-2013.

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Abstract. In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the maximum out-of-band gain directly in continuous time. In addition, the input amplitude distribution between each quantization level of multi bit sigma-delta modulator can be adapted.
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15

Li, Bin, Xiang Ning Fan, and Wei Wei Zhu. "A Long Sequence Length, Reduced Complexity MASH 1-1-1 DDSM for Fractional-N Frequency Synthesizer." Applied Mechanics and Materials 130-134 (October 2011): 4286–90. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.4286.

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In this paper, a long sequence length, reduced complexity MASH 1-1-1 digital delta-sigma modulator (DDSM) suitable for fractional-N frequency synthesizer applications is presented. Good shaping of quantization noise is achieved by using the state of art MASH structure for a digital third-order delta-sigma modulator, meanwhile, the hardware required for this modulator is considerably reduced by recoding all carry output signal from accumulators. The functional operation of the modulator is confirmed by simulation.
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16

Park, Sungkyung, and Chester Sungchung Park. "Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators." Journal of Circuits, Systems and Computers 25, no. 11 (August 14, 2016): 1650131. http://dx.doi.org/10.1142/s0218126616501310.

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All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.
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17

Sahu, Anil Kumar, Vivek Kumar Chandra, and G. R. Sinha. "Analysis of Quantization Noise and Power Estimation of Continuous-Time Delta Sigma Analog-to-Digital Converter Using Test Enable Feature For 4G Radios." International Journal of Informatics and Communication Technology (IJ-ICT) 7, no. 2 (August 1, 2018): 82. http://dx.doi.org/10.11591/ijict.v7i2.pp82-88.

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<span>This paper presents a novel approach for completely test enable feature and low-voltage delta– sigma analog-to-digital (A/D) converters for cutting edge wireless applications. Oversampling feature of ADCs and DACs is enough to meet the requirement related to in-band and adjacent channel leakage ratio (ACLR) execution of 3G/4G portable radio. The quantization noise which is not filtered in ADC is addressed. We have achieved work power-optimization and test enable feature of oversampling ADC is uses in design and simulation so that the problem of quantization error in continues time sigma delta ADC is solved. This paper suggests support to designer for selecting appropriate topologies with various channel arrangements, number of bits and oversampling issues. A test enable feature of CT A/D is presented introducing the test signal generation (TSG) and the COrdinate Rotation Digital Computer (CORDIC) for evaluating the performance of ADC. This helps in addressing the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta–sigma modulator ADC for 4G radios is studied</span><span lang="IN">.</span>
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18

Liu, Yun-Tao, Ying Wang, and Lei Shao. "Quantization noise consideration and characterization in Sigma-Delta MEMS accelerometer." Microelectronics Journal 47 (January 2016): 53–60. http://dx.doi.org/10.1016/j.mejo.2015.10.020.

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19

Galton, I. "Granular quantization noise in the first-order delta-sigma modulator." IEEE Transactions on Information Theory 39, no. 6 (1993): 1944–56. http://dx.doi.org/10.1109/18.265502.

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20

Galton, I. "Granular quantization noise in a class of delta-sigma modulators." IEEE Transactions on Information Theory 40, no. 3 (May 1994): 848–59. http://dx.doi.org/10.1109/18.335895.

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21

Benedetto, John J., Alexander M. Powell, and Özgür Yılmaz. "Second-order Sigma–Delta (ΣΔ) quantization of finite frame expansions." Applied and Computational Harmonic Analysis 20, no. 1 (January 2006): 126–48. http://dx.doi.org/10.1016/j.acha.2005.04.003.

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22

Ziquan, Tong, Yang Shaojun, Jiang Yueming, and Dou Naiying. "The Design of a Multi-bit Quantization Sigma-delta Modulator." International Journal of Signal Processing, Image Processing and Pattern Recognition 6, no. 5 (October 31, 2013): 265–74. http://dx.doi.org/10.14257/ijsip.2013.6.5.24.

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23

Lin, Kung-Ching. "Analysis of Decimation on Finite Frames with Sigma-Delta Quantization." Constructive Approximation 50, no. 3 (September 12, 2019): 507–42. http://dx.doi.org/10.1007/s00365-019-09480-3.

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24

Wang, Rongrong. "Sigma Delta Quantization with Harmonic Frames and Partial Fourier Ensembles." Journal of Fourier Analysis and Applications 24, no. 6 (December 1, 2017): 1460–90. http://dx.doi.org/10.1007/s00041-017-9582-2.

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25

Bodmann, Bernhard G., Vern I. Paulsen, and Soha A. Abdulbaki. "Smooth Frame-Path Termination for Higher Order Sigma-Delta Quantization." Journal of Fourier Analysis and Applications 13, no. 3 (June 2007): 285–307. http://dx.doi.org/10.1007/s00041-006-6032-y.

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26

Gao, Zhen, Felix Krahmer, and Alexander M. Powell. "High-order low-bit Sigma-Delta quantization for fusion frames." Analysis and Applications 19, no. 01 (October 19, 2020): 1–20. http://dx.doi.org/10.1142/s0219530520400096.

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We construct high-order low-bit Sigma-Delta [Formula: see text] quantizers for the vector-valued setting of fusion frames. We prove that these [Formula: see text] quantizers can be stably implemented to quantize fusion frame measurements on subspaces [Formula: see text] using [Formula: see text] bits per measurement. Signal reconstruction is performed using a version of Sobolev duals for fusion frames, and numerical experiments are given to validate the overall performance.
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27

Liu, Wen Yan, Bin Zhang, Long Chen, Chao Gao, and Xiao Wei Liu. "A High-Performance Mash Fourth-Order Sigma-Delta Modulator." Key Engineering Materials 503 (February 2012): 207–10. http://dx.doi.org/10.4028/www.scientific.net/kem.503.207.

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This paper reports on a system level design and analysis of a mash fourth-order sigma-delta (ΣΔ) modulator. Compared with a high-order single-loop ΣΔ modulator (ΣΔM), there’s no need to consider about the system stability of a mash ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 122.0 dB, and the effective number of bits (ENOB) is 19.97 bits when the over sampling ratio (OSR) is 128.
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28

Majd, Nasser Erfani, and Amin Aeenmehr. "Efficiency Improvement of Delta Sigma Modulator-Based Transmitter Using Complex Delta Sigma Modulator and Noise Reduction Loop." Journal of Circuits, Systems and Computers 29, no. 16 (July 18, 2020): 2050267. http://dx.doi.org/10.1142/s0218126620502679.

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This paper proposes an architecture to enhance coding efficiency (CE) of the Delta Sigma Modulator (DSM) transmitters. In this architecture, a complex–low pass delta sigma modulator (LPDSM) is used instead of existing Cartesian–LPDSM and polar–low pass envelope delta sigma modulator (LPEDSM). Simulation results show that for Uplink long-term evolution (LTE) signal with 1.92[Formula: see text]MHz bandwidth and 7.8-dB peak to average power ratio (PAPR), the CE for the complex–LPDSM-based transmitter is equal to 41.7% in compare to 9.7% CE for Cartesian–LPDSM transmitter. Also, due to the resolving of noise convolution problem, the complex–LPDSM-based transmitter baseband part needs lower oversampling ratio (OSR) and clock speed than polar–LPEDSM transmitter baseband part to achieve the same signal-to-noise and distortion ratio (SNDR). In the next step, a quantization noise reduction loop is implemented in this architecture. By using this technique for an Uplink LTE signal with 1.92[Formula: see text]MHz bandwidth, with the same PAPR and OSR of 16, the CE is improved from 41.7% to 56.1% with 40[Formula: see text]dB SNDR.
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29

Kwon, Sunwoo, and Franco Maloberti. "Comments on "Efficient multibit quantization in continuous-time Sigma Delta modulators"." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 1 (January 2009): 280. http://dx.doi.org/10.1109/tcsi.2008.926981.

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30

Gustavsson, Ulf, Thomas Eriksson, and Christian Fager. "Quantization Noise Minimization in $\Sigma\Delta$ Modulation Based RF Transmitter Architectures." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 12 (December 2010): 3082–91. http://dx.doi.org/10.1109/tcsi.2010.2052512.

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31

Gray, R. M., W. Chou, and P. W. Wong. "Quantization noise in single-loop sigma-delta modulation with sinusoidal inputs." IEEE Transactions on Communications 37, no. 9 (1989): 956–68. http://dx.doi.org/10.1109/26.35376.

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32

He, Lin, Yuncheng Zhang, Fang Long, Fengcheng Mei, Mingyuan Yu, Fujiang Lin, Libin Yao, and Xicheng Jiang. "Digital Noise-Coupling Technique for Delta–Sigma Modulators With Segmented Quantization." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 6 (June 2014): 403–7. http://dx.doi.org/10.1109/tcsii.2014.2319994.

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33

Cheng, Y., C. Petrie, B. Nordick, and D. Comer. "Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 9 (September 2006): 848–52. http://dx.doi.org/10.1109/tcsii.2006.881825.

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34

Colodro, F., A. Torralba, and J. L. Mora. "Digital Noise-Shaping of Residues in Dual-Quantization Sigma–Delta Modulators." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 51, no. 2 (February 2004): 225–32. http://dx.doi.org/10.1109/tcsi.2003.822408.

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35

Hsieh, H., and Chia-Liang Lin. "Spectral Shaping of Dithered Quantization Errors in Sigma–Delta Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 5 (May 2007): 974–80. http://dx.doi.org/10.1109/tcsi.2007.895511.

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36

Feng, Joe-Mei, and Felix Krahmer. "An RIP-Based Approach to $\Sigma \Delta $ Quantization for Compressed Sensing." IEEE Signal Processing Letters 21, no. 11 (November 2014): 1351–55. http://dx.doi.org/10.1109/lsp.2014.2336700.

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37

Ul Haq, Faizan, Mikko Englund, Kim B. Östman, Kari Stadius, Marko Kosunen, Kimmo Koli, and Jussi Ryynänen. "Quantization noise upconversion effects in mixer‐first direct delta‐sigma receivers." International Journal of Circuit Theory and Applications 47, no. 12 (November 3, 2019): 1893–906. http://dx.doi.org/10.1002/cta.2705.

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38

Bodmann, Bernhard G., and Stanley P. Lipshitz. "Randomly dithered quantization and sigma–delta noise shaping for finite frames." Applied and Computational Harmonic Analysis 25, no. 3 (November 2008): 367–80. http://dx.doi.org/10.1016/j.acha.2007.12.003.

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39

Iwen, Mark, and Rayan Saab. "Near-Optimal Encoding for Sigma-Delta Quantization of Finite Frame Expansions." Journal of Fourier Analysis and Applications 19, no. 6 (August 28, 2013): 1255–73. http://dx.doi.org/10.1007/s00041-013-9295-0.

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40

Blum, James, Mark Lammers, Alexander M. Powell, and Özgür Yılmaz. "Erratum to: Sobolev Duals in Frame Theory and Sigma-Delta Quantization." Journal of Fourier Analysis and Applications 16, no. 3 (February 19, 2010): 382. http://dx.doi.org/10.1007/s00041-010-9120-y.

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41

Chen, Dongliang, Liang Yin, Qiang Fu, Wenbo Zhang, Yihang Wang, Guorui Zhang, Yufeng Zhang, and Xiaowei Liu. "A Straightforward Approach for Synthesizing Electromechanical Sigma-Delta MEMS Accelerometers." Sensors 20, no. 1 (December 22, 2019): 91. http://dx.doi.org/10.3390/s20010091.

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The EM- Σ Δ (electromechanical sigma-delta) approach is a concise and efficient way to realize the digital interface for micro-electromechanical systems (MEMS) accelerometers. However, including a fixed MEMS element makes the synthesizing of the EM- Σ Δ loop an intricate problem. The loop parameters of EM- Σ Δ can not be directly mapped from existing electrical Σ Δ modulator, and the synthesizing problem relies an experience-dependent trail-and-error procedure. In this paper, we provide a new point of view to consider the EM- Σ Δ loop. The EM- Σ Δ loop is analyzed in detail from aspects of the signal loop, displacement modulation path and digital quantization loop. By taking a separate consideration of the signal loop and quantization noise loop, the design strategy is made clear and straightforward. On this basis, a discrete-time PID (proportional integral differential) loop compensator is introduced which enhances the in-band loop gain and suppresses the displacement modulation path, and hence, achieves better performance in system linearity and stability. A fifth-order EM- Σ Δ accelerometer system was designed and fabricated using 0.35 μ m CMOS-BCD technology. Based on proposed architecture and synthesizing procedure, the design effort was saved, and the in-band performance, linearity and stability were improved. A noise floor of 1 μ g / Hz , with a bandwidth 1 kHz and a dynamic range of 140 dB was achieved.
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42

Li, Yao Guang, Xiao Wei Liu, Yan Xiao, and Yun Tao Liu. "A High-Performance Fourth-Order Sigma-Delta Micromachined Accelerometer." Key Engineering Materials 483 (June 2011): 422–26. http://dx.doi.org/10.4028/www.scientific.net/kem.483.422.

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This paper reports on a system level design and analysis of a single-loop fourth-order sigma-delta (ΣΔ) accelerometer. Compared with a second-order single-loop ΣΔ modulator (ΣΔM) formed by the sensing element here the sensing element is cascaded with two extra electronic integrators to form the fourth ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 96.86 dB, and the effective number of bits (ENOB) is 15.8 bits when the over sampling ratio (OSR) is 128. Stability of the system is analyzed by root locus method based on the linear model established in this work, and the minimum gain of the quantizer Kq min is about 0.375.
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43

Yin, Y., H. Klar, and P. Wennekers. "A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator." Advances in Radio Science 3 (May 12, 2005): 277–80. http://dx.doi.org/10.5194/ars-3-277-2005.

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Abstract. A 14-b, 5-MHz output-rate cascaded 3-1 sigma-delta analog-to-digital converters (ADC) has been developed for broadband communication applications, and a novel 4th-order noise-shaping is obtained by using the proposed architecture. At a low oversampling ratio (OSR) of 8, the ADC achieves 91.5dB signal-to-quantization ratio (SQNR), in contrast to 71.8dB of traditional 2-1-1 cascaded sigma-delta ADC in 2.5-MHz bandwidth and over 80dB signal-to-noise and distortion (SINAD) even under assumptions of awful circuit non-idealities and opamp non-linearity. The proposed architecture can potentially operates at much more high frequencies with scaled IC technology, to expand the analog-to-digital conversion rate for high-resolution applications.
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44

Lagunas, Miguel A., Ana Perez-Neira, and José Rubio. "NDM: 1-Bit Delta-Sigma Converter with Non-Linear Loop." MATEC Web of Conferences 292 (2019): 04005. http://dx.doi.org/10.1051/matecconf/201929204005.

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In this paper we propose to introduce a new processing scheme in the basic loop of a Delta Sigma (ΔΣ) analog-to-digital converter. This processing confers extra gains of the converter over both the quantization error and the channel noise. This is an advance with respect to all cases found in the literature, where the desired signal is not protected against channel noise. Also, the proposed processing is simple and contrasts with the existing architectures, which produce better quality at the expense of sensitivity to implementation imperfections due to the presence of multiples loops in the corresponding architecture. Furthermore, the in-phase/quadrature components structure of a band pass signal has not been used to improve the performance of ΔΣ converters.
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45

Pamarti, S. "A Theoretical Study of the Quantization Noise in Split Delta–Sigma ADCs." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 5 (June 2008): 1267–78. http://dx.doi.org/10.1109/tcsi.2008.916554.

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46

Daubechies, Ingrid, and Rayan Saab. "A Deterministic Analysis of Decimation for Sigma-Delta Quantization of Bandlimited Functions." IEEE Signal Processing Letters 22, no. 11 (November 2015): 2093–96. http://dx.doi.org/10.1109/lsp.2015.2459758.

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47

Rangan, S., and B. Leung. "Quantization noise spectrum of double-loop sigma-delta converter with sinusoidal input." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 41, no. 2 (1994): 168–73. http://dx.doi.org/10.1109/82.281851.

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48

Deift, Percy, Felix Krahmer, and C. Sınan Güntürk. "An optimal family of exponentially accurate one-bit Sigma-Delta quantization schemes." Communications on Pure and Applied Mathematics 64, no. 7 (March 14, 2011): 883–919. http://dx.doi.org/10.1002/cpa.20367.

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49

Yu-Che Yang and Shey-Shi Lu. "A Quantization Noise Pushing Technique for $\Delta\Sigma$ Fractional-$N$ Frequency Synthesizers." IEEE Transactions on Microwave Theory and Techniques 56, no. 4 (April 2008): 817–25. http://dx.doi.org/10.1109/tmtt.2008.918166.

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50

Lammers, Mark, Alexander M. Powell, and Özgür Yılmaz. "Alternative dual frames for digital-to-analog conversion in sigma–delta quantization." Advances in Computational Mathematics 32, no. 1 (July 19, 2008): 73–102. http://dx.doi.org/10.1007/s10444-008-9088-1.

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