Dissertations / Theses: 'SiC power MOSFET'

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Linewih, Handoko, and h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET." Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.

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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

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2

Linewih, Handoko. "Design and Application of SiC Power MOSFET." Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.

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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
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3

Chen, Cheng. "Studies of SiC power devices potential in power electronics for avionic applications." Thesis, Université Paris-Saclay (ComUE), 2016. http://www.theses.fr/2016SACLN045.

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Mes travaux de thèse dans les laboratoires SATIE de ENS de Cachan et Ampère de l’INSA de Lyon se sont déroulés dans le cadre du projet Gestion OptiMisée de l'Energie (GENOME) pour étudier le potentiel de certains composants de puissance (JFET, MOSFET et BJT) en carbure de silicium (SiC) dans des convertisseurs électroniques de puissance dédiés à des applications aéronautiques suite au développement de l'avion plus électrique. La première partie de mes travaux étudie la robustesse de MOSFET et BJT en SiC soumis à des régimes de court circuit. Pour les MSOFET SiC, en soumettant ces transistors à la répétition de plusieurs courts-circuits, nous observons une évolution du courant de fuite de grille qui semble être un bon indicateur de vieillissement. Nous définissons une énergie critique répétitive pour évaluer la robustesse à la répétition de plusieurs courts-circuits. Aucun effet significatif de la température ambiante n’a pu être mis en évidence sur la robustesse des MOSFET et BJT SiC sous contraintes de court-circuit. Pour les MOSFET, nous avons également constaté une élévation significative du courant de fuite de grille en augmentant de 600V à 750V la tension, ce qui se traduit également par une défaillance plus rapide. Après ouverture des boîtiers des MOSFET Rohm ayant présenté un court-circuit entre grille et source après défaillance, on remarque une fusion de la métallisation de source qui vient effectivement court-circuiter grille et source. Dans ce mode de défaillance particulier, le court-circuit entre grille et source auto-protège la puce en lui permettant de s’ouvrir.La deuxième partie de ce mémoire est consacrée à l’étude de JFET, MSOFET et BJT SiC en régime d’avalanche. Les JFET de SemiSouth et les BJT de Fairchild présentent une bonne robustesse à l’avalanche. Mais le test d'avalanche révèle la fragilité du MOSFET Rohm puisqu’il entre en défaillance avant d’entrer en régime d’avalanche. La défaillance du MOSFET Rohm et sa faible robustesse en régime d’avalanche sont liées à l’activation du transistor bipolaire parasite. Le courant d'avalanche n’est qu’une très faible partie du courant dans l’inductance et circule du drain/collecteur à la grille/base pour maintenir le transistor en régime linéaire. Une résistance de grille de forte valeur diminue efficacement le courant d'avalanche à travers la jonction drain-grille pour le JFET.La troisième partie concerne l’étude de la commutation de BJT SiC à très haute fréquence de découpage. Nous avons dans un premier temps cherché à valider des mesures de pertes par commutation. Après avoir vérifié l'exactitude de la méthode électrique par rapport à une méthode calorimétrique simplifiée, nous montrons que la méthode électrique est adaptée à l’estimation des pertes de commutation mais nécessite beaucoup d’attention. En raison de mobilité élevée des porteurs de charge dans le SiC, nous montrons que le BJT SiC ne nécessite pas l’utilisation de diode d’anti-saturation. Enfin, aucune variation significative des pertes de commutation n’a pu être constatée sur une plage de température ambiante variant de 25°C à 200°C.La quatrième partie concentre l’étude du comportement de MOSFET SiC sous contraintes HTRB (High Temperature Reverse Bias) et dans une application diode-less dans laquelle les transistors conduisent un courant inverse à travers le canal, exception faite de la phase de temps mort pendant laquelle c’est la diode de structure qui assurera la continuité du courant dans la charge. Les résultats montrent que la diode interne ne présente aucune dégradation significative lors de la conduction inverse des MOSFET. Le MOSFET Cree testé montre une dérive de la tension de seuil et une dégradation de l’oxyde de grille qui sont plus significatives lors des essais dans l’application diode-less que sous des tests HTRB. La dérive de la tension de seuil est probablement due au champ électrique intense régnant dans l’oxyde et aux pièges de charge dans l'oxyde de grille
My PhD work in laboratories SATIE of ENS de Cachan and Ampère of INSA de Lyon is a part of project GEstioN OptiMisée de l’Energie (GENOME) to investigate the potential of some Silicon carbide (SiC) power devices (JFET, MOSFET and BJT) in power electronic converters dedicated to aeronautical applications for the development of more electric aircraft.The first part of my work investigates the robustness of MOSFET and SiC BJT subjected to short circuit. For SiC MOSFETs, under repetition of short-term short circuit, a gate leakage current seems to be an indicator of aging. We define repetitive critical energy to evaluate the robustness for repetition of short circuit. The effect of room temperature on the robustness of SiC MOSFET and BJT under short circuit stress is not evident. The capability of short circuit is not improved by reducing gate leakage current for MOSFET, while BJT shows a better robustness by limiting base current. For MSOFET, a significant increase in gate leakage current accelerates failure for DC voltage from 600V to 750V. After opening Rohm MOSFETs with a short circuit between gate and source after failure, the fusion of metallization is considered as the raison of failure. In this particular mode of failure, the short circuit between gate and source self-protects the chip and opens drain short current.The second part of the thesis is devoted to the study of SiC JFET, MSOFET and BJT in avalanche mode. The SemiSouth JFET and Fairchild BJT exhibit excellent robustness in the avalanche. On the contrary, the avalanche test reveals the fragility of Rohm MOSFET since it failed before entering avalanche mode. The failure of Rohm MOSFET and its low robustness in avalanche mode are related to the activation of parasitic bipolar transistor. The avalanche current is a very small part of the current in the inductor. It flows from the drain/collector to the gate/base to drive the transistor in linear mode. A high-value gate resistance effectively reduces the avalanche current through the drain-gate junction to the JFET.The third part of this thesis concerns the study of switching performance of SiC BJT at high switching frequency. We initially attempted to validate the switching loss measurements. After checking the accuracy of the electrical measurement compared to calorimetric measurement, electrical measurement is adopted for switching power losses but requires a lot of attention. Thanks to high carrier charge mobility of SiC material, SiC BJT does not require the use of anti-saturation diode. Finally, no significant variation in switching losses is observed over an ambient temperature range from 25°C to 200°C.The fourth part focuses on the study of SiC MOSFET behavior under HTB (High Temperature Reverse Bias) and in diode-less application in which the transistors conduct a reverse current through the channel, except for the dead time during which the body diode ensure the continuity of the current in the load. The results show that the body diode has no significant degradation when the reverse conduction of the MOSFET. Cree MOSFET under test shows a drift of the threshold voltage and a degradation of the gate oxide which are more significant during the tests in the diode-less application than under HTRB test. The drift of the threshold voltage is probably due to intense electric field in the oxide and the charge traps in the gate oxide

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Rajagopal, Narayanan. "Design of 1.7 kV SiC MOSFET Switching-Cells for Integrated Power Electronics Building Block (iPEBB)." Thesis, Virginia Tech, 2021. http://hdl.handle.net/10919/104148.

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The need for high-density power electronics converters becomes more critical by the day as energy consumption continues to grow across the world. Specifically, the need for medium-voltage (MV) high-density converters in power distribution systems, electric ships, and airplanes become more critical as weight and space becomes more a premium. The limited space and footprint require new packaging technologies and methods to develop an integrated power converter. The advancement of wide-bandgap (WBG) devices like silicon carbide (SiC) allows converters to have higher power and faster switching... To benefit from these devices, the packaging of the converter needs to be carefully considered. This thesis presents the design of a 250 kW integrated power electronics building block (iPEBB) for future electric system applications. This work explores the common substrate concept that would serve as the electrical, thermal, and mechanical foundation for the converter. State-of-the-art organic direct-bonded copper (ODBC) is explored to serve as the material foundation for the common substrate. Multi-domain simulations are used to design the integrated SiC bridges to achieve a power loop inductance of 3.5 nH, a maximum temperature of 175 °C, and a weight of 16 kg. ODBC and silicon nitride switching cells are packaged and analyzed in order to see the benefits on a multi-layer design as well as determining electrical and thermal trade-offs. The insights gained from hardware testing will help in the redesign and refinement of the iPEBB.
M.S.
This thesis presents the design of an integrated power electronics building block (iPEBB) for high-density systems. The PEBB concept allows for modular converters that can perform various power conversions. The design begins with exploring state-of-the-art substrates that will serve as the foundation for the iPEBB. Due to the integrated design, the substrate plays a vital role in the thermal, electrical, and mechanical performance, and contributes to the weight and reliability of the iPEBB. State-of-the-art organic direct-bonded copper (ODBC) substrates and multi-layer silicon nitride substrates are explored in this work. The ODBC is used to develop a common substrate for the converter, which allows for a high level of integration between different SiC half-bridges. Switching-cell prototypes based on the ODBC and multi-layer silicon nitride are fabricated to provide insight into the electrical and thermal performance of different substrates. This information will aid in the further redesign and refinement of the iPEBB concept.

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Soler, Victor. "Design and process developments towards an optimal 6.5 kV SiC power MOSFET." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/668916.

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A sustainable future requires efficient power electronic converters at any stage of the electrical energy consumption. Silicon carbide (SiC) is one of the most technologically advanced wide bandgap semiconductors that can outperform silicon limits for power devices. SiC power MOSFETs are of the greatest interest since they are unipolar gate-controlled switches with high blocking voltage capability and reasonably low specific on-resistance. The focus of this thesis is on the design optimisation and process technology refinement towards the improvement of high-voltage SiC MOSFETs. Previous developments in our group were taken as a reference for this work. The results of this research allowed the fabrication of large-area SiC power MOSFETs with voltage ranges targeting 1.7 kV up to 6.5 kV. The inherent properties of SiC entail challenging technological solutions to successfully integrate a power MOSFET of such high-voltage capability. To ensure suitable blocking capability, different planar edge termination structures have been designed, optimised by TCAD simulation and implemented on PiN diodes. The termination schemes considered are single-zone JTE, FGRs and a novel RA-JTE structure combining JTE with rings. RA-JTE design, with the lowest sensitivity to fabrication process deviations and a lower consumed area, achieved more than 90% of the ideal breakdown voltage and suitable blocking capability up to 6.5 kV. The optimisations performed on the unit-cell of the SiC power MOSFET target both the layout design and the fabrication process. The optimisation has been performed by TCAD modelling and experimental evaluation of specific test structures. Several techniques to improve the performance of the fabricated devices have been considered: i) the use of an offset retrograde p-body profile to provide an adequate Vth value while preventing p-body punch-through, ii) a submicronic self-aligned channel definition, iii) a boron treatment to the gate oxide to improve channel mobility, iv) a discrete location of the p-contact to reduce cell-pitch, v) the use of a lower-doped-source (LDS) to improve reliability, vi) the optimisation of the JFET area, and vii) the integration of gate runners to improve the switching performance. As a result of these investigations, a full mask-set were designed and used for processing wafers of several voltage-class in different batches. All the fabrication steps have been carried out at IMB-CNM cleanroom. The electrical characterisation of large-area devices has evidenced an optimal Vth in the range of 5 V, a proper gate control, and a good blocking capability. We obtained relatively high specific on-resistance due to the large cell pitch dimensions required by IMB-CNM cleanroom design rules as well as a still low channel mobility. Fabricated SiC MOSFETs are capable of switching at high bus voltages (tested up to 80% of the rated voltage). Although, their switching performance is limited by internal gate resistance. Fabricated devices have shown better short-circuit capability (>15 µs) than existing commercial devices, mainly due to the cell design considerations. The evaluation of electrical performance evidenced the successful functionality of the fabricated VDMOS up to 6.5 kV and validates our new RA-JTE termination design. On the other hand, the novel boron doping treatment to the gate oxide clearly demonstrated to improve the on-resistance of our devices in all voltage classes without affecting breakdown and short-circuit capabilities. Nevertheless, it strongly compromises stability and reliability at temperatures above 100 °C. These results show that the MOS interface quality is still the major issue for the development of reliable SiC power MOSFETs. Finally, alternative SiC structures have also been investigated to take advantage of the SiC superior material properties. These include a SiC IGBT showing conductivity modulation, and a preliminary SiC CMOS cell able to operate at high temperatures.
Un futur sostenible requereix convertidors electrònics d'alta potència eficients per totes les fases del consum d'energia elèctrica. El carbur de silici (SiC) és un dels semiconductors de banda prohibida ampla més avançats que permet superar els límits de silici en dispositius de potència. El gran interès en els MOSFETs de potència SiC recau en que són interruptors unipolars que presenten una alta capacitat de tensió de bloqueig i una resistència específica relativament baixa. L’objectiu d’aquesta tesi és la optimització del disseny i el perfeccionament de la tecnologia de processos per a la millora dels MOSFETs d’alta tensió SiC tenint com a referencia els desenvolupaments previs realitzats pel grup. Els resultats d'aquesta investigació han permès la fabricació de MOSFETs de potència de SiC d’àrea gran amb capacitat de bloqueig des de 1,7 kV fins a 6,5 kV. Les inherents propietats del SiC requereixen solucions tecnològiques específiques per a integrar amb èxit un MOSFET de potència de tensió tan elevada. Per garantir una bona capacitat de bloqueig, s'han dissenyat diferents estructures de terminació planars, optimitzades per simulació i implementades sobre díodes PiN. Els esquemes de terminació considerats son JTE mono-zona, FGR i una nova estructura RA-JTE que combina una JTE amb anells flotants. La terminació RA-JTE, amb una menor sensibilitat a desviacions del procés de fabricació i menor àrea consumida, ha aconseguit més del 90% de la tensió ideal i bona capacitat de bloqueig per dispositius de fins a 6,5 kV. Les millores realitzades a la cel·la del MOSFET de SiC afecten tant al disseny com al procés de fabricació. L’optimització de la cel·la bàsica s’ha realitzat mitjançant simulacions TCAD i l’avaluació de dades experimentals mesurades en estructures de test específiques. Les tècniques aplicades per a la millora del rendiment dels MOSFETs de SiC inclouen: i) l’ús d’un perfil de dopatge retrògrad pel pou p per obtenir un valor de Vth adequada alhora que s'evita el punch-through del pou p, ii) canal auto-alineat de longitud sub-micrònica, iii) un tractament de bor a l'òxid de la porta per millorar la interfície, iv) la ubicació discreta del contacte p per reduir les dimensions de la cel·la, v) una regió de font menys dopada (LDS) per millorar la fiabilitat, vi) l’optimització de l’àrea JFET i vii) la integració de corredors de porta per reduir el temps de commutació. Com a resultat d'aquestes investigacions, un joc complet de màscares s’ha dissenyat i utilitzat per processar oblies de diferents rangs de tensió. Tots els processos de fabricació s’han realitzat a la sala blanca de l’IMB-CNM. La caracterització elèctrica dels MOSFETs d’àrea gran mostra una Vth en el rang de 5 V, control de la porta i bona capacitat de bloqueig. No obstant, la resistència específica és relativament alta a causa de les dimensions de cel·la i la baixa mobilitat al canal. Els MOSFETS de SiC fabricats commuten a altes tensions de bus, però el temps de transició està limitat per la resistència interna de porta. Els dispositius fabricats presenten una capacitat de curtcircuit (>15 µs) superior als dispositius comercials, principalment gràcies al disseny de la cel·la. L’anàlisi del comportament elèctric valida el funcionament satisfactori dels MOSFETs de SiC fabricats fins a 6,5 kV així com també el disseny de terminació RA-JTE. El nou tractament de bor a l’òxid de porta ha demostrat reduir la resistència dels VDMOS fabricats en totes les classes de tensió sense afectar a la capacitat de bloqueig i de curt-circuit, però en compromet l'estabilitat i la fiabilitat a més de 100 °C. Aquests resultats mostren que la qualitat de la interfície continua sent el punt clau per al desenvolupament de MOSFETs de potència fiables en SiC. Finalment, també s’han investigat estructures alternatives en SiC. Destaca la integració d’un IGBT...

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Phankong, Nathabhat. "Characterization of SiC Power Transistors for Power Conversion Circuits Based on C-V Measurement." 京都大学 (Kyoto University), 2010. http://hdl.handle.net/2433/126807.

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DiMarino, Christina Marie. "High Temperature Characterization and Analysis of Silicon Carbide (SiC) Power Semiconductor Transistors." Thesis, Virginia Tech, 2014. http://hdl.handle.net/10919/78116.

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This thesis provides insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor transistors, including the MOSFET, BJT, SJT, and normally-on and normally-off JFETs. Both commercial and sample devices from the semiconductor industry's well-known manufacturers were evaluated in this study. These manufacturers include: Cree Inc., ROHM Semiconductor, General Electric, Fairchild Semiconductor, GeneSiC Semiconductor, Infineon Technologies, and SemiSouth Laboratories. To carry out this work, static characterization of each device was performed from 25 ºC to 200 ºC. Dynamic characterization was also conducted through double-pulse tests. Accordingly, this thesis describes the experimental setup used and the different measurements conducted, which comprise: threshold voltage, transconductance, current gain, specific on-resistance, parasitic capacitances, internal gate resistance, and the turn on and turn off switching times and energies. For the latter, the driving method used for each device is described in detail. Furthermore, for the devices that require on-state dc currents, driving losses are taken into consideration. While all of the SiC transistors characterized in this thesis demonstrated low specific on-resistances, the SiC BJT showed the lowest, with Fairchild's FSICBH057A120 SiC BJT having 3.6 mΩ•cm2 (using die area) at 25 ºC. However, the on-resistance of GE's SiC MOSFET proved to have the smallest temperature dependency, increasing by only 59 % from 25 ºC to 200 ºC. From the dynamic characterization, it was shown that Cree's C2M0080120D second generation SiC MOSFET achieved dv/dt rates of 57 V/ns. The SiC MOSFETs also featured low turn off switching energy losses, which were typically less than 70 µJ at 600 V bus voltage and 20 A load current.
Master of Science

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STELLA, FAUSTO. "On-line Junction Temperature Estimation of SiC Power MOSFETs." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2734315.

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Francisco, sousa alves Luciano. "Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT050.

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Ce travail de thèse étudie de nouvelles configurations d'alimentation de commande rapprochée et un nouveau concept de packaging afin d'améliorer les performances des MOSFETs SiC connectés en série. Les nouvelles configurations de commande rapprochée sont proposées afin de réduire les courants de bruit qui circulent dans la partie commande du système électrique. De plus, une nouvelle alimentation de commande de grille est proposée pour augmenter le dv / dt de la cellule de commutation. Ces améliorations, c'est-à-dire la réduction du courant de bruit et l'amplification du dv/dt, sont obtenues en modifiant l'impédance des circuits de commande de grille. Le nouveau concept de packaging est proposé afin d'améliorer les performances d’équilibrage de tension. Les nouvelles configurations de commande rapprochée et les concepts de packaging sont introduits et analysés grâce à des modèles analytique et des simulations. Ensuite, des essayes expérimentales sont effectuées pour confirmer que les concepts proposés sont meilleurs que les concepts traditionnels en termes d'équilibrage de tension, de vitesse de commutation et de réduction EMI conduite
This work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction

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Noborio, Masato. "Fundamental Study on SiC Metal-Insulator-Semiconductor Devices for High-Voltage Power Integrated Circuits." 京都大学 (Kyoto University), 2009. http://hdl.handle.net/2433/78006.

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Romero, Amy Marie. "Static and Dynamic Characterization of Silicon Carbide and Gallium Nitride Power Semiconductors." Thesis, Virginia Tech, 2018. http://hdl.handle.net/10919/93744.

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Wide-bandgap semiconductors have made and are continuing to make a major impact on the power electronics world. The most common commercially available wide-bandgap semiconductors for power electronics applications are SiC and GaN devices. This paper focuses on the newest devices emerging that are made with these wide-bandgap materials. The static and dynamic characterization of six different SiC MOSFETs from different manufacturers are presented. The static characterization consists of the output characteristics, transfer characteristics and device capacitances. High temperature (up to 150 °C) static characterization provides an insight into the dependence of threshold voltage and on-state resistance on temperature. The dynamic characterizations of the devices are conducted by performing the double-pulse test. The switching characteristics are also tested at high temperature, with the presented results putting an emphasis on one of the devices. A comparison of the key characterization results summarizes the performance of the different devices. The characterization of one of the SiC MOSFETs is then continued with a short-circuit failure mode operation test. The device is subjected to non-destructive and destructive pulses to see how the device behaves. The non-destructive tests include a look at the performance under different external gate resistances and drain-source voltages. It is found that as the external gate resistance is increased, the waveforms get noisier. Also, as the drain-source voltage is increased, the maximum short-circuit current level rises. The destructive tests find the amount of time that the device is able to withstand short-circuit operation. At room temperature the device is able to withstand 4.5 μs whereas at 100 °C, the device is able to withstand 4.2 μs. It is found that despite the different conditions that the device is tested at for destructive tests, the energy that they can withstand is similar. This paper also presents the static and dynamic characterization of a 600 V, 2A, normallyoff, vertical gallium-nitride (GaN) transistor. A description of the fabrication process and the setup used to test the device are presented. The fabricated vertical GaN transistor has a threshold voltage of 3.3 V, a breakdown voltage of 600 V, an on-resistance of 880 mΩ, switching speeds up to 97 V/ns, and turn-on and turn-off switching losses of 8.12 µJ and 3.04 µJ, respectively, demonstrating the great potential of this device
MS

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Laspeyres, Antoine. "Etude et conception d’un « Intelligent Power Module (IPM) » forte puissance en technologie SiC : développement du Gâte Driver." Electronic Thesis or Diss., Nantes Université, 2023. http://www.theses.fr/2023NANU4036.

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L’aéronautique tend à hybrider la propulsion et à électrifier de plus en plus de fonctions. Ceci entraîne une augmentation de la tension du réseau de bord HVDC afin de répondre à ces nouvelles contraintes sur les réseaux et systèmes électroniques. Pour atteindre ces objectifs, les nouveaux composants à semi-conducteurs de puissance SiC en calibre 3.3kV semblent être une alternative pro- metteuse à la filière Silicium IGBT. Cependant, leur faible maturité par rapport à la technologie Si est le principal frein à leur implémentation dans les réseaux de bords. Les travaux de recherche s’inscrivent dans le projet RA- PID AM-PM. L’objectif du projet est de concevoir un module de puissance bras d’onduleur 3,3kV@500A en technologie SiC en apportant une rupture technologique sur le packaging de puissance et son monitoring. Les travaux de recherche concernent le développement d’un circuit de commande intelligent permettant de fiabiliser le module de puissance et d’assurer des commutations sécurisées du semiconducteur. A partir des études sur la fiabilité des compo- sants SiC, deux indicateurs de vieillissement ont été identifiés, la résistance à l’état passant du module et le courant de fuite de grille du composant semiconducteur. Des circuits de surveillance embarqués de ces indicateurs ont été proposés et une nouvelle topologie de com- mande des semiconducteurs, le source driver, est proposée afin de rendre ces circuits compatibles. Pour finir, un démonstrateur spécialement conçu pour le module AM-PM est testé sur module SiC
Aeronautics tend to hybridize propulsion and electrify more and more functions on board. This leads to an increase in the voltage of the onboard network in order to meet these new constraints from electronic systems. To achieve these objectives, the new 3.3kV-rating SiC power semiconductor components seem to be a promising alternative to the Silicon IGBT sector. However, SiC technology’s low level of maturity compared to Si technol- ogy is the main obstacle to its implementation. The research work is part of the AM-PM RAPID project. The project objective is to design a 3.3kV@500A inverter arm power module in SiC technology by providing a technological break- through in power packaging and its monitoring. The research work focuses on the development of the gate driver and its intelligent functions to make the power module more reliable and to ensure secure switching of the semiconductor. From studies on the SiC component’s reliability, two aging indicators have been identified, the on-state resistance of the module and the gate leakage current of the semiconductor compo- nent. On-board monitoring circuits for these in- dicators have been proposed and a new semi- conductor control topology, the source driver, is proposed in order to make these circuits com- patible. Finally, a demonstrator specially de- signed for the AM-PM module is tested on a SiC module

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Sun, Keyao. "Protection, Control, and Auxiliary Power of Medium-Voltage High-Frequency SiC Devices." Diss., Virginia Tech, 2021. http://hdl.handle.net/10919/103743.

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Due to the superior characteristics compared to its silicon (Si) counterpart, the wide bandgap (WBG) semiconductor enables next-generation power electronics systems with higher efficiency and higher power density. With higher blocking voltage available, WBG devices, especially the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), have been widely explored in various medium-voltage (MV) applications in both industry and academia. However, due to the high di/dt and high dv/dt during the switching transient, potential overcurrent, overvoltage, and gate failure can greatly reduce the reliability of implementing SiC MOSFETs in an MV system. By utilizing the parasitic inductance between the Kelvin- and the power-source terminal, a short-circuit (SC) and overload (OL) dual-protection scheme is proposed for overcurrent protection. A full design procedure and reliability analysis are given for SC circuit design. A novel OL circuit is proposed to protect OL faults at the gate-driver level. The protection procedure can detect an SC fault within 50 nanoseconds and protect the device within 1.1 microsecond. The proposed method is a simple and effective solution for the potential overcurrent problem of the SiC MOSFET. For SiC MOSFETs in series-connection, the unbalanced voltages can result in system failure due to device breakdown or unbalanced thermal stresses. By injecting current during the turn-off transient, an active dv/dt control method is used for voltage balancing. A 6 kV phase-leg using eight 1.7 kV SiC MOSFETs in series-connection has been tested with voltage balanced accurately. Modeling of the stacked SiC MOSFET with active dv/dt control is also done to summarize the design methodology for an effective and stable system. This method provides a low-loss and compact solution for overvoltage problems when MV SiC MOSFETs are connected in series. Furthermore, a scalable auxiliary power network is proposed to prevent gate failure caused by unstable gate voltage or EMI interference. The two-stage auxiliary power network (APN) architecture includes a wireless power transfer (WPT) converter supplied by a grounded low voltage dc bus, a high step-down-ratio (HSD) converter powered from dc-link capacitors, and a battery-based mini-UPS backup power supply. The auxiliary-power-only pre-charge and discharge circuits are also designed for a 6 kV power electronics building block (PEBB). The proposed architecture provides a general solution of a scalable and reliable auxiliary power network for the SiC-MOSFET-based MV converter. For the WPT converter, a multi-objective optimization on efficiency, EMI mitigation, and high voltage insulation capability have been proposed. Specifically, a series-series-CL topology is proposed for the WPT converter. With the optimization and new topology, a 120 W, 48 V to 48 V WPT converter has been tested to be a reliable part of the auxiliary power network. For the HSD converter, a novel unidirectional voltage-balancing circuit is proposed and connected in an interleaved manner, which provides a fully modular and scalable solution. A ``linear regulator + buck" solution is proposed to be an integrated on-board auxiliary power supply. A 6 kV to 45 V, 100 W converter prototype is built and tested to be another critical part of the auxiliary power network.
Doctor of Philosophy
The wide bandgap semiconductor enables next-generation power electronics systems with higher efficiency and higher power density which will reduce the space, weight, and cost for power supply and conversion systems, especially for renewable energy. However, by pushing the system voltage level higher to medium-voltage of tens of kilovolts, although the system has higher efficiency and simpler control, the reliability drops. This dissertation, therefore, focusing on solving the possible overcurrent, overvoltage, and gate failure issues of the power electronics system that is caused by the high voltage and high electromagnetic interference environment. By utilizing the inductance of the device, a dual-protection method is proposed to prevent the overcurrent problem. The overcurrent fault can be detected within tens of nanoseconds so that the device will not be destroyed because of the huge fault current. When multiple devices are connected in series to hold higher voltage, the voltage sharing between different devices becomes another issue. The proposed modeling and control method for series-connected devices can balance the shared voltage, and make the control system stable so that no overvoltage problem will happen due to the non-evenly distributed voltages. Besides the possible overcurrent and overvoltage problems, losing control of the devices due to the unreliable auxiliary power supply is another issue. This dissertation proposed a scalable auxiliary power network with high efficiency, high immunity to electromagnetic interference, and high reliability. In this network, a wireless power transfer converter is designed to provide enough insulation and isolation capability, while a switched capacitor converter is designed to transfer voltage from several kilovolts to tens of volts. With the proposed overcurrent protection method, voltage sharing control, and reliable auxiliary power network, systems utilizing medium-voltage wide-bandgap semiconductor will have higher reliability to be implemented for different applications.

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Sadik, Diane-Perle. "On Reliability of SiC Power Devices in Power Electronics." Doctoral thesis, KTH, Elkraftteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207763.

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Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.
Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.

QC 20170524

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Cairnie, Mark A. Jr. "Bayesian Optimization of PCB-Embedded Electric-Field Grading Geometries for a 10 kV SiC MOSFET Power Module." Thesis, Virginia Tech, 2021. http://hdl.handle.net/10919/103566.

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A finite element analysis (FEA) driven, automated numerical optimization technique is used to design electric field grading structures in a PCB-integrated bus bar for a 10 kV bondwire-less silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, careful design of field-grading structures inside the bus bar is required to mitigate the high electric field strength in the air. Using Bayesian optimization and a new weighted point-of-interest (POI) cost function, the highly non-uniform electric field is efficiently optimized without the use of field integration, or finite-difference derivatives. The proposed optimization technique is used to efficiently characterize the performance of the embedded field grading structure, providing insights into the fundamental limitations of the system. The characterization results are used to streamline the design and optimization of the bus bar and high-density module interface. The high-density interface experimentally demonstrated a partial discharge inception voltage (PDIV) of 11.6 kV rms. When compared to a state-of-the-art descent-based optimization technique, the proposed algorithm converges 3x faster and with 7x smaller error, making both the field grading structure and the design technique widely applicable to other high-density high-voltage design problems.
M.S.
Innovation trends in electrical engineering such as the electrification of consumer and commercial vehicles, renewable energy, and widespread adoption of personal electronics have spurred the development of new semiconductor materials to replace conventional silicon technology. To fully take advantage of the better efficiency and faster speeds of these new materials, innovation is required at the system-level, to reduce the size of power conversion systems, and develop converters with higher levels of integration. As the size of these systems decreases, and operating voltages rise, the design of the insulation systems that protect them becomes more critical. Historically, the design of high-density insulation system requires time-consuming design iteration, where the designer simulates a case, assesses its performance, modifies the design, and repeats, until adequate performance is achieved. The process is computationally expensive, time-consuming, and the results are not easily applied to other insulation design problems. This work proposes an automated design process that allows for the streamlined optimization of high-density insulation systems. The process is applied to a 10 kV power module and experimentally demonstrates a 38\% performance improvement over manual design techniques, while providing an 8 times reduction in design cycle time.

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Rong, Yu. "A Synchronous Distributed Control and Communication Network for High-Frequency SiC-Based Modular Power Converters." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/96395.

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Numerous power electronics building blocks (PEBB) based power conversion systems have been developed to explore modular design, scalable voltage and current ratings, low-cost operations, etc. This paper further extends the modular concept from the power stage to the control system. The communication network in SiC-based modular power converters is becoming significant for distributed control architecture, with the requirements of tight synchronization and low latency. The influence of the synchronization accuracy on harmonics under the phase-shifted carrier pulse width modulation (PSC-PWM) is evaluated. When the synchronization is accurate, the influence of an increase in harmonics can be ignored. Thus, a synchronous distributed control and communication protocol with well-performed synchronization of 25 ns accuracy is proposed and verified for a 120 kHz SiC-based impedance measurement unit (IMU) with cascaded H-bridge PEBBs. An improved synchronization method with additional analog circuits is further implemented and verified with sub-ns synchronization accuracy.
The power electronics building block (PEBB) concept is proposed for medium-voltage converter applications in order to realize the modular design of the power stage. Traditionally, the central control architecture is popular in converter systems. The voltage and current are sensed and then processed in one central controller. The control hardware interfaces and software have to be customized for a specified number of power cells, and the scalability of controller is lost. In stead, in the distributed control architecture, a local controller in each PEBB can communicate with the sensors, gate drivers, etc. A high-level controller collects the information from each PEBB and conducts the control algorithm. In this way, the design can be more modular, and the local controller can share the computation burden with the high-level controller, which is good for scalability. In such distributed control architecture, a synchronous communication system is required to transmit data and command between the high-level controller and local controllers. A power converter always requires a highly synchronized operation to turn on or turn off the devices. In this work, a synchronous communication protocol is proposed and experimentally validated on a SiC-based modular power converter.

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Kulisek, Jonathan Andrew. "The Effects of Nuclear Radiation on Schottky Power Diodes and Power MOSFETs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1267502877.

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Mocevic, Slavko. "PCB-Embedded Phase Current Sensor and Short-Circuit Detector for High Power SiC-Based Converters." Thesis, Virginia Tech, 2018. http://hdl.handle.net/10919/84348.

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Nowadays, major public concern is concentrated on reducing the usage of fossil fuels and reducing emissions of CO2 by different energy advancement. Electric vehicle technology presents extremely effective way of reducing carbon emissions and paves the way of having sustainable and renewable energy future. In order to wear the cost of electric vehicles down, batteries have to be improved as well as higher power density and high reliability has to be achieved. This research work mainly focuses on achieving higher power density and higher reliability of the inverter stage by utilizing wide-bandgap SiC MOSFET semiconductor devices in electric vehicle application. In order to achieve higher reliability of the inverter stage, high bandwidth, high performance Rogowski coil switch current sensors are employed. These sensor were embedded on the PCB and integrated on the gate driver. High bandwidth switch current sensor measurement is used for fast short-circuit detection and protection of the SiC MOSFET semiconductor switches. Furthermore, comparison with conventional detection and protection method used in automotive IGBT applications is shown where novel protection showed superior performance. This thesis also shows principle of how to obtain phase currents of the system using Rogowski coil switch current sensor measurements. Digital reconstruction principle is employed to obtain the phase currents. Accurate and linear current sensor is achieved. By successfully realizing this integrated phase current measurement on the gate driver, elimination of the commercial current sensors from the system is possible. By eliminating existing phase current sensors, higher power density could be achieved. Sensor is evaluated in both continuous and discontinuous PWM schemes.
Master of Science
Together with renewable sources, electric vehicle will play an important role as a part of sustainable and renewable energy future by significantly reducing emissions of CO2 into the atmosphere. In order to make electric cars more acceptable and accessible and make a significant impact on the environment, cost must be lowered down. To wear the cost of the electric vehicles down, powertrain of the car must be significantly improved and made smaller as well as lighter. This thesis mainly focuses on improving the reliability of the motor driving stage by implementing novel protection during fault periods such as short-circuit event. Furthermore, this novel protection allows current sensing that is crucial for motor control during normal operation periods. This will enable more compact motor driving stage since existing current sensing elements can be eliminated.

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Dbeiss, Mouhannad. "Mission Profile-Based Accelerated Ageing Tests of SiC MOSFET and Si IGBT Power Modules in DC/AC Photovoltaic Inverters." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT020/document.

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Dans le cas des installations photovoltaïques, l’onduleur est le premier élément défaillant dont il est difficile d’anticiper la panne, et peu d’études ont été faites sur la fiabilité de ce type de convertisseur. L'objectif de cette thèse est de proposer des outils et méthodes en vue d'étudier le vieillissement des modules de puissance dans ce type d'application en se focalisant sur les phénomènes de dégradation liés à des aspects thermomécaniques. En règle générale, le vieillissement accéléré des modules de puissance est effectué dans des conditions aggravées de courant (Cyclage Actif) ou de température (Cyclage Passif) pour accélérer les processus de vieillissement. Malheureusement, en appliquant ce type de vieillissement accéléré, des mécanismes de défaillances qui ne se produisent pas dans la vraie application peuvent être observés et, inversement, d'autres mécanismes qui se produisent habituellement peuvent ne pas apparaître. La première partie de la thèse se focalise donc sur la mise en place d'une méthode de vieillissement accéléré des composants semi-conducteurs des onduleurs photovoltaïques. Cela est fait en s’appuyant sur l’analyse des profils de mission du courant efficace de sortie des onduleurs et de la température ambiante, extraits des centrales photovoltaïques situées au sud de la France sur plusieurs années. Ces profils sont utilisés pour étudier les dynamiques du courant photovoltaïque, et sont introduites dans des modèles numériques pour estimer les pertes et les variations de la température de jonction des semi-conducteurs utilisés dans les onduleurs, en utilisant l’algorithme de comptage de cycles "Rainflow". Cette méthode est ensuite mise en œuvre dans deux bancs expérimentaux. Dans le premier, les composants sous test sont des modules IGBT. Les composants sont mis en œuvre dans un banc de cyclage utilisant la méthode d'opposition et mettant en œuvre le profil de vieillissement défini précédemment. Un dispositif in-situ de suivi d'indicateurs de vieillissement (impédance thermique et résistance dynamique) est également proposé et évalué. Le deuxième banc est consacré à l'étude de modules de puissance à base de MOSFET SiC. Le vieillissement est effectué dans les mêmes conditions que pour les modules IGBT et de nombreux indicateurs électriques sont monitorés mais, cette fois ci, en extrayant les composants de l'onduleur de cyclage. Les résultats obtenus ont permis de déterminer des indicateurs de vieillissement d’IGBT et de MOSFET SiC utilisés dans un onduleur photovoltaïque
In the case of photovoltaic installations, the DC/AC inverter has the highest failure rate, and the anticipation of its breakdowns is still difficult, while few studies have been done on the reliability of this type of inverter. The aim of this PhD is to propose tools and methods to study the ageing of power modules in this type of application, by focusing on ageing phenomena related to thermo-mechanical aspects. As a general rule, the accelerated ageing of power modules is carried out under aggravated conditions of current (Active Cycling) or temperature (Passive Cycling) in order to accelerate the ageing process. Unfortunately, when applying this type of accelerated ageing tests, some failure mechanisms that do not occur in the real application could be observed, while inversely, other mechanisms that usually occur could not be recreated. The first part of the PhD focuses on the implementation of an accelerated ageing method of the semiconductor devices inside photovoltaic inverters. This is accomplished by analyzing the mission profiles of the inverter’s output current and ambient temperature, extracted over several years from photovoltaic power plants located in the south of France. These profiles are used to study photovoltaic current dynamics, and are introduced into numerical models to estimate losses and junction temperature variations of semiconductors used in inverters, using the cycle counting algorithm “Rainflow”. This method is then performed in two experimental test benches. In the first one, the devices under test are IGBT modules, where the accelerated ageing profile designed is implemented using the opposition method. Moreover, an in-situ setup for monitoring ageing indicators (thermal impedance and dynamic resistance) is also proposed and evaluated. The second bench is devoted to study the ageing of SiC MOSFET power modules. The accelerated ageing test is carried out under the same conditions as for the IGBT modules with more monitored electrical indicators, but this time by disconnecting the semiconductor devices from the inverter. The results obtained allowed to determine several potential ageing indicators of IGBTs and SiC MOSFETs used in a photovoltaic inverter

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Stackler, Caroline. "Transformateurs électroniques pour applications ferroviaires." Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0015.

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Actuellement, la majorité des convertisseurs embarqués dans des trains circulant sous une caténaire alternative est composée d’un transformateur basse fréquence, puis de redresseurs,alimentant des moteurs de traction via des onduleurs de traction. Les inconvénients majeurs de ces structures sont un volume et une masse embarqués importants, dus au transformateur fonctionnant en basse fréquence. Le rendement est également mauvais, à cause des contraintes de volume et de masse. Grâce aux développements des semiconducteurs haute tension et forte puissance et des transformateurs moyenne fréquence, i.e. de l’ordre de quelques kilohertz, de nouvelles topologies de convertisseurs embarqués, appelées transformateurs électroniques, sont à l’étude. Si plusieurs topologies ont déjà été étudiées dans la littérature, elles n’ont jamais été comparées. L’objectif principal de cette thèse est donc de proposer une méthodologie de dimensionnement des différentes topologies de transformateurs électroniques, afin de pouvoir les comparer. Un état de l’art des différentes structures proposées dans la littérature est présenté dans le premier chapitre de ce mémoire. Le chapitre 2 est consacré à la comparaison de structures indirectes. Pour cela, une méthodologie, permettant d’optimiser le dimensionnement de chaque structure afin de maximiser son rendement sous des contraintes de masse et de volume, a été développée. Elle est ensuite appliquée sur des topologies utilisant des MOSFET SiC, contrairement aux structures à IGBT Si développées dans la littérature. L’inductance magnétisante est considérée afin d’assurer un fonctionnement en commutation douce, et ainsi limiter les pertes. Un troisième chapitre propose un filtre actif innovant, intégré aux DC-DC du convertisseur. Celui-ci a pour but de réduire le volume du condensateur de filtrage des bus intermédiaires, et ainsi le volume total du convertisseur, sans dégrader la fiabilité intrinsèque de celui-ci. Son fonctionnement et son impact sur les pertes du DC-DC y sont étudiés. Enfin, le dernier chapitre est dédié à l’étude des interactions entre le convertisseur embarqué et l’infrastructure ferroviaire. Pour cela, des modèles d’infrastructure 25 kV-50 Hz ont été réalisés. Ceux ci comportent notamment un circuit original modélisant l’effet de peau dans la caténaire. Des résonances à certaines fréquences, caractéristiques de la géométrie du réseau et de la position du train sur celui-ci, ont été mises en évidence dans l’impédance vue par le train. Ces modèles ont aussi été implémentés dans un simulateur numérique, pour alimenter une maquette petite échelle de convertisseur. Ce type de test n’a, a priori, jamais été réalisé sur un transformateur électronique. Une conclusion générale et des perspectives sur les travaux présentés concluent ce mémoire
Current on-board converters, running on AC catenaries, are mainly composed by a low frequency transformer, then rectifiers, supplying traction motors through three-phase inverters. Due to volume and mass constraints on the converter, the efficiency of the transformer is limited. Moreover, this transformer is quite bulky and heavy. Thanks to the development of high voltage and high power semiconductors, such as Si IGBTs or SiC MOSFETs, and of medium frequency transformer, i.e. operating at a few kilohertz, new topologies of on-board converters, named Power Electronic Traction Transformer (PETT), are studied. Though several structures have been studied in the literature, they have never been compared. The main objective of this thesis is, thus, to develop a methodology to size PETT topologies, in order to compare them. In the first chapter, a state of the art of the PETT structures proposed in literature is presented. The second chapter is dedicated to the comparison of indirect topologies. A methodology, optimising the sizing of each structure to maximise its efficiency under mass and volume constraints, is developed. It is applied on topologies using SiC MOSFETs, contrary to Si IGBT structures developed in the literature. The magnetizing inductance is also considered to insure soft switching and reduce the losses. In the third chapter, an novel active filter, included in the DC-DCs of the converter, is proposed. The aim is to reduce the volume of the filtering capacitors on the intermediate buses, and thus, of the entire converter, without impacting the intrinsic reliability of the converter. Its impact on the losses of the DC-DC is studied. The last chapter deals with the interactions between the on-board converter and the infrastructure. Thus, the 25 kV-50 Hz railway network is modeled. It includes a novel circuit, modelling the skin effect in the catenary. Some resonances, dependant on the sector geometry and the train position, are highlighted in the impedance seen by a train. Moreover, the models are implemented in a numerical simulator to supply a small scale mock-up of a PETT. PHIL tests have, a priori, never been carried on a PETT. A conclusion and some perspectives of future work close thisdissertation

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Salinaro, Alberto Verfasser], Lothar [Gutachter] Frey, and Nando [Gutachter] [Kaminski. "Characterization and Development of the 4H-SiC/SiO2 Interface for Power MOSFET Applications / Alberto Salinaro ; Gutachter: Lothar Frey, Nando Kaminski." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2016. http://d-nb.info/1118850076/34.

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Salinaro, Alberto [Verfasser], Lothar Gutachter] Frey, and Nando [Gutachter] [Kaminski. "Characterization and Development of the 4H-SiC/SiO2 Interface for Power MOSFET Applications / Alberto Salinaro ; Gutachter: Lothar Frey, Nando Kaminski." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2016. http://d-nb.info/1118850076/34.

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Aviñó, Salvadó Oriol. "Contribution to the study of the SiC MOSFETs gate oxide." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI110/document.

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Les MOSFET en SiC sont appelées à remplacer les IGBT en Silicium pour des applications de demandant une plus forte vitesse de commutation. Cependant, les MOSFET en SiC ont encore quelques problèmes de fiabilité, tels que la robustesse de la diode interne ou bien la robustesse de l'oxyde de grille. Cette dernière est liée à l’oxyde de grille des composants du type MOSFET. Des instabilités de la tension de seuil sont aussi signalées. Cette thèse aborde ces deux sujets sur des MOSFET commerciaux 1200 V. L'étude de la diode interne met en évidence que les caractéristiques I-V (de la diode intrinsèque) demeurent stables après l'application d'un stress. Cependant, une dérive surprenante de la tension de seuil apparaît. Des tests complémentaires, en stressant le canal à la place de la diode, avec les mêmes contraintes n'ont pas montré de dérive significative de la tension de seuil. Donc, l'application d'un stress en courant quand le composant est en mode d'accumulation semble favoriser l'apparition des instabilités de la tension de seuil. La robustesse de l'oxyde de grille concerne les instabilités de la tension de seuil, mais aussi l'estimation de la durée de vie à des conditions d'opération nominales. Les résultats obtenus montrent que la durée de vie de l'oxyde de grille n'est plus un problème. Pourtant, le suivi du courant de grille pendant les tests ainsi que les caractérisations de la capacité de grille mettent en évidence des translations de la courbe C(V) à cause des phénomènes d’injection des porteurs et de piégeage, mais aussi la possible présence d’ions mobiles. Aussi, une bonne analyse des dégradations et dérives liées à l’oxyde de grille doit être réalisée
SiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate

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Watt, Grace R. "Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/96559.

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This paper describes the design, fabrication, and testing of a 1.2 kV, 6.5 mΩ, half-bridge, SiC MOSFET power module to evaluate the impact of parametric device tolerances on electrical and thermal performance. Paralleling power devices increases current handling capability for the same bus voltage. However, inherent parametric differences among dies leads to unbalanced current sharing causing overstress and overheating. In this design, a symmetrical DBC layout is utilized to balance parasitic inductances in the current pathways of paralleled dies to isolate the impact of parametric tolerances. In addition, the paper investigates the benefits of flexible PCB in place of wire bonds for the gate loop interconnection to reduce and minimize the gate loop inductance. The balanced modules have dies with similar threshold voltages while the unbalanced modules have dies with unbalanced threshold voltages to force unbalanced current sharing. The modules were placed into a clamped inductive DPT and a continuous, boost converter. Rogowski coils looped under the wire bonds of the bottom switch dies to observe current behavior. Four modules performed continuously for least 10 minutes at 200 V, 37.6 A input, at 30 kHz with 50% duty cycle. The modules could not perform for multiple minutes at 250 V with 47.7 A (23 A/die). The energy loss differential for a ~17% difference in threshold voltage ranged from 4.52% (~10 µJ) to -30.9% (~30 µJ). The energy loss differential for a ~0.5% difference in V_th ranged from -2.26% (~8 µJ) to 5.66% (~10 µJ). The loss differential was dependent on whether current unbalance due to on-state resistance compensated current unbalance due to threshold voltage. While device parametric tolerances are inherent, if the higher threshold voltage devices can be paired with devices that have higher on-state resistance, the overall loss differential may perform similarly to well-matched dies. Lastly, the most consistently performing unbalanced module with 17.7% difference in V_th had 119.9 µJ more energy loss and was 22.2°C hotter during continuous testing than the most consistently performing balanced module with 0.6% difference inV_th.
Master of Science
This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to different parts of the vehicle; for example, energy is stored in a battery as direct current (DC) power, but the motor requires alternating current (AC) power. Therefore, power electronics can alter the energy to be delivered as DC or AC. In order to carry more power, multiple devices can be used together just as 10 people can carry more weight than 1 person. However, because the devices are not perfect, there can be slight differences in the performance of one device to another. One device may have to carry more current than another device which could cause failure earlier than intended. In this research project, multiple power devices were placed into a package, or "module." In a control module, the devices were selected with similar properties to one another. In an experimental module, the devices were selected with properties very different from one another. It was determined that the when the devices were 17.7% difference, there was 119.9 µJ more energy loss and it was 22.2°C hotter than when the difference was only 0.6%. However, the severity of the difference was dependent on how multiple device characteristics interacted with one another. It may be possible to compensate some of the impact of device differences in one characteristic with opposing differences in another device characteristic.

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Molin, Quentin. "Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI111.

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Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap qui possède des caractéristiques bien meilleures que le silicium. Ces nouveaux interrupteurs de puissances permettent d’obtenir entre autres propriétés remarquables, des fréquences de commutations et des tenues en tension plus élevées dans les systèmes de conversions de puissance. Ils sont particulièrement mis en avant depuis un peu plus d’une dizaine d’années pour les gains en performances, diminution des tailles et poids qu’ils apportent à certaines topologies de convertisseurs pour les réseaux haute tension à courant continu. Puis sont répertoriés les principaux mécanismes de défaillances de ces MOSFET SiC induits par la faiblesse de la grille. Toutes les mesures nécessaires au suivi des paramètres clés lors des prochains vieillissements sont présentées. Les résultats de nos tests sur l’instabilité de la tension de seuil sont aussi détaillés et un modèle empirique pour valider le comportement de relaxation observé est proposé. Celui-ci nous aidera par la suite à établir un protocole de mesure rigoureux de la tension de seuil. Les tests expérimentaux et résultats de vieillissement en statique et dynamique sur les composants 1,7 kV vont permettre de se rendre compte de l’importance de la dérive de la tension de seuil sur 1000 h. Dans le cas d’un vieillissement statique, il y a environ 7 % de dérive positive du VTH et un pourcentage équivalent pour les tests dynamiques. Des analyses supplémentaires (C-V et pompage de charge) sur l’oxyde de grille en cours de vieillissement sont proposées pour une meilleure compréhension des mécanismes mis en jeu dans la dégradation de l’oxyde. Enfin, les derniers tests présentés seront focalisés sur le comportement en court-circuit et courts-circuits répétitifs des mêmes composants. Avec une énergie critique évaluée autour de 1,5 J nos tests sur les MOSFET 1,7 kV montrent les limites de la robustesse de ces composants, avec une tenue en court-circuit bien inférieure à 10 µs et une incapacité à résister à plus de 150 courts-circuits successifs. L’influence de la tension entre drain et source y est notamment étudiée, et montre que l’énergie critique supportée par le composant diminue avec l’augmentation de cette tension
This manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks. Others power switches available are still introduced and an introduction to reliability is explaining why such work on this new power switches is important. Transition from Si technologies to SiC ones require a lot of work regarding its robustness. Before showing reliability and robustness results is presented I give a lot of details regarding to the measurement and monitoring of key parameters used in the next chapters. The results of our tests on the threshold voltage instability are presented and how we validated an empirical model on this drift. This was used to propose an enhanced measurement protocol on the threshold voltage. Static and dynamic experimental results presented next will show if the voltage drift during ageing is significant or not. Further analysis is proposed to add more insight on the understanding of the oxide degradation mechanisms through C-V and charge pumping measurements. Finally, the ageing results presented on 1,7 kV SiC MOSFET are focused on the short-circuit and repetitive short-circuit behavior of the same components. Drain to source voltage influence on critical energy during this particular and stressful operation mode is studied. This time, the results are worrying.The last chapter is confidential

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Barazi, Yazan. "Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology." Thesis, Toulouse, INPT, 2020. http://www.theses.fr/2020INPT0091.

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Les transistors de puissance grands gaps tels que les MOSFETs SiC et HEMT GaN repoussent les compromis classiques en électronique de puissance. Brièvement, des gains significatifs ont été démontrés par les transistors SiC et GaN: meilleurs rendements, couplés à une augmentation des densités de puissance offertes par la montée en fréquence de découpage. Les MOSFET SiC à haute tension présentent des spécificités telles qu'une faible tenue en court-circuit (SC) par rapport aux IGBT Si et un oxyde de grille aminci, et une tension de commande rapprochée grillesource élevée. La polarisation négative sur la grille à l'état bloqué crée un stress supplémentaire qui réduit la fiabilité du MOSFET SiC. La forte polarisation positive de la grille provoque un courant de saturation de drain important en cas de SC. Ainsi, cette technologie fait émerger des besoins spécifiques de surveillance et de protection ultra-rapides. Pour cela, le travail de cette thèse se focalise sur deux études pour surmonter ces contraintes toute en gardant un bon compromis de performances entre « niveau d’intégration technologique ‘CMS/ASIC-CMOS’–rapidité–robustesse ». La première, regroupe un ensemble de solutions nouvelles permettant une détection du courtcircuit sur le cycle de commutation, sur la base d'une architecture conventionnelle de commande rapprochée dite à 2 niveaux de tension. La deuxième étude est plus exploratoire et basée sur une nouvelle architecture de gate–driver, dite multi-niveaux, à faible niveau de stress pour le MOSFET SiC tout en maintenant les performances dynamiques. Les travaux portent tout d’abord sur l’environnement du SiC MOSFET, (caractérisation et propriétés de comportement en SC par simulations orientées "circuit" de type PLECS™ et LTSpice™), puis présentent une étude bibliographique sur les commandes rapprochées dites Gate Driver, une étude approfondie a été réalisée sur les court-circuits type I & II (Hard switch fault) (Fault under Load) ; regroupés dans un premier chapitre du manuscrit. Un banc de test réalisé antérieurement au sein du laboratoire, a permis de compléter et de valider l’étude d'analyse-simulation et de préparer des stimuli test pour l'étape de conception des nouvelles solutions. Inspirée par la méthode de Gate charge apparue pour les IGBTs en silicium et évoquée pour les MOSFETs SiC, cette première approche fait l'objet d'un travail de conception, de dimensionnement et de prototypage. Cette méthode de référence permet une détection de type HSF en moins de 200ns sous 0-600V avec des composants 1,2kV allant de 80 mOhm à 120mOhm. S'agissant des nouvelles méthodes de détection rapides et intégrées, les travaux de cette thèse se focalisent particulièrement sur la conception d’un circuit ASIC CMOS. Pour cela, la conception d’un gate driver adapté est essentiel. Un ASIC est conçu en technologie X-Fab XT-0,18μm SOICMOS sous Cadence™, et puis mis en boitier et assemblé sur PCB conçu pour les besoins de tests et adaptable au banc principal. La conception du gate driver a considéré de nombreuses fonctions (détection du SC, SSD Soft shut down, buffer segmenté, AMC Active Miller Clamp", …). Du point de vue de la détection du SC, les fonctions nouvelles de surveillance intégrées concernent la méthode de dérivation temporelle de VGS qui est basée sur une détection par un circuit dérivateur analogique RC sur la séquence de plateau avec deux variantes. Une deuxième méthode nouvelle partiellement intégrée dans l'ASIC a été conçu, non développé dans ce mémoire dans le but d’une valorisation. En marge de cette étude principale, une étude exploratoire a porté sur une nouvelle architecture modulaire de commande rapprochée à plusieurs niveaux de tension de polarisation tirant profit de l'isolation SOI et des transistors CMOS à basse tension pour piloter le MOSFETs SiC et améliorer leur fiabilité grâce à une sélection active et dynamique à plusieurs niveaux sur les séquences de commutation et les états marche/arrêt
Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states

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Roder, Raphaël. "Intégration et fiabilité d'un disjoncteur statique silicium intelligent haute température pour application DC basse et moyenne tensions." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0287/document.

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Cette thèse présente l'étude et la réalisation d'un disjoncteur statique tout silicium et intelligent pouvant fonctionner à haute température (200°C) pour des applications de type DC basse et moyenne tensions. Plusieurs applications dans l’aéronautique, l’automobile et les transports ferroviaires poussent les composants à semi-conducteur de puissance à être utilisés à haute température. Cependant, les Si-IGBT et Si-CoolMOSTM actuellement commercialisés ont une température de jonction spécifiée et estimée à 150°C et quelque fois à 175°C. L’une des faiblesses des convertisseurs provient de la réduction du rendement avec l’augmentation de la température de jonction des composants à semiconducteur de puissance qui peut amener à leur destruction. La solution serait d’utiliser des composants grand-gap (SiC, GaN), qui autorisent un fonctionnement à une température de jonction plus élevée ;mais ces technologies en plein essor ont un coût relativement élevé. Une solution alternative serait de faire fonctionner des composants en silicium à une température de jonction voisine de 200°C afin de conserver l’un des principaux intérêts du silicium en termes de coût. Avant de commencer, le premier chapitre portera sur un état de l’art des différentes techniques de protection aussi bien mécanique que statique afin d’identifier les éléments essentiels pour la réalisation du circuit de protection. Les disjoncteurs hybrides seront aussi abordés afin de voir comment ceux-ci arrivent à combler les lacunes des disjoncteurs mécaniques et purement électroniques (statiques). A partir du chapitre précédent, un disjoncteur statique intelligent de faible puissance sera réalisé afin de mieux cerner les différentes difficultés qui sont liées à ce type de disjoncteur. Le disjoncteur statique sera réalisé à partir de fonction analogique de telle façon à ce qui soit autonome et bas cout. Il en ressort que les inductances parasites ainsi que la température des composants à base de semi-conducteurs ont un impact significatif lors de la coupure.Le chapitre III portera sur une analyse non exhaustive, vis-à-vis de la température, de différents types d’interrupteurs contrôlés à base de semi-conducteur de puissance en s’appuyant sur plusieurs caractérisations électriques (test de conduction, tension de seuil, etc) afin de sélectionner le type d’interrupteur de puissance qui sera utilisé pour le chapitre IV. Comme il sera démontré, les composants silicium à super jonction peuvent se rapprocher du comportement des composants à base de carbure de silicium pour les basses puissances. Un disjoncteur statique 400V/63A (courant de court-circuit prédictible de 5kA) sera étudié et 4développé afin de mettre en pratique ce qui a été précédemment acquis et pour montrer la compétitivité du silicium pour cette gamme de puissance
This thesis presents a study about a smart solid state circuit breaker which can work at 200°C forlow and medium voltage continuous applications. Some applications in aeronautics, automotive,railways, petroleum extraction push power semiconductor devices to operate at high junctiontemperature. However, current commercially available Si-IGBT and Si-CoolMOS have basically amaximum junction temperature specified and rated at 150°C and even 175°C. Indeed, the main problemin conventional DC-DC converters is the switching losses of power semiconductor devices (linked to thetemperature influence on carrier lifetime, on-state voltage, on-resistance and leakage current) whichdrastically increase with the temperature rise and may drive to the device failure. Then, the use of wideband gap semiconductor like SiC or GaN devices allows higher junction temperature operation (intheory about 500°C) and higher integration (smaller heatsink, higher switching frequency, smallconverter), but are still under development and are expensive technologies. In order to keep theadvantage of low cost silicon devices, a solution is to investigate the feasibility to operate such devicesat junction temperature up to 200°C.Before starting the first starting chapter is a stat of the art of protectives circuit technics as well asmechanics as statics in order to identify essentials elements to develop the protective circuit. Hybridprotective circuits are approached too.From the precedent chapter, a smart and low power solid state circuit breaker is realized to identifyproblems which are linked with this type of circuit breaker. Solid state circuit breaker is developed withanalog components in a way that is autonomous and low cost. It’s follow that stray inductance andtemperature have an important impact when a default occurs.Chapter III give an analyze on different silicon power semiconductor dice towards temperature5relying on statics and dynamics characteristics in order to find the best silicon power switch which beused in the chapter IV. It has been shown that super junction MOSFET has the same behavior at lowpower than silicon carbide MOSFET.Solid state circuit breaker (400V/63A) has been studied and developed, in order to use all theknowledge previously acquired and to show the competitively of the silicon for this power range

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Santini, Thomas. "Contribution à l'étude de la fiabilité des MOSFETs en carbure de silicium." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEI021/document.

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Ces dernières années ont vu apparaître sur le marché les premiers transistors de puissance de type MOSFET en carbure de silicium. Ce type de composant est particulièrement adapté à la réalisation d’équipement électrique à haut rendement et capable de fonctionner à haute température. Néanmoins, la question de la fiabilité doit être posée avant de pouvoir envisager la mise en œuvre de ces composants dans des applications aéronautiques ou spatiales. Les mécanismes de défaillance liés à l’oxyde de grille ont pendant longtemps retardé la mise sur le marché des transistors à grille isolée en carbure de silicium. Cette étude s’attache donc à estimer la durée de vie des MOSFET SiC de 1ére génération. Dans un premier temps, le mécanisme connu sous le nom de Time Dependent Dielectric Breakdown(TDDB) a été étudié au travers de résultats expérimentaux issus de la bibliographie. Notre analyse nous a permis de justifier de l’emploi d’une loi de Weibull pour modéliser la distribution des temps à défaillance issue de ces tests. Les résultats nous ont également permis de confirmer l’amélioration significative de la fiabilité de ces structures vis-à-vis de ce mécanisme. Dans un second temps, l’impact du mécanisme d’instabilité de la tension de seuil sur la fiabilité a été quantifié au travers de tests de vieillissement de type HTGB. Les données de dégradation ainsi collectées ont été modélisées à l’aide d’un processus gamma non-homogène, qui nous a permis de prendre en compte la variabilité entre les composants testés dans des conditions identiques et de proposer des facteurs d’accélération en tension et en température pour ce mécanisme. Enfin, ces travaux ont permis d’ouvrir la voie à la mise en œuvre d’outils de pronostic de la durée de vie résiduelle pour les équipements électriques
Recent years have seen SiC MOSFET reach the industrial market. This type of device is particularly adapted to the design of power electronics equipment with high efficiency and high reliability capable to operate in high ambient temperature. Nevertheless the question of the SiC MOSFET reliability has to be addressed prior to considering the implementation of such devices in an aeronautic application. The failure mechanisms linked to the gate oxide of the SiC MOSFET have for a long time prevented the introduction of the device. In this manuscript we propose to study the reliability of the first generation of SiC MOSFET. First, the mechanism known as the Time–Dependent Dielectric Breakdown is studied through experimental results extracted from literature. Our study shows the successful application of a Weibull law to model the time-to-failure distribution extracted from the accelerated tests. The results show also a significant improvement of the SiC MOSFET structure with respect to this phenomenon. In a second step, the impact of the threshold voltage instability is quantified through accelerated tests known as High Temperature Gate Bias. The collected degradation data are modeled using a non-homogeneous Gamma process. This approach allows taking into account the variability between devices tested under the same conditions. Acceleration factors have been proposed with respect to temperature and gate voltage. Eventually the study delivers a primary estimation of the remaining useful lifetime of the SiC MOSFET in a typical aeronautic application

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Alhoussein, Ali. "Caractérisation et modélisation CEM des nouvelles technologie de composants de puissance (SIC). : Application : convertisseurs de puissance." Thesis, Normandie, 2020. http://www.theses.fr/2020NORMR043.

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Avec le développement des nouveaux composants de puissance à grand gap plus performants que leurs homologues en Silicium et l’intégration croissante de ces composants dans le véhicule électrique, la compatibilité électromagnétique est devenue un enjeu important pour le respect des normes de conformité en vigueur. La thèse traite donc les méthodes de modélisation haute fréquence des composants grand gap. Les problèmes liés à la fiabilité et la précision des modèles actuels sont mis en évidence. Ensuite, un nouveau modèle générique est proposé avec des formulations spécifiques lui permettant de mieux reproduire les caractéristiques statiques et dynamiques des MOSFETs en SiC. Des bancs de test ont été mis en place permettant de caractériser ces nouveaux composants avec des précautions spécifiques afin d’améliorer la précision de ces mesures. L’utilisation d’un algorithme génétique développé pour identifier les paramètres du modèle générique proposé, a permis une reproduction fine des caractéristiques mesurées expérimentalement de plusieurs composants SiC ainsi que les perturbations CEM générées dans un convertisseur statique
With the development of new large-gap power components with superior performance compared to their Silicon counterparts and the rising integration of these components in the electric vehicle, electromagnetic compatibility has become an important issue for compliance with normative standards. Hence, this thesis discusses the modeling methods of wide bandgap components. Problems related to the reliability of the models and their accuracy are highlighted. Then, a new model is proposed with specific formulations allowing it to better reproduce the static and dynamic characteristics of SiC MOSFETs. Test benches have been set up to characterize these new components with specific precautions in order to improve the precision of the measurements. The use of a developed genetic algorithm to identify the parameters of the proposed generic model, allowed a close reproduction of the characteristics measured experimentally of several SiC components as well as the EMC disturbances generated in a static converter

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Shah, Vatsal Sonikbhai. "Optimization and Up-Gradation of 3-Phase Half-Bridge Inverter Board." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-173664.

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Solar Bora AB is a Linköping based company that provides end to end solution for clean and reliable energy. System developed by them generates high power 230V AC to run electrical appliances. The system consist of string of batteries which are charged by rooftop solar cells and the energy stored in the batteries is converted to AC to provide a grid voltage like experience even though the system is not connected to a grid. Energy stored in the batteries need to be converted from DC to AC efficiently. Inverter used for conversion should be efficient enough to reduce losses. This master thesis deals with optimization and Up-gradation of Half-Bridge inverter board so that switching loss can be minimized to increase efficiency. Initial part of the thesis involves investigation of different parameters which contribute to losses in inverter. Based on that some improvements were suggested in existing design of half-bridge board. Another task involved in the thesis was complete re-design of half-bridge. More efficient and robust components were selected for complete re-design. Based on new components and its specifications a new circuit and PCB was designed in Altium Designer. Lab testing was performed to verify the functionality of new Half-bridge.

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Niu, Shiqin. "Conception, optimisation et caractérisation d’un transistor à effet de champ haute tension en Carbure de Silicium." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEI136/document.

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La thèse intitulée "Conception, caractérisation et optimisation d’un transistor à effet de champ haute tension en Carbure de Silicium (SiC) et de leur diode associée", s’est déroulée au sein du laboratoire AMPERE sous la direction du Prof. D. PLANSON. Des premiers démonstrateurs de JFET ont été réalisés. Le blocage du JFET n'est pas efficace, ceci étant lié aux difficultés de réalisation technologique. Le premier travail a consisté en leur caractérisation précise puis en leur simulation, en tenant compte des erreurs de processus de fabrication. Ensuite, un nouveau masque a été dessiné en tenant en compte des problèmes technologiques identifiés. Les performances électriques de la nouvelle génération du composant ont ainsi démontré une amélioration importante au niveau de la tenue en tension. Dans le même temps, de nouveaux problèmes se sont révélés, qu’il sera nécessaire de résoudre dans le cadre de travaux futurs. Par ailleurs, les aspects de tenue en court-circuit des JFETs en SiC commercialement disponibles ont été étudiés finement. Les simulations électrothermiques par TCAD ont révélé les modes de défaillances. Ceci a permis d'établir finalement des modèles physiques valables pour les JFETs en SiC
Silicon carbide (SiC) has higher critical electric field for breakdown and lower intrinsic carrier concentration than silicon, which are very attractive for high power and high temperature power electric applications. In this thesis, a new 3.3kV/20A SiC-4H JFET is designed and fabricated for motor drive (330kW). This breakdown voltage is beyond the state of art of the commercial unipolar SiC devices. The first characterization shows that the breakdown voltage is lower (2.5kV) than its theoretical value. Also the on-state resistance is more important than expected. By means of finite element simulation the origins of the failure are identified and then verified by optical analysis. Hence, a new layout is designed followed by a new generation of SiC-4H JFET is fabricated. Test results show the 3.3kV JFET is developed successfully. Meanwhile, the electro-thermal mechanism in the SiC JFETs under short circuit is studied by means of TCAD simulation. The commercial 1200V SIT (USCi) and LV-JFET (Infineon) are used as sample. A hotspot inside the structures is observed. And the impact the bulk thickness and the canal doping on the short circuit capability of the devices are shown. The physical models validated by this study will be used on our 3.3kV once it is packaged

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Liebig, Sebastian. "Optimization of rectifiers for aviation regarding power density and reliability." Doctoral thesis, Universitätsbibliothek Chemnitz, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-159936.

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The intentions of the so-called "More Electrical Aircraft" (MEA) are higher efficiency and lower weight. A main topic here is the application of electrical instead of hydraulical, pneumatical and mechanical systems. The necessary power electronic devices have intermediate DC-links, which are typically supplied by a three-phase system with active B6 and passive B12 rectifiers. A possible alternative is the B6 diode bridge in combination with an active power filter (APF). Due to the parallel arrangement, the APF offers a higher power density and is able to compensate for harmonics from several devices. The use of the diode bridge rectifier alone is not permitted due to the highly distorted phase current. The following investigations are dealing with the development of an active power filter for a three-phase supply with variable frequency from 360 to 800 Hz. All relevant components such as inductors, EMC-filters, power modules and DC-link capacitor are designed. A particular focus is put on the customized power module with SiC-MOSFETs and SiC-diodes, which is characterized electrically and thermally. The maximum supply frequency slope has a value of 50 Hz/ms, which requires a high dynamic and robustness on the control algorithm. Furthermore, the content of 5th and 7th harmonics must be reduced to less than 2 %, which demands a high accuracy. To cope with both requirements, a two-stage filter algorithm is developed and implemented in two independent signal processors. Simulations and laboratory experiments confirm the performance and robustness of the control algorithm. This work comprehensively presents the design of aerospace rectifiers. The results were published in conferences and patents
Hauptziele des sogenannten "More Electrical Aircraft" (MEA) sind Effizienzerhöhung und Gewichtseinsparung. Ein Schwerpunkt hierbei ist die Nutzung von elektrischen statt hydraulischen, pneumatischen und mechanischen Systemen. Die notwendigen Leistungselektroniken haben DC-Zwischenkreise, welche mittels aktiven B6 und passiven B12 Gleichrichtern aus dem Dreiphasennetz gespeist werden. Eine mögliche Alternative ist die B6 Diodenbrücke in Kombination mit einem aktiven Netzfilter, welcher aufgrund der parallelen Anordnung eine höhere Leistungsdichte aufweist und darüber hinaus mehrere Geräte gleichzeitig entstören kann. Die alleinige Nutzung einer Diodenbrücke ist aufgrund des hohen Anteils von Stromharmonischen nicht zulässig. Diese Arbeit beschäftigt sich mit der Entwicklung eines aktiven Filters für ein Dreiphasensystem mit variabler Frequenz von 360 bis 800 Hz. Es werden alle relevanten Bauteile wie Induktivitäten, EMV-Filter, Leistungsmodule und Zwischenkreiskondensator ausgelegt. Besonderes Augenmerk liegt auf dem kundenspezifischen Modul mit SiC-Dioden und SiCMOSFETs, welches vollständig elektrisch und thermisch charakterisiert wird. Die Änderung der Netzfrequenz beträgt bis zu 50 Hz/ms, was eine hohe Dynamik und Robustheit von der Filterregelung verlangt. Weiterhin ist im statischen Fall eine hohe Genauigkeit gefordert, da die 5. und 7. Harmonische auf unter 2% geregelt werden müssen. Um beiden Anforderungen gerecht zu werden, wird ein zweistufiger Regelungsalgorithmus entwickelt der auf zwei digitalen Signalprozessoren implementiert wird. Simulationen und Labormessungen bestätigen die Robustheit des Regelungskonzeptes. Diese Arbeit stellt umfassend die Entwicklung von Luftfahrtgleichrichtern dar. Die Ergebnisse wurden in Konferenzen und Patenten veröffentlicht

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33

Xiangxiang, Fang. "Characterization and Modeling of SiC Power MOSFETs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1354687371.

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34

Liebig, Sebastian. "Optimization of rectifiers for aviation regarding power density and reliability." Doctoral thesis, Universitätsverlag der Technischen Universität Chemnitz, 2014. https://monarch.qucosa.de/id/qucosa%3A20187.

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The intentions of the so-called "More Electrical Aircraft" (MEA) are higher efficiency and lower weight. A main topic here is the application of electrical instead of hydraulical, pneumatical and mechanical systems. The necessary power electronic devices have intermediate DC-links, which are typically supplied by a three-phase system with active B6 and passive B12 rectifiers. A possible alternative is the B6 diode bridge in combination with an active power filter (APF). Due to the parallel arrangement, the APF offers a higher power density and is able to compensate for harmonics from several devices. The use of the diode bridge rectifier alone is not permitted due to the highly distorted phase current. The following investigations are dealing with the development of an active power filter for a three-phase supply with variable frequency from 360 to 800 Hz. All relevant components such as inductors, EMC-filters, power modules and DC-link capacitor are designed. A particular focus is put on the customized power module with SiC-MOSFETs and SiC-diodes, which is characterized electrically and thermally. The maximum supply frequency slope has a value of 50 Hz/ms, which requires a high dynamic and robustness on the control algorithm. Furthermore, the content of 5th and 7th harmonics must be reduced to less than 2 %, which demands a high accuracy. To cope with both requirements, a two-stage filter algorithm is developed and implemented in two independent signal processors. Simulations and laboratory experiments confirm the performance and robustness of the control algorithm. This work comprehensively presents the design of aerospace rectifiers. The results were published in conferences and patents.
Hauptziele des sogenannten "More Electrical Aircraft" (MEA) sind Effizienzerhöhung und Gewichtseinsparung. Ein Schwerpunkt hierbei ist die Nutzung von elektrischen statt hydraulischen, pneumatischen und mechanischen Systemen. Die notwendigen Leistungselektroniken haben DC-Zwischenkreise, welche mittels aktiven B6 und passiven B12 Gleichrichtern aus dem Dreiphasennetz gespeist werden. Eine mögliche Alternative ist die B6 Diodenbrücke in Kombination mit einem aktiven Netzfilter, welcher aufgrund der parallelen Anordnung eine höhere Leistungsdichte aufweist und darüber hinaus mehrere Geräte gleichzeitig entstören kann. Die alleinige Nutzung einer Diodenbrücke ist aufgrund des hohen Anteils von Stromharmonischen nicht zulässig. Diese Arbeit beschäftigt sich mit der Entwicklung eines aktiven Filters für ein Dreiphasensystem mit variabler Frequenz von 360 bis 800 Hz. Es werden alle relevanten Bauteile wie Induktivitäten, EMV-Filter, Leistungsmodule und Zwischenkreiskondensator ausgelegt. Besonderes Augenmerk liegt auf dem kundenspezifischen Modul mit SiC-Dioden und SiCMOSFETs, welches vollständig elektrisch und thermisch charakterisiert wird. Die Änderung der Netzfrequenz beträgt bis zu 50 Hz/ms, was eine hohe Dynamik und Robustheit von der Filterregelung verlangt. Weiterhin ist im statischen Fall eine hohe Genauigkeit gefordert, da die 5. und 7. Harmonische auf unter 2% geregelt werden müssen. Um beiden Anforderungen gerecht zu werden, wird ein zweistufiger Regelungsalgorithmus entwickelt der auf zwei digitalen Signalprozessoren implementiert wird. Simulationen und Labormessungen bestätigen die Robustheit des Regelungskonzeptes. Diese Arbeit stellt umfassend die Entwicklung von Luftfahrtgleichrichtern dar. Die Ergebnisse wurden in Konferenzen und Patenten veröffentlicht.

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35

Fayyaz, Asad. "Performance and robustness characterisation of SiC power MOSFETs." Thesis, University of Nottingham, 2018. http://eprints.nottingham.ac.uk/48937/.

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Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics.

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Španěl, Petr. "Spínané zdroje." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-433024.

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This thesis deals with switched mode power supplies based on resonant principle to achieve high efficiency. Several ways of switched mode power supplies optimalisation are described as part of the work to achieve better efficiency. Priparily, the new generation of switching elements based on SiC and resonant topology are used to achieve significant switching loss minimization. The selected resonant topology is simualted in detail and then built with focus on high efficiency. The main content of the work consists in the design and realization of the switched mode power supply with selected control algorithms and their comparison. The problems associated with usage of new SiC MOSFET generation in TO-247-4L package are being solved within the design and implementation of the power source. To solve the main problems, new 3rd SiC MOSFET gate driver was developer for working with switching frequencies in hundreds of kHz and resisting very high voltage stress on the controlled transistor. The next part of the gate driver is the overcurrent protection. The overcurrent limit can be set easily by changing one component. This protection reacts very quickly in hundreds of nanoseconds, so it is capable of saving the converter even in branch failure and going to hard short circuit. The functional sample of the series resonant converter was built and revated in the work. The converter based on 3. Generation of SiC MOSFET transistors from Cree in a modern case TO-247-4L was built. For this inverter, it was also necessary to develop both the control scheme and the resonance frequency tracking to achieve accurate switching and thus achieve the use of the resonant principle of the converter to the maximum extent possible. The result of this work is up to 3 kW converter with adjustable output voltage while maintaining high efficiency up to 96%.

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Rong, Hua. "Development of 4H-SiC power MOSFETs for high voltage applications." Thesis, University of Warwick, 2015. http://wrap.warwick.ac.uk/79426/.

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Silicon carbide is a promising wide bandgap semiconductor for high-power, high-temperature and high frequency devices, owing to its high breakdown electric field strength, high thermal conductivity and ability to grow high quality SiO2 layers by thermal oxidation. Although the SiC power MOSFET (metal-oxide-semiconductor field effect transistor) is preferred as a power switch, it has suffered from low channel mobility with only single digit field effect mobility achieved using standard oxidation process (1200◦C thermal oxidation). As such, this thesis is focussed on the development of 4H-SiC MOSFETs (both lateral and vertical MOSFETs) to improve the channel mobility and breakdown characteristics of these devices. In this work, high temperature nitridation using N2O has been investigated on MOS capacitors and MOSFETs, both with gate oxides grown directly in N2O environment or in a O2 ambient followed by a N2O post-oxidation annealing process. Results have demonstrated that at high temperature (>1200◦C) there is a significant improvement in the interface trap density to as low as (1.5x10^11cm-2eV-1) and field effect channel mobility (19cm2/V.s) of 4H-SiC MOSFET compare with a lower temperature (between 800 and 1200◦C) oxidation (1x10^12cm-2eV-1 and 4cm2/V.s). Nitridation temperatures of 1300◦C was found to be the most effective method for increasing the field effect channel mobility and reducing threshold voltage. The number of working devices per sample also increased after N2O nitridation at 1300◦C as observed for both lateral and vertical MOSFETs. Other post oxidation techniques have also been investigated such as phosphorous passivation using solid SiP2O7 planar diffusion source (PDS). The peak value of the field effect mobility for 4H-SiC MOSFET after phosphorus passivation is approximately 80cm2/V.s, which is four times more than the valued obtained using high temperature N2O annealing. Different JTE structures have been designed and simulated including single-zone JTE, space modulated JTE (SMJTE) and the novel two-step mesa JTE structures. It was found that for the same doping concentration the SM two-zone JTE and SMJTE have higher breakdown voltage than the single zone JTE. With SMJTE, the device could achieve more than 90% of the ideal parallel plane voltage from simulations and 86% from the breakdown test of the fabricated devices.

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Marzoughi, Alinaghi. "Investigating Impact of Emerging Medium-Voltage SiC MOSFETs on Medium-Voltage High-Power Applications." Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/81822.

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For decades, the Silicon-based semiconductors have been the solution for power electronics applications. However, these semiconductors have approached their limits of operation in blocking voltage, working temperature and switching frequency. Due to material superiority, the relatively-new wide-bandgap semiconductors such as Silicon-Carbide (SiC) MOSFETs enable higher voltages, switching frequencies and operating temperatures when compared to Silicon technology, resulting in improved converter specifications. The current study tries to investigate the impact of emerging medium-voltage SiC MOSFETs on industrial motor drive application, where over a quarter of the total electricity in the world is being consumed. Firstly, non-commercial SiC MOSFETs at 3.3 kV and 400 A rating are characterized to enable converter design and simulation based on them. In order to feature the best performance out of the devices under test, an intelligent high-performance gate driver is designed embedding required functionalities and protections. Secondly, total of three converters are targeted for industrial motor drive application at medium-voltage and high-power range. For this purpose the cascaded H-bridge, the modular multilevel converter and the 5-L active neutral point clamped converters are designed at 4.16-, 6.9- and 13.8 kV voltage ratings and 3- and 5 MVA power ratings. Selection of different voltage and power levels is done to elucidate variation of different parameters within the converters versus operating point. Later, comparisons are done between the surveyed topologies designed at different operating points based on Si IGBTs and SiC MOSFETs. The comparison includes different aspects such as efficiency, power density, semiconductor utilization, energy stored in converter structure, fault containment, low-speed operation capability and parts count (for a measure of reliability). Having the comparisons done based on simulation data, an H-bridge cell is implemented using 3.3 kV 400 A SiC MOSFETs to evaluate validity of the conducted simulations. Finally, a novel method is proposed for series-connecting individual SiC MOSFETs to reach higher voltage devices. Considering the fact that currently the SiC MOSFETs are not commercially available at voltages higher above 1.7 kV, this will enable implementation of converters using medium-voltage SiC MOSFETs that are achieved by stacking commercially-available 1.7 kV MOSFETs. The proposed method is specifically developed for SiC MOSFETs with high dv/dt rates, while majority of the existing solutions could only work merely with slow Si-based semiconductors.
Ph. D.

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Akram, Farhan. "Gate driver solutions for high power density SMPS using Silicon Carbide MOSFETs." Thesis, Mittuniversitetet, Institutionen för elektronikkonstruktion, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41188.

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Discrete silicon carbide (SiC) power devices have unique characteristics that outpace those of silicon (Si) counterparts. The improved physical features have provided better faster switching, greater current densities, lower on-resistance, and temperature performances. However, there is lack of suitable commercial gate drivers that are compatible for high-voltage, and high-speed devices. There has been a great research effort required for the advancement of gate drivers for high voltage SiC transistors. A drive circuit for a SiC MOSFET needs to be optimized in normal operation to give best efficiency and same drive circuit should secure the MOSFET under unsuitable conditions. To ensure the rapid switching of these advanced SiC MOSFETs, a gate driver capable of providing the high current capability is required. In this work, three different high-power-density, high-speed, and high-noise-immunity gate driver modules for 10 kV SiC MOSFET were built and optimized. Double-pulse test was developed for the dynamic characterization of SiC MOSFETs and gate drivers. This setup provided clean measurements of DUT voltage and current under well-defined conditions and correlated to simulation results. Designed gate drivers have thoroughly investigated to test and compare it with our future design. The influential parameters such as dV/dt, dI/dt, and gate driving capability of gate driver were adjusted according to the requirements. The short circuit protection test was performed to check the reliability of driver modules in worst conditions. Furthermore, a DC-DC converter was designed and tested with the advanced gate drivers. The driver modules were tested in designed converter under different load conditions and influential parameters were successfully demonstrated. The driver modules effectively helped in reducing the EMI and switching losses. These designed gate drivers and prototype converter provide all the attractive features and can be widely implemented in industrial applications for energy efficient systems.

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Gopalakrishna, Keshava. "Frequency Characterization of Si, SiC,and GaN MOSFETs Using Buck ConverterIn CCM as an Application." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1387661422.

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Gill, Lee. "Evaluation and Development of Medium-Voltage Converters Using 3.3 kV SiC MOSFETs for EV Charging Application." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/93976.

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The emergence of wide-bandgap-based (WBG) devices, such as silicon carbide (SiC) and gallium nitride (GaN), have unveiled unprecedented opportunities, enabling the realization of superior power conversion systems. Among the potential areas of advancement are medium-voltage (MV) and high-voltage (HV) applications, due to the growing demand for high-power-density and high-efficiency power electronics converters. These advancements have propelled a wide adoption of electric vehicles (EV), which in the future will require great improvements in the charging time of these vehicles. Thereby, this thesis attempts to address such a challenge and bring about technological improvements, enabling faster, more efficient, and more effective ways of charging an electric vehicle through the application of MV 3.3 kV SiC MOSFETs. The current fast-charging solution involves heavy and bulky MV-LV transformers, which add installation complexity for EV charging stations. However, this thesis presents an alternative power-delivery solution utilizing an MV dual-active-bridge (DAB) converter. The proposed architecture is designed to directly interface with the MV grid for high-power, fast-charging capabilities while eliminating the need for an installation of the MV-LV transformer. The MV DAB converter utilizes 3.3 kV SiC MOSFETs to realize the next 800 V EV charging system, along with an extended zero-voltage-switching (ZVS) scheme, in order to provide an efficient charging strategy across a wide range of battery voltage levels. Lastly, a detailed design comparison analysis of an MV Flyback converter, targeted for the auxiliary power supply for the proposed MV EV charging architecture, is presented.
The field of power electronics, which controls and manages the conversion of electrical energy, is an important topic of discussion, as new technologies like electric vehicles (EV) are quickly emerging and disrupting the current status-quo of vehicle-choice. In order to promote timely and extensive adoption of such an enabling EV technology, it is critical to understand the current challenges involving EV charging stations and seek out opportunities to engender future innovations. Indeed, wide-bandgap (WBG) devices, such as silicon carbide (SiC) and gallium nitride (GaN), have unveiled unprecedented opportunities in enabling the realization of superior power conversion systems. Thus, utilizing these WGB devices in EV charging applications can bring about improved design and development of EV fast chargers that are faster-charging, more efficient, and more effective. Hence, this thesis presents an opportunity in EV charging station applications with the utilization of medium-voltage SiC MOSFETs. Because the current fast-charging solution involves a heavy and bulky transformer, it adds installation complexity for EV charging stations. However, this thesis presents an alternative power-delivery solution that could potentially provide an efficient and fast-charging mechanism of EVs while reducing the size of EV chargers. All things considered, this thesis provides in-depth evaluation-studies of medium-voltage 3.3 kV SiC MOSFET-based power converters, targeted for future fast EV charging applications. The development and design of the hardware prototype is presented in this thesis, along with testing and verification of experimental results.

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Ohn, Sungjae. "Circuits and Modulation Schemes to Achieve High Power-Density in SiC Grid-connected Converters." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/89550.

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The emergence of silicon-carbide (SiC) devices has been a 'game changer' in the field of power electronics. With desirable material properties such as low-loss characteristics, high blocking voltage, and high junction temperature operation, they are expected to drastically increase the power density of power electronics systems. Recent state-of-the-art designs show the power density over 17 ; however, certain factors limit the power density to increase beyond this limit. In this dissertation, three key factors are selected to increase the power density of SiC-based grid-connected three-phase converters. Throughout this dissertation, the techniques and strategies to increase the power density of SiC three-phase converters were investigated. Firstly, a magnetic integration method was introduced for the coupled inductors in the interleaved three-phase converters. Due to limited current-capacity compared to the silicon insulated-gate bipolar transistors (Si-IGBTs), discrete SiC devices or SiC modules, operate in parallel to handle a large current. When three-phase inverters are paralleled, interleaving can be used, and coupled inductors are employed to limit the circulating current. In Chapter 2, the conventional integration method was extended to integrate three coupled inductors into two; one for differential-mode circulating current and the other for common-mode circulating current. By comparing with prior research work, a 20% reduction in size and weight is demonstrated. From Chapter 3 to Chapter 5, a full-SiC uninterruptible power supply (UPS) was investigated. With the high switching frequency and fast switching dynamics of SiC devices, strategies on electromagnetic inference become more important, compared to Si-IGBT based inverters. Chapter 3 focuses on a common-mode equivalent circuit model for a topology and pulse width modulation (PWM) scheme selection, to set a noise mitigation strategy in the design phase. A three terminal common-mode electromagnetic interference (EMI) model is proposed, which predicts the impact of the dc-dc stage and a large battery-rack on the output CM noise. Based on the model, severe deterioration of noise by the dc-dc stage and battery-rack can be predicted. Special attention was paid on the selection of the dc-dc stage's topology and the PWM scheme to minimize the impact. With the mitigation strategy, a maximum 16 dB reduction on CM EMI can be achieved for a wide frequency range. In Chapter 4, an active PWM scheme for a full-SiC three-level back-to-back converter was proposed. The PWM scheme targets the size reduction of two key components: dc-link capacitors and a common-mode EMI filter. The increase in switching frequency calls for a large common-mode EMI filter, and dc-link capacitors in the three-level topology may take a considerable portion in the total volume. To reduce the common-mode noise emission, different combinations of the voltage vectors are investigated to generate center-aligned single pulse common-mode voltage. By such an alignment of common-mode voltage with different vector combinations, noise cancellation between the rectifier and the inverter can be maximally utilized, while the balancing of neutral point voltage can be achieved by the transition between the combinations. Also, to reduce the size of the dc-link capacitor for the three-level back-to-back converter, a compensation algorithm for neutral point voltage unbalance was developed for both differential-mode voltage and the common-mode voltage of the ac-ac stage. The experimental results show a 4 dB reduction on CM EMI, which leads to a 30% reduction on the required CM inductance value. When a 10% variation of neutral point voltage can be handled, the dc-link capacitance can be reduced by 56%. In Chapter 5, a 20 kW full-SiC UPS prototype was built to demonstrate a possible size-reduction with the proposed PWM scheme, as well as a selection of topologies and PWM schemes based on the model. The power density and efficiency are compared with the state-of-the-art Si-IGBT based UPSs. Chapter 6 seeks to improve power density by a change in a modulation method. Triangular conduction mode (TCM) operation of the three-level full-SiC inverter was investigated. The switching loss of SiC devices is reported to be concentrated on the turn-on instant. With zero-voltage turn-on of all switches, the switching frequency of a three-level three-phase SiC inverter can be drastically increased, compared to the hard-switching operation. This contributes to the size-reduction of the filter inductors and EMI filters. Based on the design to achieve a 99% peak efficiency, a comparison was made with a full-SiC three-level inverter, operating in continuous conduction mode (CCM), to verify the benefit of the soft switching scheme on the power density. A design procedure for an LCL filter of paralleled TCM inverters was developed. With 3.5 times high switching frequency, the total weight of the filter stage of the TCM inverter can be reduced by 15%, compared to that of the CCM inverter. Throughout this dissertation, techniques for size reduction of key components are introduced, including coupled inductors in parallel inverters, an EMI filter, dc-link capacitors, and the main boost inductor. From Chapter 2 to 5, the physical size or required value of these key components could be reduced by 20% to 56% by different schemes such as magnetic integration, EMI mitigation strategy through modeling, and an active PWM scheme. An optimization result for a full-SiC UPS showed a 40% decrease in the total volume, compared to the state-of-the-art Si-IGBT solution. Soft-switching modulation for SiC-based three-phase inverters can bring a significant increase in the switching frequency and has the potential to enhance power-density notably. A three-level three-phase full-SiC 40 kW PV inverter with TCM operation contributed to a 15% reduction on the filter weight.
Doctor of Philosophy
The power density of a power electronics system is regarded as an indicator of technological advances. The higher the power density of the power supply, the more power it can generate with the given volume and weight. The size requirement on power electronics has been driven towards tighter limits, as the dependency on electric energy increases with the electrification of transportation and the emergence of grid-connected renewable energy sources. However, the efficiency of a power electronics system is an essential factor and is regarded as a trade-off with the power density. The size of power electronics systems is largely impacted by its magnetic components for filtering, as well as its cooling system, such as a heatsink. Once the switching frequency of power semiconductors is increased to lower the burden on filtering, more loss is generated from filters and semiconductors, thus enlarging the size of the cooling system. Therefore, considering the efficiency has to be maintained at a reasonable value, the power density of Si-based converters appears to be saturated. With the emergence of wide-bandgap devices such as silicon carbide (SiC) or gallium nitride (GaN), the switching frequency of power devices can be significantly increased. This is a result of superior material properties, compared to Si-based power semiconductors. For grid-connected applications, SiC devices are adopted, due to the limitations of voltage ratings in GaN devices. Before commercial SiC devices were available, the power density of SiC- based three-phase inverters was expected to go over 20 𝑘𝑊 𝑑𝑚3 ⁄ . However, the state-of-the art designs shows the power density around 3 ~ 4 𝑘𝑊 𝑑𝑚3 ⁄ , and at most 17 𝑘𝑊 𝑑𝑚3 ⁄ . The SiC devices could increase the power density, but they have not reached the level expected. The adoption of SiC devices with faster switching was not a panacea for power density improvement. This dissertation starts with an analysis of the factors that prevent power density improvement of SiC-based, grid-connected, three-phase inverters. Three factors were identified: a limited increase in the switching frequency, large high-frequency noise generation to be filtered, and smaller but still significant magnetic components. Using a generic design procedure for three-phase inverters, each chapter seeks to frame a strategy and develop techniques to enhance the power density. For smaller magnetic components, a magnetic integration scheme is proposed for paralleled ac-dc converters. To reduce the size of the noise filter, an accurate modeling approach was taken to predict the noise phenomena during the design phase. Also, a modulation scheme to minimize the noise generation of the ac-ac stage is proposed. The validity of the proposed technique was verified by a full-SiC three-phase uninterruptible power supply with optimized hardware design. Lastly, the benefit of soft-switching modulation, which leads to a significant increase in switching frequency, was analyzed. The hardware optimization procedure was developed and compared to hard-switched three-phase inverters.

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Beydoun, Bilal. "Simulation et conception des transistors M. O. S. De puissance." Toulouse 3, 1994. http://www.theses.fr/1994TOU30163.

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Ce mémoire traite de la simulation et de la conception du transistor VDMOS de puissance. On propose un outil de conception de modèles pour ce transistor, qui est base d'une part sur l'analyse des mécanismes dont la structure est le siège, d'autre part sur la géométrie (layout) et la technologie, et enfin sur la prise en compte de la topologie d'un schéma équivalent établi antérieurement au laboratoire. Plus précisément, on effectue tout d'abord une étude des mécanismes-conduction, tenue en tension, étude dynamique-intervenant dans les diverses zones de la structure du composant. En se basant sur les aspects de modélisation antérieurement développes au LAAS, nous proposons ensuite une nouvelle méthodologie de conception des modèles VDMOS. Celle-ci prend en compte les équations de fonctionnement, le dessin des masques, la technologie et les lois de dépendance entre les paramètres. Pour ce faire, nous développons un logiciel nomme power mosfet's designer qui permet à partir des données de la physique, de la géométrie et de la technologie de la structure, de générer le modèle VDMOS et de connaitre les performances électriques du dispositif dans une application de circuit spécifiée a priori. On procède ensuite à la validation de ce logiciel sur des composants industriels. On l'applique à l'étude de nouvelles générations de structures VDMOS telles que le transistor VDMOS à double niveau d'oxyde de grille intercellulaire. Un exemple d'analyse spéculative du transistor VDMOS élaboré sur un autre matériau que le silicium est enfin proposé : on étudie le cas où le substrat est en carbure de silicium (sic)

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Eial, Awwad Abdullah [Verfasser], Sibylle [Akademischer Betreuer] Dieckerhoff, Sibylle [Gutachter] Dieckerhoff, Regine [Gutachter] Mallwitz, and Uwe [Gutachter] Schäfer. "On the perspectives of SiC MOSFETs in high-frequency and high-power isolated DC/DC converters / Abdullah Eial Awwad ; Gutachter: Sibylle Dieckerhoff, Regine Mallwitz, Uwe Schäfer ; Betreuer: Sibylle Dieckerhoff." Berlin : Technische Universität Berlin, 2018. http://d-nb.info/116832405X/34.

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Chih-Pan, Yang, and 楊志潘. "Investigation of Device Structure and Application of SiC Power MOSFET." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/zbqtv3.

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碩士
國立交通大學
電子工程系所
92
The basic structure of power MOSFET consists of an epitaxial layer for voltage blocking and a drain electrode at the substrate contact. In the conventional double diffused MOSFET, the poor channel resistance and JFET effect limited the DIMOS performance. The trench gate MOSFET, have a much improved on-resistance and packing density because of its vertical channel, however, a high local electric field at the trench corner is of critical importance to the performance of the device. A innovative structure of SiC accumulation-mode MOSFET designed to improve the performance of conventional structure of power MOSFET. This thesis focused on the design of high voltage MOSFET on SiC power devices. Parameter extraction for 4H-SiC MOS devices is the main focus for this thesis, which includes the mobility parameter extraction. Detailed analysis of the important design parameters of the innovative structure is performed using MEDICI with the parameter been used in calibration process.

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(11184465), Madankumar Sampath. "Deeply-Scaled Fully Self-Aligned Trench MOSFETs in 4H-SiC." Thesis, 2021.

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Increasing demand for higher power density in many applications such as Hybrid Electric Vehicles (HEVs) and renewable power generation has led to great technological advances in power electronics. To meet this increasing demand, a power semiconductor device needs to have low on resistance, increased switching speeds and reduced total system cost. Silicon (Si) power devices have been used for several decades but they are fundamentally limited by material properties. Silicon carbide (SiC) as a power semiconductor material offers superior electrical and thermal properties compared to silicon, which it can replace in a large spectrum of applications. Because of a lower critical electric field, drift regions in Si power transistors need to be much thicker and more lightly doped, which in turn increases the specific onresistance Ron,sp. To combat the drift resistance component for higher blocking voltages, superjunction MOSFETs for medium voltages and Si IGBTs for high voltages are used. Since IGBTs are bipolar transistors, they exhibit much higher switching energy losses than MOSFETs. The SiC MOSFET is an excellent candidate in the medium to high voltage range, which mainly targets the HEV market.

Due to their low channel mobility, SiC MOSFETs have not reached the theoretical limit below 1200 V where channel resistance is dominant. Planar DMOSFETs dominate the

commercial SiC market today because of higher yield and relatively simpler fabrication process, but trench MOSFETs can be made with a smaller cell area and thus lower Ron,sp. Due to lower cell-pitch and high integration density of trench-gate devices, they offer an opportunity to reduce the size and weight of HEV power control units by replacing IGBTs with MOSFETs. The single-trench UMOSFET was first reported in 1994 by CREE and the first oxide protected trench MOSFET in 1998 by Purdue. This structure inserts a grounded p-type region below the gate trench to protect the oxide in the blocking state. In 2012, Rohm Semiconductor reported a novel double-trench UMOSFET with separate gate and

field-protection trenches. In 2017, Infineon published their new trench UMOSFET, known as Cool-SiC, with high gate oxide reliability. In this work a deeply-scaled, fully-self-aligned trench MOSFET is fabricated and characterized. The innovative process described enables a record cell-pitch of 0.5 μm per channel, equivalent to a channel density 6Å~ higher than currently available commercial UMOSFETs.

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(9115403), Rahul Padavagodu ramamurthy. "VERTICAL TRIGATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR IN 4H - SILICON CARBIDE." Thesis, 2020.

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Advances in modern technology and recent demand for high power applications have motivated great interest in power electronics. Power semiconductor devices are key components that have enabled significant advances in power electronic systems. Historically, silicon has been the material of choice for power semiconductor devices such as diodes, transistors and thyristors. However, silicon devices are now reaching their fundamental limits, and a transition to wide bandgap semiconductors is critical to make further progress in the field. Among them, SiC (silicon carbide) has attracted increasing attention as a power semiconductor to replace silicon due to its superior properties and technological maturity. In fact, SiC power MOSFETs have been commercially available since 2011, and are actively replacing their silicon counterparts at blocking voltages above 1 kV. At these voltages, the specific on-resistance of SiC MOSFETs is 200-300x lower than that of silicon devices. However, conventional vertical SiC MOSFETs are still far from their theoretical performance at blocking voltages below 2 kV. In this regime, the channel resistance is the dominant limitation due to the relatively low channel mobility at the SiO2/4H-SiC MOS interface.

In this thesis, the first successful demonstration of a novel power device in 4H-SiC called the trigate power DMOSFET (double diffused metal oxide semiconductor field effect transistor) is presented. This device reduces the channel resistance by a factor of 3-5× compared with the state-of-art commercial power DMOSFETs, without requiring an increase in the channel mobility. The trigate structure is applied to a power MOSFET for the first time along with a self-aligned short channel process. This new structure utilizes both the conventional horizontal surface as well as the sidewalls of a trench to increase the effective width of the channel without increasing the device area. Conceptual design, optimization, process development and electrical results are presented. The trigate power MOSFET with a trench depth of 1 μm designed for a blocking voltage of 650 V has a specific on-resistance of 1.98 mΩcm²and a channel resistance of 0.67 mΩcm².This corresponds to a ∼2× reduction in the total specific on-resistance, and a 3.3× reduction in the specific channel resistance as compared to a conventional DMOSFET with the same blocking voltage rating. This demonstration is a landmark that could help SiC technology compete successfully in the lower blocking voltage regime below 600 V, and access for the first time a completely new segment in the power electronics application space.

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MAZZA, BRUNA. "Defects and traps electrical characterization in 4H-SiC PowerMOSFET." Doctoral thesis, 2021. http://hdl.handle.net/11570/3214439.

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In this thesis work, the methods used to investigate Silicon Carbide defects and the energy levels associated with them are presented. Different measurement methods will be presented to characterize the so-called "fixed charges" in gate oxide and "interface charges" in SiO2/SiC interface in 4H-SiC power MOSFET devices. These methods are effective both to be able to identify these charges, which are nothing more than defects in the material, such as the Capacitance-Voltage (CV) and conductance (GV) techniques, and to be able to qualify SiC devices in terms of reliability, for example Time Dependent Dielectric Breakdown (TDDB) test.

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"High Power Density, High Efficiency Single Phase Transformer-less Photovoltaic String Inverters." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.45041.

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abstract: Two major challenges in the transformer-less, single-phase PV string inverters are common mode leakage currents and double-line-frequency power decoupling. In the proposed doubly-grounded inverter topology with innovative active-power-decoupling approach, both of these issues are simultaneously addressed. The topology allows the PV negative terminal to be directly connected to the neutral, thereby eliminating the common-mode ground-currents. The decoupling capacitance requirement is minimized by a dynamically-variable dc-link with large voltage swing, allowing an all-film-capacitor implementation. Furthermore, the use of wide-bandgap devices enables the converter operation at higher switching frequency, resulting in smaller magnetic components. The operating principles, design and optimization, and control methods are explained in detail, and compared with other transformer-less, active-decoupling topologies. A 3 kVA, 100 kHz single-phase hardware prototype at 400 V dc nominal input and 240 V ac output has been developed using SiC MOSFETs with only 45 μF/1100 V dc-link capacitance. The proposed doubly-grounded topology is then extended for split-phase PV inverter application which results in significant reduction in both the peak and RMS values of the boost stage inductor current and allows for easy design of zero voltage transition. A topological enhancement involving T-type dc-ac stage is also developed which takes advantage of the three-level switching states with reduced voltage stress on the main switches, lower switching loss and almost halved inductor current ripple. In addition, this thesis also proposed two new schemes to improve the efficiency of conventional H-bridge inverter topology. The first scheme is to add an auxiliary zero-voltage-transition (ZVT) circuit to realize zero-voltage-switching (ZVS) for all the main switches and inherent zero-current-switching (ZCS) for the auxiliary switches. The advantages include the provision to implement zero state modulation schemes to decrease the inductor current THD, naturally adaptive auxiliary inductor current and elimination of need for large balancing capacitors. The second proposed scheme improves the system efficiency while still meeting a given THD requirement by implementing variable instantaneous switching frequency within a line frequency cycle. This scheme aims at minimizing the combined switching loss and inductor core loss by including different characteristics of the losses relative to the instantaneous switching frequency in the optimization process.
Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2017

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50

(11184600), Md monzurul Alam. "The Design, Fabrication, and Characterization of Waffle-substrate-based n-channel IGBTs in 4H-SiC." Thesis, 2021.

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Power semiconductor devices play an important role in many areas, including household

appliances, electric vehicles, high speed trains, electric power stations, and renewable energy

conversion. In the modern era, silicon based devices have dominated the semiconductor

market, including power electronics, because of their low cost and high performance. The

applications of devices rated 600 V - 6.5 kV are still dominated by silicon devices, but they

are nearly reaching fundamental material limits. New wide band gap materials such as silicon

carbide (SiC) offer significant performance improvements due to superior material properties

for such applications in and beyond this voltage range. 4H-SiC is a strong candidate

among other wide band gap materials because of its high critical electric field, high thermal

conductivity, compatibility with silicon processing techniques, and the availability of high

quality conductive substrates.

Vertical DMOSFETs and insulated gate bipolar transistors (IGBT) are key devices for

high voltage applications. High blocking voltages require thick drift regions with very light

doping, leading to specific on-resistance (R_ON,SP ) that increases with the square of blocking

voltage (V_BR). In theory, superjunction drift regions could provide a solution because of a

linear dependence of R_ON,SP on V_BR when charge balance between the pillars is achieved

through extremely tight process control. In this thesis, we have concluded that superjunction

devices inevitably have at least some level of charge imbalance which leads to a quadratic

relationship between V_BR and R_ON,SP . We then proposed an optimization methodology to

achieve improved performance in the presence of this inevitable imbalance.

On the other hand, an IGBT combines the benefits of a conductivity modulated drift

region for significantly reduced specific on-resistance with the voltage controlled input of a

MOSFET. Silicon carbide n-channel IGBTs would have lower conduction losses than equivalent

DMOSFETs beyond 6.5 kV, but traditionally have not been feasible below 15 kV. This

is due to the fact that the n+ substrate must be removed to access the p+ collector of the

IGBT, and devices below 15 kV have drift layers too thin to be mechanically self-supporting.

In this thesis, we have demonstrated the world’s first functional 10 kV class n-IGBT with

a waffle substrate through simulation, process development, fabrication and characterization.

The waffle substrate would provide the required mechanical support for this class of devices.

The fabricated IGBT has exhibited a differential R_ON,SP of 160 mohm

.cm², less than half of

what would be expected without conductivity modulation. An extensive fabrication process

development for integrating a waffle substrate into an active IGBT structure is described

in this thesis. This process enables an entirely new class of moderate voltage SiC IGBTs,

opening up new applications for SiC power devices.

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