Journal articles: 'Sequential logic circuits'

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JAHANIRAD, HADI, and KARIM MOHAMMADI. "SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS." Journal of Circuits, Systems and Computers 21, no. 05 (August 2012): 1250040. http://dx.doi.org/10.1142/s0218126612500405.

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Reliability analysis using error probabilities for combinational logic circuits has been investigated widely in the literature. Reliability analysis for sequential logic circuits using these methods would be inaccurate because of existence of loops in their architecture. In this paper a new method based on conversion of sequential circuit to combinational one and applying an iterative reliability analysis is developed. A Monte Carlo method-based reliability analysis is introduced for sequential circuits, which is used for first method validation. Experimental results demonstrate good accuracy of the method.

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Watt, A. "Astables and sequential logic circuits." Electronics Education 1990, no. 2 (1990): 7–8. http://dx.doi.org/10.1049/ee.1990.0021.

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Andrews, Lauren B., Alec A. K. Nielsen, and Christopher A. Voigt. "Cellular checkpoint control using programmable sequential logic." Science 361, no. 6408 (September 20, 2018): eaap8987. http://dx.doi.org/10.1126/science.aap8987.

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Biological processes that require orderly progression, such as growth and differentiation, proceed via regulatory checkpoints where the cell waits for signals before continuing to the next state. Implementing such control would allow genetic engineers to divide complex tasks into stages. We present genetic circuits that encode sequential logic to instructEscherichia colito proceed through a linear or cyclical sequence of states. These are built with 11 set-reset latches, designed with repressor-based NOR gates, which can connect to each other and sensors. The performance of circuits with up to three latches and four sensors, including a gated D latch, closely match predictions made by using nonlinear dynamics. Checkpoint control is demonstrated by switching cells between multiple circuit states in response to external signals over days.

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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.

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Basu, Shaunak, and Subhashree Basu. "Reversible Logic Synthesis of Sequential Circuits." International Journal of Computer Applications 129, no. 11 (November 17, 2015): 29–32. http://dx.doi.org/10.5120/ijca2015906999.

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Zhang, Li Min, Zhi Wei Yang, Yao Kun Pang, Tao Zhou, Chi Zhang, and Zhong Lin Wang. "Tribotronic triggers and sequential logic circuits." Nano Research 10, no. 10 (June 14, 2017): 3534–42. http://dx.doi.org/10.1007/s12274-017-1564-9.

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Levin, Iliya, Osnat Keren, and Vladimir Ostrovsky. "Synthesis of sequential circuits by using linearization." Facta universitatis - series: Electronics and Energetics 20, no. 3 (2007): 461–77. http://dx.doi.org/10.2298/fuee0703461l.

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The paper deals with synthesis of sequential circuits defined by their algorithmic state machine notation. Such circuits have a number of specific properties which enable efficient design of the circuits by utilizing so-called linearization techniques. A typical linearization technique includes calculation of autocorrelation values for a system of logic functions corresponding to the circuit. For the mentioned sequential circuits, the calculations which usually require massive computational recourses may be significantly reduced and thus low-overhead implementations of the circuits can be obtained relatively easy. The paper introduces a novel architecture of so-called linearized sequential circuits, and a piece-wise linearization approach for synthesis of sequential circuits. Results are evaluated both analytically and by using a number of standard benchmarks.

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Jagadeesan, Neeraja, B. Saman, M. Lingalugari, P. Gogna, and F. Jain. "Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs." International Journal of High Speed Electronics and Systems 24, no. 03n04 (September 2015): 1550011. http://dx.doi.org/10.1142/s0129156415500111.

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The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

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MONTEIRO, JOSÉ, SRINIVAS DEVADAS, and ABHIJIT GHOSH. "RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 323–40. http://dx.doi.org/10.1142/s0129156496000141.

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Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the circuit. We give an exact method of estimating power in pipelined sequential circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of circuits.

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Hudli, Anand V., and Raghu V. Hudli. "Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits." VLSI Design 2, no. 1 (January 1, 1994): 69–80. http://dx.doi.org/10.1155/1994/94514.

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Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

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Shieh, M. D., C. L. Wey, and P. D. Fisher. "Fault effects in asynchronous sequential logic circuits." IEE Proceedings E (Computers and Digital Techniques) 140, no. 6 (November 1993): 327–32. http://dx.doi.org/10.1049/ip-e.1993.0046.

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Chi-Ying Tsui, J. Monteiro, Massoud Pedram, Srinivas Devadas, A. M. Despain, and B. Lin. "Power estimation methods for sequential logic circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3, no. 3 (September 1995): 404–16. http://dx.doi.org/10.1109/92.406998.

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Sarica, Fatma, and Avni Morgül. "Basic circuits for multi-valued sequential logic." Analog Integrated Circuits and Signal Processing 74, no. 1 (August 29, 2012): 91–96. http://dx.doi.org/10.1007/s10470-012-9946-0.

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Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (December 6, 2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.

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This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

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Saito, Ro, Christopher L. Ayala, Olivia Chen, Tomoyuki Tanaka, Tomohiro Tamura, and Nobuyuki Yoshikawa. "Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic." IEEE Transactions on Applied Superconductivity 31, no. 5 (August 2021): 1–5. http://dx.doi.org/10.1109/tasc.2021.3061636.

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Jiang, Jin Tao, Yu Zhang, and Jian Ping Hu. "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits." Advanced Materials Research 159 (December 2010): 155–61. http://dx.doi.org/10.4028/www.scientific.net/amr.159.155.

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With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

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Madec, Morgan, Elise Rosati, and Christophe Lallement. "Feasibility and reliability of sequential logic with gene regulatory networks." PLOS ONE 16, no. 3 (March 30, 2021): e0249234. http://dx.doi.org/10.1371/journal.pone.0249234.

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Gene regulatory networks exhibiting Boolean behaviour, e.g. AND, OR or XOR, have been routinely designed for years. However, achieving more sophisticated functions, such as control or computation, usually requires sequential circuits or so-called state machines. For such a circuit, outputs depend both on inputs and the current state of the system. Although it is still possible to design such circuits by analogy with digital electronics, some particularities of biology make the task trickier. The impact of two of them, namely the stochasticity of biological processes and the inhomogeneity in the response of regulation mechanisms, are assessed in this paper. Numerical simulations performed in two use cases point out high risks of malfunctions even for designed GRNs functional from a theoretical point of view. Several solutions to improve reliability of such systems are also discussed.

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MOHAMMADI, MAJID, ALIAKBAR NIKNAFS, MOHAMMAD ESHGHI, and GERHARD W. DUECK. "DESIGN AND OPTIMIZATION OF SINGLE AND MULTIPLE-LOOP REVERSIBLE AND QUANTUM FEEDBACK CIRCUITS." Journal of Circuits, Systems and Computers 21, no. 03 (May 2012): 1250018. http://dx.doi.org/10.1142/s0218126612500181.

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The majority of work in reversible logic circuits has been limited to combinational logic. Researchers are now beginning to suggest designs for sequential circuits. In this paper we propose a new method to design and optimize feedback reversible logic circuits and a specific group of quantum logic circuits based on the reversible state transition table and genetic algorithms (GA). To show the efficiency of the proposed method, some reversible sequential elements such as D and T flip-flops (FFs), with and without clock and reset, and edge triggered FFs are designed. We have also extended our method to multiple loop feedback circuits. The proposed circuits are highly optimized using a GA synthesis tool that allows don't care values. Some of the designs in this paper are presented in other papers; however, the comparisons show that the quantum cost and number of garbage inputs/outputs are reduced efficiently by our method.

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Amirany, Abdolah, and Ramin Rajaei. "Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory." SPIN 09, no. 01 (March 2019): 1950007. http://dx.doi.org/10.1142/s2010324719500073.

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As CMOS technology scales down toward below 2-digit nanometer dimensions, exponentially increasing leakage power, vulnerability to radiation induced soft errors have become a major problem in today’s logic circuits. Emerging spin-based logic circuits and architectures based on nonvolatile magnetic tunnel junction (MTJ) cells show a great potential to overcome the aforementioned issues. However, radiation induced soft errors are still a problem in MTJ-based circuits as they need sequential peripheral CMOS circuits for sensing the MTJs. This paper proposes a novel nonvolatile and low-cost radiation hardened magnetic full adder (MFA). In comparison with the previous designs, the proposed MFA is capable of tolerating particle strikes regardless of the amount of charge induced to a single node and even multiple nodes. Besides, the proposed MFA offers low power operation, low area and high performance as compared with previous counterparts. One of the most important features suggested by the proposed MFA circuit is full nonvolatility. Nonvolatile logic circuits remove the cost of high volume data transactions between memory and logic and also facilitate power gating in logic-in-memory architectures.

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KAO, CHI-CHOU, and YEN-TAI LAI. "IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS." Journal of Circuits, Systems and Computers 22, no. 05 (May 9, 2013): 1350033. http://dx.doi.org/10.1142/s0218126613500333.

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The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm.

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Kumaresan, Raja Sekar, Marshal Raj, and Lakshminarayanan Gopalakrishnan. "Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology." Journal of Electrical Engineering 73, no. 1 (February 1, 2022): 1–10. http://dx.doi.org/10.2478/jee-2022-0001.

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Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.

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Butyrlagin, Nikolay, Nikolay Chernov, Nikolay Prokopenko, and Vladislav Yugai. "Linear Logic Synthesis of Multi-Valued Sequential Circuits." Advances in Science, Technology and Engineering Systems Journal 4, no. 6 (2019): 430–42. http://dx.doi.org/10.25046/aj040654.

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Browne, Clarke, Dill, and Mishra. "Automatic Verification of Sequential Circuits Using Temporal Logic." IEEE Transactions on Computers C-35, no. 12 (December 1986): 1035–44. http://dx.doi.org/10.1109/tc.1986.1676711.

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Wu, S. F., and P. D. Fisher. "Automating the design of asynchronous sequential logic circuits." IEEE Journal of Solid-State Circuits 26, no. 3 (March 1991): 364–70. http://dx.doi.org/10.1109/4.75015.

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Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, and Scott Morton. "Low-level logic fault testing ASIC simulation environment." World Journal of Engineering 11, no. 3 (June 1, 2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.

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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

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Xiao, Lin Rong, Xiang Xu, and Shi Yan Ying. "Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata." Advanced Materials Research 662 (February 2013): 562–67. http://dx.doi.org/10.4028/www.scientific.net/amr.662.562.

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As an emerging nanotechnology, quantum-dot cellular automata (QCA) has the potential to be used for next generation VLSI. Various designs of combinational logic circuits have been proposed for QCA implementation, but sequential circuit design is limited due to the lack of high-performance QCA flip-flops. After an introduction on QCA and dual-edge triggered (DET) flip-flops, a new QCA DET T flip-flop following a pulsed latch scheme is presented. The proposed T flip-flop is simulated using QCADesigner simulator and its logic functionality is verified. The same data throughput of the DET flip-flop can be achieved while operating at half the clock frequency of a single-edge triggered (SET) counterpart. The proposed flip-flop is promising in building QCA sequential circuits with low power and high performance.

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Feldman, Alexander, Ingo Pill, Franza Wotawa, Ion Matei, and Johan De Kleer. "Efficient Model-Based Diagnosis of Sequential Circuits." Proceedings of the AAAI Conference on Artificial Intelligence 34, no. 03 (April 3, 2020): 2814–21. http://dx.doi.org/10.1609/aaai.v34i03.5670.

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In Model-Based Diagnosis (MBD), we concern ourselves with the health and safety of physical and software systems. Although we often use different knowledge representations and algorithms, some tools like satisfiability (SAT) solvers and temporal logics, are used in both domains. In this paper we introduce Finite Trace Next Logic (FTNL) models of sequential circuits and propose an enhanced algorithm for computing minimal-cardinality diagnoses. Existing state-of-the-art satisfiability algorithms for minimal diagnosis use Sorting Networks (SNs) for constraining the cardinality of the diagnostic candidates. In our approach we exploit Multi-Operand Adders (MOAs). Based on extensive tests with ISCAS-89 circuits, we found that MOAs enable Conjunctive Normal Form (CNF) encodings that are significantly more compact. These encodings lead to 19.7 to 67.6 times fewer variables and 18.4 to 62 times fewer clauses. For converting an FTNL model to CNF, we could achieve a speed-up ranging from 6.2 to 22.2. Using SNs fosters 3.4 to 5.5 times faster on-line satisfiability checking though. This makes MOAs preferable for applications where RAM and off-line time are more limited than on-line CPU time.

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Sasipriya, P., and V. S Kanchana Bhaaskaran. "Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)." International Journal of Engineering & Technology 7, no. 3 (July 19, 2018): 1548. http://dx.doi.org/10.14419/ijet.v7i3.14632.

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This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

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Matrosova, Anjela Yu, Evgeny V. Mitrofanov, Sergey A. Ostanin, Nataly B. Butorina, Elena G. Pakhomova, and Sergey A. Shulga. "Detection and masking of trojan circuits in sequential logic." Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitel'naya tekhnika i informatika, no. 42 (February 1, 2018): 89–99. http://dx.doi.org/10.17223/19988605/42/10.

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Pomeranz, Irith. "Invariant States and Redundant Logic in Synchronous Sequential Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 6 (June 2007): 1171–75. http://dx.doi.org/10.1109/tcad.2006.885832.

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Chen, J. E., C. L. Lee, and W. Z. Shen. "Single-fault fault-collapsing analysis in sequential logic circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 12 (1991): 1559–68. http://dx.doi.org/10.1109/43.103505.

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Jahanirad, H. "Efficient reliability evaluation of combinational and sequential logic circuits." Journal of Computational Electronics 18, no. 1 (December 7, 2018): 343–55. http://dx.doi.org/10.1007/s10825-018-1288-4.

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Debany, Warren H. "Coverage of Node Shorts Using Internal Access and Equivalence Classes." VLSI Design 1, no. 1 (January 1, 1993): 71–85. http://dx.doi.org/10.1155/1993/42309.

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A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS power supply current monitoring (including IDDQ), CrossCheck, and voltage contrast. Only fault-free circuit simulation is used to obtain node states. Two versions of the algorithm are presented: a simple algorithm that is suitable for use with two-state logic (0 and 1), and a more general algorithm for four-state logic (0, 1, X, and Z). The result is a set of sets of nodes, where a list of all potential shorts that could exist in the circuit yet be undetected after testing is obtained easily from the power sets of these sets; unlike other approaches the full universe of potential shorts is not generated. Experiments show that short, randomly generated sequences of test vectors detect essentially all detectable shorts of multiplicity 2 for both combinational and sequential circuits.

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Stamoulis, Georgios I. "A Monte-Carlo Approach for the Estimation of Average Transition Probabilities in Sequential Logic Circuits." Active and Passive Electronic Components 24, no. 2 (2001): 69–85. http://dx.doi.org/10.1155/2001/41403.

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This paper presents an efficient and accurate Monte-Carlo approach to the problem of estimating average node switching probabilities in sequential circuits, which are used in average power estimation and reliability analysis of these circuits. Specific error bounds for the proposed estimation method are given at a certain level of confidence. This method is based on the analysis of paths in the State Transition Graph (STG) of the circuit and is validated by both theoretical analysis as well as experimental results.

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Houshmand, Pouran, and Majid Haghparast. "Design of a novel quantum reversible ternary up-counter." International Journal of Quantum Information 13, no. 05 (August 2015): 1550038. http://dx.doi.org/10.1142/s0219749915500380.

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Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others.

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Jone, Wen-Ben, Nigam Shah, Anita Gleason, and Sunil R. Das. "PGEN: A Novel Approach to Sequential Circuit Test Generation." VLSI Design 4, no. 3 (January 1, 1996): 149–65. http://dx.doi.org/10.1155/1996/68463.

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A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits. PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation. A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.

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Uemura, Taiki, Yoshiharu Tosaka, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda, and Kichiji Hatanaka. "Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits." Japanese Journal of Applied Physics 48, no. 4 (April 20, 2009): 04C070. http://dx.doi.org/10.1143/jjap.48.04c070.

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Ni, Hai Yan, and Jian Ping Hu. "Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes." Key Engineering Materials 460-461 (January 2011): 837–42. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.837.

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This paper presents adiabatic flip-flops operating on near-threshold supply voltages. The near-threshold adiabatic flip-flops and sequential circuits are realized with improved CAL (Clocked Adiabatic Logic) circuits using a single-phase power clock. An auxiliary clock generator is used to obtain the non-overlap sinusoidal auxiliary signal pair. A near-threshold mode-10 counter is implemented. All circuits are simulated using Predictive Technology Model (PTM) 45nm process. The near-threshold adiabatic circuits attain large energy savings over a wide range of frequencies, as compared with conventional static CMOS logic circuits.

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40

Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment." Electronics 10, no. 8 (April 10, 2021): 901. http://dx.doi.org/10.3390/electronics10080901.

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Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

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41

Andaloussi, Issam, and Moulay Brahim Sedra. "A design of sequential reversible circuits by reversible gates." International Journal of Engineering & Technology 9, no. 2 (April 18, 2020): 397. http://dx.doi.org/10.14419/ijet.v9i2.30451.

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Reversible logic has become increasingly important in the design of low power CMOS circuits, quantum computing and nanotechnology. In this article we work on recent sequential circuits namely RS Flip Flop JK Flop Flip Flop Flop Flip Flop Master Slave Flip Flop using some reversible gates FG (Feyman Gate), FRG (Fredkin Gate), NG (New Gate) , PG (Peres Gate), BJN (New BJN Gate), while modifying them to obtain new circuits keeping their same functionality and increasing their performances.

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42

Cao, Ruiping, and Jianping Hu. "Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits." Journal of Electrical and Computer Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/836019.

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In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

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43

Chi-Ying Tsui, J. Monteiro, M. Pedram, S. Devadas, A. M. Despain, and B. Lin. "Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 4, no. 4 (December 1996): 495. http://dx.doi.org/10.1109/tvlsi.1996.544414.

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Venkatasubramanian, Ramakrishnan, Sujan K. Manohar, and Poras T. Balsara. "NEM Relay-Based Sequential Logic Circuits for Low-Power Design." IEEE Transactions on Nanotechnology 12, no. 3 (May 2013): 386–98. http://dx.doi.org/10.1109/tnano.2013.2252923.

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Harris, M. S. "Computer-aided design techniques for low power sequential logic circuits." Microelectronics Journal 29, no. 6 (June 1998): 363. http://dx.doi.org/10.1016/s0026-2692(97)00073-6.

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46

De Micheli, G. "Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 4 (October 1986): 597–616. http://dx.doi.org/10.1109/tcad.1986.1270230.

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Mancini, Toni, Annalisa Massini, and Enrico Tronci. "Parallelization of Cycle-Based Logic Simulation." Parallel Processing Letters 27, no. 02 (June 2017): 1750003. http://dx.doi.org/10.1142/s0129626417500037.

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Verification of digital circuits by Cycle-based simulation can be performed in parallel. The parallel implementation requires two phases: the compilation phase, that sets up the data needed for the execution of the simulation, and the simulation phase, that consists in executing the parallel simulation of the considered circuit for a certain number of cycles. During the early phase of design, compilation phase has to be repeated each time a bug is found. Thus, if the time of the compilation phase is too high, the advantages stemming from the parallel approach may be lost. In this work we propose an effective version of the compilation phase and compute the corresponding execution time. We also analyze the percentage of execution time required by the different steps of the compilation phase for a set of literature benchmarks. Further, we implemented the simulation phase exploiting the GPU architecture, and we computed the execution times for a set of benchmarks obtaining values comparable with literature ones. Finally, we implemented the sequential version of the Cycle-based simulation in such a way that the execution time is optimized. We used the sequential values to compute the speedup of the parallel version for the considered set of benchmarks.

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Liu, Wenting, and Qun Sun. "Research on a design method of pneumatic logic control system." Measurement and Control 54, no. 5-6 (May 2021): 1105–12. http://dx.doi.org/10.1177/00202940211020336.

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Aiming at the complex characteristics of the sequential logic control system design, such as X-D diagram and karnaugh map method, a design method based on stepper module was proposed, the procedure of which does not need to be checked and corrected. The design of different pneumatic circuits was carried out with the automatic drilling machine as the application object. First, a stepper module composed of a two-position three-way valve and a dual-pressure valve was constructed, and its structure principle was analyzed in detail. Next, three kinds of stroke programs were listed by analyzing the working process of automatic drilling machine, which were multi-cylinder single reciprocating, multi-cylinder multi reciprocating and multi-cylinder multi-section reciprocating stroke program, and the pneumatic circuit control system was designed by the stepper module method. Finally, the pneumatic circuit was simulated and analyzed using the software Fluid-SIM. The simulation results showed that each actuator can complete the corresponding actions according to the design requirements, which verified the correctness and reliability of the stepper module design method. This work would provide a fast and effective method for the design of the sequential logic control system.

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Mahmood, Ausif, and William I. Baker. "An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations." VLSI Design 4, no. 2 (January 1, 1996): 91–105. http://dx.doi.org/10.1155/1996/56545.

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A recent paper by Bailey [1] contains a theorem stating that the idealized execution times of unit-delay, synchronous and conservative asynchronous simulations are equal under the conditions that unlimited number of processors are available and the evaluation time of each logic element is equal. Further it is shown that the above conditions result in a lower bound on the execution times of both synchronous and conservative asynchronous simulations. Bailey's above important conclusions are derived under a strict assumption that the inputs to a circuit remain fixed during the entire simulation. We remove this limitation and, by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events, show that the conservative asynchronous simulation extracts more parallelism and executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits.

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Yakunin, A. N., Aung Myo San, and Khant Win. "Improving Performance of a Multi-Bit Arithmetic Logic Unit." Proceedings of Universities. Electronics 26, no. 1 (February 2021): 40–53. http://dx.doi.org/10.24151/1561-5405-2021-26-1-40-53.

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In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

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Journal articles on the topic 'Sequential logic circuits'

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