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Journal articles on the topic 'Sequential digital circuits'
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Jagadeesan, Neeraja, B. Saman, M. Lingalugari, P. Gogna, and F. Jain. "Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs." International Journal of High Speed Electronics and Systems 24, no. 03n04 (September 2015): 1550011. http://dx.doi.org/10.1142/s0129156415500111.
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The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).
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Hudli, Anand V., and Raghu V. Hudli. "Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits." VLSI Design 2, no. 1 (January 1, 1994): 69–80. http://dx.doi.org/10.1155/1994/94514.
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Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.
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Nagar, Ayushi, and Rahul Shrivastava. "Review of Clocked Storage Elements in Digital Circuit Design." International Journal on Recent and Innovation Trends in Computing and Communication 7, no. 5 (June 4, 2019): 30–34. http://dx.doi.org/10.17762/ijritcc.v7i5.5308.
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Storage of digital circuit is "state" or memory. These are called sequential circuits. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. It is ponder four distinct assortments of these gadgets and their utilization in registers and register documents, which can be considered as one type of on– CPU memory. The traditional memory, called RAM, is ordinarily not on the CPU chip. Regular Slam and its assortments, including RAM, ROM, SRAM, Measure, and SDRAM. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. At first as a quick topology, the TSPC structure in like manner eats up less power and includes less areas than various systems. In flip-flop plan only a single transistor is being clocked by short heartbeat get ready which is known as True Single Phase Clocking (TSPC) flip-flop.
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Madec, Morgan, Elise Rosati, and Christophe Lallement. "Feasibility and reliability of sequential logic with gene regulatory networks." PLOS ONE 16, no. 3 (March 30, 2021): e0249234. http://dx.doi.org/10.1371/journal.pone.0249234.
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Gene regulatory networks exhibiting Boolean behaviour, e.g. AND, OR or XOR, have been routinely designed for years. However, achieving more sophisticated functions, such as control or computation, usually requires sequential circuits or so-called state machines. For such a circuit, outputs depend both on inputs and the current state of the system. Although it is still possible to design such circuits by analogy with digital electronics, some particularities of biology make the task trickier. The impact of two of them, namely the stochasticity of biological processes and the inhomogeneity in the response of regulation mechanisms, are assessed in this paper. Numerical simulations performed in two use cases point out high risks of malfunctions even for designed GRNs functional from a theoretical point of view. Several solutions to improve reliability of such systems are also discussed.
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Dobai, Roland, and Elena Gramatová. "A novel automatic test pattern generator for asynchronous sequential digital circuits." Microelectronics Journal 42, no. 3 (March 2011): 501–8. http://dx.doi.org/10.1016/j.mejo.2010.10.013.
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Tayal, Shubham, and Sunil Jadav. "Power-Delay Trade-Offs in Complementary Metal-Oxide Semiconductor Circuits Using Self and Optimum Bulk Control." Sensor Letters 18, no. 3 (March 1, 2020): 210–15. http://dx.doi.org/10.1166/sl.2020.4211.
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Power dissipation and delay are the challenging issues in the design of VLSI circuits. This manuscript explores joint effect of Self-Bias transistors (SBTs) and Optimum Bulk Bias Technique (OBBT) on CMOS circuits. Earlier investigations on SBTs shows decrease in power dissipation of combinational as well as sequential circuits. We extend the analysis by studying the effect of OBBT on the static and dynamic power of CMOS circuits with SBTs coupled amid the pull-up/down network and the supply bars. Extensive SPICE simulations have been carried out in 0.18 μm technology. Results demonstrate that, a 73% drop in power in case of combinational circuits and 43% in case of sequential circuits can be accomplished by engaging OBBT in digital circuits. Trade-off between power and delay is also been presented.
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Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, and Scott Morton. "Low-level logic fault testing ASIC simulation environment." World Journal of Engineering 11, no. 3 (June 1, 2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.
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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.
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Barkalov, Oleksandr O., Larisa O. Titarenko, Oleksandr M. Golovin, and Oleksandr V. Matvienko. "Optimization of a Composition Microprogram Control Unit with Elementary Circuits." Control Systems and Computers, no. 2-3 (292-293) (July 2021): 40–51. http://dx.doi.org/10.15407/csc.2021.02.040.
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Introduction. The control unit coordinating interaction of all other blocks of a digital system is one of the central blocks and is a sequential circuit. As a rule, when synthesizing control unit circuits, the problem arises of reducing hardware costs. Methods for solving this problem depend on features of both the architecture of the control unit and the elemental basis. Purpose. The main goal of this work is to reduce hardware costs and power consumption of control units of digital systems by taking into account features of the element base of the control unit and rational organization of addressing microinstructions. FPGA (field-programmable logic array) microcircuits, widely used for the implementation of modern digital systems, were chosen as an elementary basis. Methods. Methods of set theory, synthesis of automata, and software modeling as well as the library of standard automata and FPGA Virtex-7 from Xilinx were used for assessment the effectiveness of solving the problem. Results. The paper proposes a method for optimizing the circuit of the microinstruction addressing unit based on splitting the set of outputs of elementary linear operator circuits, which is based on the idea of double coding of states. The proposed method, under certain conditions, makes it possible to reduce the number of levels in the microinstruction addressing circuit to two. Conclusion. Studies have shown that double coding of states can increase performance, reduce hardware costs (the number of LUTs and their interconnections) and power consumption in Mealy’s circuitry. Based on these results, it can be expected that, with the number of conditions exceeding the number of LUT inputs, the proposed approach will improve the characteristics of the composition microprogram control unit in comparison with the equivalent control unit U1.
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OBATA, K., K. TAKAGI, and N. TAKAGI. "A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits." IEICE Transactions on Electronics E90-C, no. 12 (December 1, 2007): 2278–84. http://dx.doi.org/10.1093/ietele/e90-c.12.2278.
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Guimarães, Janaina Gonçalves, and Beatriz De Oliveira Câmara. "Digital Circuits and Systems based on Single-Electron Tunneling Technology." Journal of Integrated Circuits and Systems 16, no. 1 (April 5, 2021): 1–9. http://dx.doi.org/10.29292/jics.v16i1.475.
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In this work, digital circuits and systems based on single-electron tunneling technology will be presented and analyzed. A simple design methodology will be proposed using a programmable single-electron NAND/NOR gate as a building block. Aspects such as operating temperature, noise, and charge fluctuations will be discussed. SET devices can reach ultra-low power consumption and high frequencies during operation. Although there are already many digital SET circuits and systems previously proposed and studied, there are few works about design methodology for SETs. This study shows a proposal for designing combinational and sequential singleelectron circuits aiming at systems design. In the end, this work reinforces the use of single-electron technology as a possible large scale device in the future.
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Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment." Electronics 10, no. 8 (April 10, 2021): 901. http://dx.doi.org/10.3390/electronics10080901.
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Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.
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Debany, Warren H. "Coverage of Node Shorts Using Internal Access and Equivalence Classes." VLSI Design 1, no. 1 (January 1, 1993): 71–85. http://dx.doi.org/10.1155/1993/42309.
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A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS power supply current monitoring (including IDDQ), CrossCheck, and voltage contrast. Only fault-free circuit simulation is used to obtain node states. Two versions of the algorithm are presented: a simple algorithm that is suitable for use with two-state logic (0 and 1), and a more general algorithm for four-state logic (0, 1, X, and Z). The result is a set of sets of nodes, where a list of all potential shorts that could exist in the circuit yet be undetected after testing is obtained easily from the power sets of these sets; unlike other approaches the full universe of potential shorts is not generated. Experiments show that short, randomly generated sequences of test vectors detect essentially all detectable shorts of multiplicity 2 for both combinational and sequential circuits.
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Tsai, Edison, and Marek Perkowski. "A quantum algorithm for automata encoding." Facta universitatis - series: Electronics and Energetics 33, no. 2 (2020): 169–215. http://dx.doi.org/10.2298/fuee2002169t.
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Encoding of finite automata or state machines is critical to modern digital logic design methods for sequential circuits. Encoding is the process of assigning to every state, input value, and output value of a state machine a binary string, which is used to represent that state, input value, or output value in digital logic. Usually, one wishes to choose an encoding that, when the state machine is implemented as a digital logic circuit, will optimize some aspect of that circuit. For instance, one might wish to encode in such a way as to minimize power dissipation or silicon area. For most such optimization objectives, no method to find the exact solution, other than a straightforward exhaustive search, is known. Recent progress towards producing a quantum computer of large enough scale to surpass modern supercomputers has made it increasingly relevant to consider how quantum computers may be used to solve problems of practical interest. A quantum computer using Grover?s well-known search algorithm can perform exhaustive searches that would be impractical on a classical computer, due to the speedup provided by Grover?s algorithm. Therefore, we propose to use Grover?s algorithm to find optimal encodings for finite state machines via exhaustive search. We demonstrate the design of quantum circuits that allow Grover?s algorithm to be used for this purpose. The quantum circuit design methods that we introduce are potentially applicable to other problems as well.
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Appels, Karel, and Jeffrey Prinzie. "Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits." Electronics 9, no. 11 (November 17, 2020): 1936. http://dx.doi.org/10.3390/electronics9111936.
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This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.
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Konuk, H., and F. J. Ferguson. "Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 11 (1998): 1200–1210. http://dx.doi.org/10.1109/43.736192.
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Prinzie, Jeffrey, Karel Appels, and Szymon Kulis. "Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies." Electronics 8, no. 4 (April 14, 2019): 432. http://dx.doi.org/10.3390/electronics8040432.
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This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.
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Pischel, Uwe. "Digital Operations with Molecules - Advances, Challenges, and Perspectives." Australian Journal of Chemistry 63, no. 2 (2010): 148. http://dx.doi.org/10.1071/ch09460.
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This Review gives a short introduction into molecular logic and focusses then on the latest advances in the field. With regard to complex logic circuits and functions, molecular devices for arithmetic processing (adders and subtractors), multiplexers/demultiplexers, and encoders/decoders are discussed. Further on, the concept of memory for data storage and sequential logic is considered together with the latest results on molecular keypad locks. Molecular logic has been often connected to the future aim of molecular computing. However, albeit the herein described approaches constitute a starting point, major challenges like concatenation of gates, solid state devices and compartmentalization, and alternative concepts (reversible logic, multivalued logic) are waiting ahead. These points are included, as well as a view on alternative applications of molecular logic in bio-inspired approaches, combinatorial chemistry, and materials science.
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Esmoris, Agustín, Carlos Iván Chesñevar, and Maráa Paula González. "TAGS: A Software Tool for Simulating Transducer Automata." International Journal of Electrical Engineering & Education 42, no. 4 (October 2005): 338–49. http://dx.doi.org/10.7227/ijeee.42.4.5.
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This paper introduces TAGS (Transducer Automata Graphical Simulator), a software tool for teaching different aspects of transducer automata theory, a theoretical topic which underlies many aspects of the design of sequential digital circuits. TAGS allows simulation of both Moore and Mealy transducer automata, integrating different theoretical concepts associated with them. The student can define an arbitrary transducer automaton in an interactive way, being able to simulate and trace its behavior by means of different ‘views’.
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Ari Setiyani, Theresia Prima, and Yohanes Suyanto. "Implementasi Reduksi Keadaan Rangkaian Digital Sekuensial Metode Bagan Implikasi." Jurnal Tekno 16, no. 2 (October 29, 2019): 23–34. http://dx.doi.org/10.33557/jtekno.v16i1.622.
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The implementation of state reduction in sequential digital circuits is made for learning the topic of state reduction. The method used for state reduction is an implication chart. This method starts with reading the transition table state and transfered into the array structure. Based on this array structure a table or chart of initial implications is arranged. The next process is to change the contents of the table if there are cells that meet the requirements to be declared as identical or not identical. This process is repeated continuously until there is no change in cell contents. The state of reduction implementation is made using the Python programming language and PHP. The results of the implementation are successful for the state transition table with 1 input and 1 output.
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Vivekananda, Ashish Alape, and Eduard Enoiu. "Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages." Designs 4, no. 3 (August 5, 2020): 31. http://dx.doi.org/10.3390/designs4030031.
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Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.
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Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (May 3, 2019): 496. http://dx.doi.org/10.3390/electronics8050496.
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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.
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Ali Muhammad Rushdi, Ali Muhammad Rushdi. "Two Novel Characterizations of the DE Flip Flop." journal of King Abdulaziz University Engineering Sciences 30, no. 1 (February 2, 2018): 3–18. http://dx.doi.org/10.4197/eng.30-1.1.
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Modern digital circuits, especially those based on large-scale integration devices employ DE flip flops, which are an extension of the D type with the capacity to store an input value only upon request or enabling. The DE flip flop could possibly be described algebraically by its characteristic equation or tabularly by its next-state table (used for analysis purposes) and its excitation table (used for synthesis purposes). This paper explores two novel characterizations of DE flip flops. First, equational and implicational descriptions are presented, and the Modern Syllogistic Method is utilized to produce complete statements of all propositions that are true for a general DE flip flop. Next, methods of Boolean-equation solving are employed to find all possible ways to express the excitations in terms of the present state and next state. The concept of Boolean quotient plays a crucial role in exposing the pertinent concepts and implementing the various desired derivations. This paper is expected to be of an immediate pedagogical benefit, and to facilitate the analysis and synthesis of contemporary sequential digital circuits.
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Mancini, Toni, Annalisa Massini, and Enrico Tronci. "Parallelization of Cycle-Based Logic Simulation." Parallel Processing Letters 27, no. 02 (June 2017): 1750003. http://dx.doi.org/10.1142/s0129626417500037.
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Verification of digital circuits by Cycle-based simulation can be performed in parallel. The parallel implementation requires two phases: the compilation phase, that sets up the data needed for the execution of the simulation, and the simulation phase, that consists in executing the parallel simulation of the considered circuit for a certain number of cycles. During the early phase of design, compilation phase has to be repeated each time a bug is found. Thus, if the time of the compilation phase is too high, the advantages stemming from the parallel approach may be lost. In this work we propose an effective version of the compilation phase and compute the corresponding execution time. We also analyze the percentage of execution time required by the different steps of the compilation phase for a set of literature benchmarks. Further, we implemented the simulation phase exploiting the GPU architecture, and we computed the execution times for a set of benchmarks obtaining values comparable with literature ones. Finally, we implemented the sequential version of the Cycle-based simulation in such a way that the execution time is optimized. We used the sequential values to compute the speedup of the parallel version for the considered set of benchmarks.
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Kubica, Marcin, and Dariusz Kania. "Graph of Outputs in the Process of Synthesis Directed at CPLDs." Mathematics 7, no. 12 (December 3, 2019): 1171. http://dx.doi.org/10.3390/math7121171.
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The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.
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Nugroho, Eko Dwi. "Development of Applications for Simplification of Boolean Functions using Quine-McCluskey Method." Telematika 18, no. 1 (March 16, 2021): 27. http://dx.doi.org/10.31315/telematika.v18i1.3195.
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Purpose: This research makes an application to simplify the Boolean function using Quine-McCluskey, because length of the Boolean function complicates the digital circuit, so that it can be simplified by finding other functions that are equivalent and more efficient, making digital circuits easier, and less cost.Design/methodology/approach: The canonical form is Sum-of-Product/Product-of-Sum and is in the form of a file, while the output is in the form of a raw and in the form of a file. Applications can receive the same minterm/maksterm input and do not have to be sequential. The method has been applied by Idempoten, Petrick, Selection Sort, and classification, so that simplification is maximized.Findings/result: As a result, the application can simplify more optimally than previous studies, can receive the same minterm/maksterm input, Product-of-Sum canonical form, and has been verified by simplifying and calculating manually.Originality/value/state of the art: Research that applies the petrick method to applications combined with being able to receive the same minterm/maksterm input has never been done before. The calculation is only up to the intermediate stage of the Quine-McCluskey method or has not been able to receive the same minterm/maksterm input.
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Ochi, Atsuhiko, Toru Tanimori, Yuji Nishi, Shunsuke Aoki, and Yasuro Nishi. "Development of an ultra-fast data-acquisition system for a two-dimensional microstrip gas chamber." Journal of Synchrotron Radiation 5, no. 3 (May 1, 1998): 1119–22. http://dx.doi.org/10.1107/s0909049597019018.
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A high-performance data-acquisition system has been developed in order to obtain time-resolved sequential images from a two-dimensional microstrip gas chamber (MSGC). This was achieved using fully digital processing with a synchronized pipeline method. Complex logical circuits for processing large numbers of signals are mounted on a small number of complex programmable logic devices. The system is operated with a 10 MHz synchronous clock, and has the capability of handling more than 3 × 106 counts s−1 for asynchronous events. The system was examined using a 5 × 5 cm MSGC and the recently developed 10 × 10 cm MSGC (1024 outputs); the anticipated performances were achieved.
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Barkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki, and Svetlana Saburova. "Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs." Electronics 9, no. 11 (November 5, 2020): 1859. http://dx.doi.org/10.3390/electronics9111859.
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Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count.
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Barkalov, Alexander, Larysa Titarenko, and Kazimierz Krzywicki. "Reducing LUT Count for FPGA-Based Mealy FSMs." Applied Sciences 10, no. 15 (July 25, 2020): 5115. http://dx.doi.org/10.3390/app10155115.
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Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.
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Larrabee, Allan R. "The P4 Parallel Programming System, the Linda Environment, and Some Experiences with Parallel Computation." Scientific Programming 2, no. 3 (1993): 23–35. http://dx.doi.org/10.1155/1993/817634.
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The first digital computers consisted of a single processor acting on a single stream of data. In this so-called "von Neumann" architecture, computation speed is limited mainly by the time required to transfer data between the processor and memory. This limiting factor has been referred to as the "von Neumann bottleneck". The concern that the miniaturization of silicon-based integrated circuits will soon reach theoretical limits of size and gate times has led to increased interest in parallel architectures and also spurred research into alternatives to silicon-based implementations of processors. Meanwhile, sequential processors continue to be produced that have increased clock rates and an increase in memory locally available to a processor, and an increase in the rate at which data can be transferred to and from memories, networks, and remote storage. The efficiency of compilers and operating systems is also improving over time. Although such characteristics limit maximum performance, a large improvement in the speed of scientific computations can often be achieved by utilizing more efficient algorithms, particularly those that support parallel computation. This work discusses experiences with two tools for large grain (or "macro task") parallelism.
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Nag, Abhishek, Subhajit Das, and Sambhu Nath Pradhan. "Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1920003. http://dx.doi.org/10.1142/s0218126619200032.
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This work introduces a concept of integrating clock gating and power gating in finite state machines (FSMs) to reduce the overall power dissipation. The theory of the proposed power gating technique is to shut down the power supply during periods of inactivity of the FSM. The inactive period is identified by the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating on the other hand disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The proposed approach introduces the concept of gating into both the state logic (DGS) and output logic (DGO) in FSM separately and can be implemented in general to all FSMs. The control logic for gating automatically extracts information from the state description of the FSM. An efficient method of partitioning of the FSM is also proposed in this paper to effectively implement the gating techniques. The dual gating approach has been introduced in 10 standard benchmark FSM circuits for DGS technique and later extended to four FSMs for implementing “DGS[Formula: see text][Formula: see text][Formula: see text]DGO.” Then the circuits are simulated and synthesized in CADENCE analog and digital design tools. Simulation results show a maximum power reduction of 62.17% in DGS technique and 73% total power savings after implementing “DGS[Formula: see text][Formula: see text][Formula: see text]DGO.” The average area overhead in DGS technique is 12.9% whereas in DGS[Formula: see text][Formula: see text][Formula: see text]DGO, the area increases by 22.6%. The area overhead and the delay tend to reduce as the size of the FSM increases.
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Avril, Hervé, and Carl Tropper. "Scalable Clustered Time Warp and Logic Simulation." VLSI Design 9, no. 3 (January 1, 1999): 291–313. http://dx.doi.org/10.1155/1999/23047.
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We introduce, in this paper, Clustered Time Warp (CTW), an algorithm for the parallel simulation of discrete event models on a general purpose distributed memory architecture. CTW has its roots in the problem of distributed logic simulation. It is a hybrid algorithm which makes use of Time Warp between clusters of LPs and a sequential algorithm within the clusters whereas Time Warp is traditionally implemented between individual LPs.We also develop a family of three checkpointing algorithms for use with CTW, each of which occupies a different point in the spectrum of possible trade-offs between memory usage and execution time. The algorithms were implemented and tested on several digital logic circuits and their speed, number of states saved and maximal memory consumption were compared to Time Warp. Our results showed that one of the algorithms saved an average of 40% of the maximal memory consumed by Time Warp while the other two decreased the maximal usage by 15 and 22%, respectively. The latter two algorithms exhibited a speed comparable to Time Warp, while the first algorithm was 60% slower.We investigated the scalability of CTW using 3 different queuing models and different service-time distributions and showed that the algorithm acts to limit the explosion of rollbacks exhibited by Time Warp. Furthermore, we showed that the memory requirements for CTW are three times smaller than that of Time Warp for one model and half as large for the two other models.
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Yu, Guangwei, Yuan Yao, and Zhuoyuan Song. "A multi-dimensional matrix keyboard interfacing circuit design." Circuit World 46, no. 3 (January 23, 2020): 175–82. http://dx.doi.org/10.1108/cw-10-2019-0142.
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Purpose This paper presents a novel design method for keyboard circuits. The purpose of this study is to enable a single-board computer with fewer pins to recognize a keyboard system consisting of a large number of switches. Through the study of different kinds of keyboard circuits, a general circuit schematic design method is abstracted. Several experiments are conducted to prove the feasibility of the proposed circuit design method. Design/methodology/approach Conventional circuit schematic diagrams are often limited to two-dimensional planes. Through investigating higher dimensional alternatives, this paper proposes to place components in high-dimensional geometry before connecting all components. A multi-pin switch construction method is proposed to allow the switches to be arranged on the vertices of high-dimensional geometry and be connected sequentially to form the keyboard system. This proposed system can allow a keyboard system consisting of a large number of switches to be recognized by a single-board computer with less available pins. Findings The design scheme proposed in this paper can read more switch states with limited Input/Output pins. With the increase of the number of Input/Output ports and pins, the number of simultaneously identifiable switches increases exponentially, which is suitable for sensor design of array type. Research limitations/implications Compared with the classical keyboard circuits, the circuit designed using the proposed method will lead to a slightly longer recognition time for each key. This can be compensated by a single-board computer with a modestly higher clock speed. Originality/value The circuit schematic design method based on high-dimensional geometry is introduced for the first time. The feasibility of the proposed method is verified by the original experiments. The proposed approach is of importance in guiding the design of new analog and digital sensor circuit systems.
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Rea, Richard. "Configurable Digital Logic for Extreme Environments." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (May 1, 2018): 000098–102. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000098.
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Abstract This paper presents a multiple-configuration IC that implements a number of sequential or combinatorial logic functions for extreme environment electronics. Operating temperature is −55°C to +300°C. Combinatorial functions include AND, OR, XOR, muxes, bi-directional transceiver, priority-encoder, magnitude comparator, etc. Sequential functions include 8-bit DFF, counter, latch, programmable clock-divider, etc. The majority of 7400 logic parts are covered by this part. Special test circuitry is included for in-situ monitoring of the part during production. Endurance testing and monitoring of part lifetime at elevated stress temperature (+350°C) is also built-in.
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Oliveira, A. L. "Techniques for the creation of digital watermarks in sequential circuit designs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 9 (2001): 1101–17. http://dx.doi.org/10.1109/43.945306.
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Yang, Chuan Lei, Jin Zhu Liu, Can Cao, and Jin Xin Wang. "Development of Automatic Examination Instrument for Diesel Engine Sequential Turbocharging Control System." Applied Mechanics and Materials 339 (July 2013): 137–42. http://dx.doi.org/10.4028/www.scientific.net/amm.339.137.
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ATmega128 single-chip microcomputer was regarded as control core, the diesel engine speed and pressure signal simulation hardware circuit were designed based on digital to analog converter TLC5618, clock chip DS12C887 and analog signal processing unit SY4-20mA-P. According to the equipment evaluation process, the sequential turbocharging control instrument automatic assessment program was compiled in the reference of real-time. The sequential turbocharging control instrument factory automatic evaluation function was realized which improve the production efficiency.
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Zhou, Ning, Xinyan Gao, Jinzhao Wu, Jianchao Wei, and Dakui Li. "Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions." Journal of Applied Mathematics 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/194574.
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We introduce an approach exploiting the power of polynomial ring algebra to perform SystemVerilog assertion verification over digital circuit systems. This method is based on Groebner bases theory and sequential properties checking. We define a constrained subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using Groebner bases for concurrent SVAs checking. Case studies show that computer algebra can provide canonical symbolic representations for both assertions and circuit designs and can act as a novel solver engine from the viewpoint of symbolic computation.
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Nakano, Teppei, Takashi Morie, Makoto Nagata, and Atsushi Iwata. "A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation." Journal of Robotics and Mechatronics 17, no. 4 (August 20, 2005): 378–86. http://dx.doi.org/10.20965/jrm.2005.p0378.
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This paper proposes a new region extraction algorithm and its digital LSI architecture based on cellular-automaton operation for very fast image processing. The algorithm sequentially extracts each region defined by a closed boundary. From digital logic simulation using Verilog-HDL, the proposed circuit with pixel-parallel operation can operate 100 times faster than serial labeling for a 100×100-pixel image. We implemented the proposed circuit in an FPGA for 30×30-pixel image processing. In an experiment with the FPGA, five regions are successfully extracted one by one within 6μs at a clock frequency of 25MHz.
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Hasan, Sayed Mohammad Rezaul. "A digital cmos sequential circuit model for bio-cellular adaptive immune response pathway using phagolysosomic digestion: a digital phagocytosis engine." Journal of Biomedical Science and Engineering 03, no. 05 (2010): 470–75. http://dx.doi.org/10.4236/jbise.2010.35065.
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Nakada, Kazuki, Tetsuya Asai, and Yoshihito Amemiya. "Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller." Journal of Robotics and Mechatronics 16, no. 4 (August 20, 2004): 397–403. http://dx.doi.org/10.20965/jrm.2004.p0397.
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The present paper proposes analog integrated circuit (IC) implementation of a biologically inspired controller in quadruped robot locomotion. Our controller is based on the central pattern generator (CPG), which is known as the biological neural network that generates fundamental rhythmic movements in locomotion of animals. Many CPG-based controllers for robot locomotion have been proposed, but have mostly been implemented in software on digital microprocessors. Such a digital processor operates accurately, but it can only process sequentially. Thus, increasing the degree of freedom of physical parts of a robot deteriorates the performance of a CPG-based controller. We therefore implemented a CPG-based controller in an analog complementary metal-oxide-semiconductor (CMOS) circuit that processes in parallel essentially, making it suitable for real-time locomotion control in a multi-legged robot. Using the simulation program with integrated circuit emphasis (SPICE), we show that our controller generates stable rhythmic patterns for locomotion control in a quadruped walking robot, and change its rhythmic patterns promptly.
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KANUNGO, JITENDRA, and S. DASGUPTA. "SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450066. http://dx.doi.org/10.1142/s0218126614500662.
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Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.
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T., Yuvaraja, and K. Ramya. "Statistical data analysis for harmonic reduction in 3Ø -fragmented source using novel fuzzy digital logic switching technique." Circuit World 45, no. 3 (August 5, 2019): 148–55. http://dx.doi.org/10.1108/cw-12-2018-0107.
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Purpose The purpose of this paper is to analyze the Luo super boost converter coupled fragmented source inversion system (LC-FSIS) and the progress of a controller structure for energy stored. The inversion system is characterized by a diode arm structure and can be easily amassed into a conversion system for high/medium- power conversion systems. Design/methodology/approach The investigation is based on the practice of a simplified circuit established as common anode/common cathode, where all the diodes in each arm are connected to a renewable DC voltage source. In this proposed work, a novel fuzzy digital logic switching technique (FDLST) for three-phase fragmented source inversion (FSI) for enhancement in power excellence is measured to enterprise the novel fuzzy digital logic switching technique to authorize operative voltage utilization and enhanced harmonic spectrum. Findings Sequential circuit design using flip-flops is used in the analysis of fuzzy digital logic switching technique. Originality/value The three-phase fragmented source configuration is designed using a split DC source which is obtained from the Opto-electric source and is implemented using MOSFET. The procedure of novel FDLST reduces the Statistical Harmonic Reduction (SHR). Simulation and results are carried out to prove the dominance of designed FDLST.
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Sidorenko, V. P., O. I. Radkevich, Yu V. Prokofiev, Yu V. Tayakin, and T. M. Virozub. "VLSI for a new generation of microelectronic coordinate-sensitive etectors with an extended field of analysis for use in mass spectrometry." Технология и конструирование в электронной аппаратуре, no. 1 (2018): 13–20. http://dx.doi.org/10.15222/tkea2018.1.13.
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The authors have developed a custom VLSI chip for the new generation of MCSD devices — multichip detectors with an extended analysis field and higher technical characteristics, which can be used in elemental analysis devices to simultaneously determine the elements that make up the material with high sensitivity and accuracy in real time. VLSI chip contains 384 channels with a spatial resolution of 25 microns has been integrated onto a single chip, each channel has a metal anode to collect the electrons as they emerge from the microchannel plate electron multiplier (MCP); a charge sensitive amplifier to produce a digital signal in response to the electron pulse and a 16-bit counter associated with it to accumulate the counts as they arrive and circuitry to read out the data sequentially from all channels in the microcircuit. The VLSI chip is designed according to the design rules standard 1,0 µm CMOS process. The speed of the microcircuit in the counting mode is at least 15 MHz, in the mode of reading information from the counters — more than 10 MHz. The output from the 16-bit counters on the detectors is presented via an 8-bit port and is read into the control electronics sequentially from each counter in turn in low-byte, high-byte order. The circuit has been designed in such a way that an arbitrary number of detector chips may be abutted together on a substrate behind the MCP, allowing for long focal plane detectors to be built, limited only by the size of MCPs available.
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Ghosh, Sumit. "A distributed algorithm for fault simulation of combinatorial and asynchronous sequential digital designs, utilizing circuit partitioning, on loosely-coupled parallel processors." Microelectronics Reliability 35, no. 6 (June 1995): 947–67. http://dx.doi.org/10.1016/0026-2714(93)e0021-z.
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Lima, Kollins Gabriel, and Maximiliam Luppe. "Restructuring the Digital Systems Laboratory in Computer Engineering Course." International Journal on Alive Engineering Education 5, no. 1 (October 4, 2018): 51. http://dx.doi.org/10.5216/ijaeedu.v5i1.50482.
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It's not difficult to find students of Computer Engineering, at the University of São Paulo, in São Carlos School of Engineering, complaining about the way that practical classes are given during the graduation. What is said is that these classes only reproduce results already seen in theory classes, that they are limited by a laboratory script and, at the end, nothing new is added to their knowledge, making them a little bit frustrated about the classes. In this paper, it's shown how PBL (Problem-based Learning) was used in Digital Systems Laboratory, a 4-semester discipline, to start a change in this situation. The main purpose of the project was to use all the knowledge in digital logic, already seen in theory classes by the students, to build the main modules of a basic processor: arithmetic logic unit (ALU), for combinational logic studies; register bank, for sequential logic studies; and control unity, used to study finite state machines. This new way to teach each topic of the discipline brought new challenges to the students, now free to solve them the way they wanted to, once only the specification of inputs and outputs were given. Using FPGA boards and circuit simulators for development, the students succeeded in their task and the modules were built and tested in a test platform, developed to allow the simulation of the entire processor. This project had a positive feedback, either reflected in grades (in laboratory and in related theoretical disciplines) and also in the student's motivation (although some difficulties was found) helping them to understand how different concepts seen during the graduation course are related. This feedback is now helping the development of a new material for next classes, in order to make specifications clearer, correct bugs in the test platform and improve some features for debug.
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Nawito, M., H. Richter, A. Stett, and J. N. Burghartz. "A programmable energy efficient readout chip for a multiparameter highly integrated implantable biosensor system." Advances in Radio Science 13 (November 3, 2015): 103–8. http://dx.doi.org/10.5194/ars-13-103-2015.
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Abstract. In this work an Application Specific Integrated Circuit (ASIC) for an implantable electrochemical biosensor system (SMART implant, Stett et al., 2014) is presented. The ASIC drives the measurement electrodes and performs amperometric measurements for determining the oxygen concentration, potentiometric measurements for evaluating the pH-level as well as temperature measurements. A 10-bit pipeline analog to digital (ADC) is used to digitize the acquired analog samples and is implemented as a single stage to reduce power consumption and chip area. For pH measurements, an offset subtraction technique is employed to raise the resolution to 12-bits. Charge integration is utilized for oxygen and temperature measurements with the capability to cover current ranges between 30 nA and 1 μA. In order to achieve good performance over a wide range of supply and process variations, internal reference voltages are generated from a programmable band-gap regulated circuit and biasing currents are supplied from a wide-range bootstrap current reference. To accommodate the limited available electrical power, all components are designed for low power operation. Also a sequential operation approach is applied, in which essential circuit building blocks are time multiplexed between different measurement types. All measurement sequences and parameters are programmable and can be adjusted for different tissues and media. The chip communicates with external unites through a full duplex two-wire Serial Peripheral Interface (SPI), which receives operational instructions and at the same time outputs the internally stored measurement data. The circuit has been fabricated in a standard 0.5-μm CMOS process and operates on a supply as low as 2.7 V. Measurement results show good performance and agree with circuit simulation. It consumes a maximum of 500 μA DC current and is clocked between 500 kHz and 4 MHz according to the measurement parameters. Measurement results of the on-chip ADC show a Differential Non Linearity (DNL) lower than 0.5 LSB, an Integral Non Linearity (INL) lower than 1 LSB and a Figure of Merit (FOM) of 6 pJ/conversion.
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Sun, Jian, and Wei Guo Lin. "Features Extraction of CO2 Signal with Operational Conditions Adaptability." Applied Mechanics and Materials 109 (October 2011): 131–35. http://dx.doi.org/10.4028/www.scientific.net/amm.109.131.
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A method for indirect online over-temperature detection of isolators in high voltage switchgear is proposed，which is based on Na Superionic Conductor CO2 sensor. The over-temperature detecting principle is put forward and an over-temperature detecting system based on the method is introduced. The reliability of over-temperature detection depends on signal noise ratio (SNR), but the sensor and signal processing determine the SNR of CO2 signal. Based on quantitative analysis, it is concluded that Na Superionic Conductor CO2 sensor has higher SNR. By signal processing, the necessity of moving average filter for SNR is demonstrated. A temperature compensation circuit is adopted to eliminate the influence of temperature. In view of the characteristics of rude signal, an appropriate method of real-time digital filtering is used to improve the Signal-to-Noise Ratio. The different features of the signal under over-temperature condition have been analyzed and compared to those under normal conditions. The paper introduces a reliable algorithm for identifying over-temperature detection based on sequential section differences. Experiments prove that the method is feasible.
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Agarwal, Neeraj, Neeru Agarwal, Chih-Wen Lu, and Masahito Oh-e. "A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application." Electronics 10, no. 14 (July 20, 2021): 1743. http://dx.doi.org/10.3390/electronics10141743.
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This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.
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Vishnoi, U., and T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies." Advances in Radio Science 10 (September 18, 2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.
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Abstract. The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz−1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.
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Malykhina, Galina, Dmitry Tarkhov, Viacheslav Shkodyrev, and Tatiana Lazovskaya. "Intelligent LED Certification System in Mass Production." Sensors 21, no. 8 (April 20, 2021): 2891. http://dx.doi.org/10.3390/s21082891.
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It is impossible to effectively use light-emitting diodes (LEDs) in medicine and telecommunication systems without knowing their main characteristics, the most important of them being efficiency. Reliable measurement of LED efficiency holds particular significance for mass production automation. The method for measuring LED efficiency consists in comparing two cooling curves of the LED crystal obtained after exposure to short current pulses of positive and negative polarities. The measurement results are adversely affected by noise in the electrical measuring circuit. The widely used instrumental noise suppression filters, as well as classical digital infinite impulse response (IIR), finite impulse response (FIR) filters, and adaptive filters fail to yield satisfactory results. Unlike adaptive filters, blind methods do not require a special reference signal, which makes them more promising for removing noise and reconstructing the waveform when measuring the efficiency of LEDs. The article suggests a method for sequential blind signal extraction based on a cascading neural network. Statistical analysis of signal and noise values has revealed that the signal and the noise have different forms of the probability density function (PDF). Therefore, it is preferable to use high-order statistical moments characterizing the shape of the PDF for signal extraction. Generalized statistical moments were used as an objective function for optimization of neural network parameters, namely, generalized skewness and generalized kurtosis. The order of the generalized moments was chosen according to the criterion of the maximum Mahalanobis distance. The proposed method has made it possible to implement a multi-temporal comparison of the crystal cooling curves for measuring LED efficiency.
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"Compact QCA based JK Flip-Flop for Digital System." International Journal of Innovative Technology and Exploring Engineering 8, no. 12 (October 10, 2019): 3182–85. http://dx.doi.org/10.35940/ijitee.l3074.1081219.
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Considering the roadmap of silicon, the high rate of shrinkage in dimensions of typical MOS circuits, genuine difficulties endanger this innovation. A quantum-dot cellular automaton (QCA) is an outstanding and conceivable answer for substitution of CMOS technology. Sequential circuits contain combinational circuits and memory elements which store binary information. Latches and Flip-flop circuits are the basic components of computerized circuits, along these lines. The area and energy of the sequential circuits has to be minimal for speed applications. Traditional implementation of JK flip-flop circuits requires more cells and consumes more energy. This paper proposes a compact and low energy JK Flip-flop, designed in CAD tool, QCADesigner. Analysis of energy was performed using the CAD tool, QCADesigner-E. The experimental results obtained in the proposed paper demonstrate the reduction in the cell count which in turn brings down the complexity of the circuit when compared to the reference QCA based JK Flip-flop circuits and it also shows a reduction in energy and area.