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Journal articles on the topic 'Semiconductor failure analysis'

Author: Grafiati

Published: 28 June 2021

Last updated: 17 February 2022

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1

Rice, Larry. "Semiconductor Failure Analysis Using EBIC and XFIB." Microscopy and Microanalysis 7, S2 (August 2001): 514–15. http://dx.doi.org/10.1017/s1431927600028646.

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Electron beam induced current (EBIC) is the common term used in the semiconductor industry for the failure analysis and yield enhancement of semiconductor devices using SEM to electrically pinpoint leakage sites. EBIC is a useful technique for locating defects in diodes, transistors, and capacitors where the scanning electron microscope beam is used to generate a signal and the sample is the detector. Often during yield enhancement efforts the failure analyst is asked to determine the mechanism for which a PC structure (which may contain as many as a few hundred thousand structures in one device) is failing tests. Blind cross sections rarely give evidence of the failure mechanism. EBIC can be used to pinpoint the bad site which is then precision cross-sectioned using the focused ion beam (FIB).When an electron beam impinges on a semiconductor such as silicon, electron-hole pairs are created when the incident beam transfers enough energy to promote an electron from the valance band to the conduction band.

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2

Ebersberger, B., A. Olbrich, and C. Boit. "Scanning probe microscopy in semiconductor failure analysis." Microelectronics Reliability 41, no. 8 (August 2001): 1231–36. http://dx.doi.org/10.1016/s0026-2714(01)00109-3.

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3

Tong, XT, L. Pan, B. Miner, K. Johnson, S. Subramaniam, and M. Sacks. "Role of Microscopy in Advanced Semiconductor Failure Analysis." Microscopy and Microanalysis 16, S2 (July 2010): 798–99. http://dx.doi.org/10.1017/s1431927610055728.

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4

Baumann, Frieder H., Brian Popielarski, Travis Mitchell, and Yinggang Lu. "Towards Routine EDX Tomography in Semiconductor Failure Analysis." Microscopy and Microanalysis 25, S2 (August 2019): 1820–21. http://dx.doi.org/10.1017/s1431927619009838.

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5

Sun, Tianyu, Lei Qiao, and Mingjun Xia. "Effective Failure Analysis for Packaged Semiconductor Lasers with a Simple Sample Preparation and Home-Made PEM System." Photonics 8, no. 6 (May 24, 2021): 184. http://dx.doi.org/10.3390/photonics8060184.

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As the application requirements of semiconductor lasers continue to increase, severe challenges are brought to the reliability of semiconductor lasers. In order to promote the study of laser failure, this paper proposes an effective failure analysis method for packaged semiconductor lasers with a simple sample preparation and home-made photon emission microscopy (PEM) system. The new simple sample preparation process for failure analysis is presented and the necessary polishing fixture is designed so that sample can be obtained without expensive and complex micro-/nano-processing. Two types of home-made PEM experimental systems were established for observing the failure from the front facet and active region of semiconductor lasers. Experimental results showed that, with the proposed sample preparation flow, the home-made PEM experimental system effectively observed the leakage defects from the front facet and dark spot defects (DSDs) in the active region of semiconductor lasers. The method can help researchers and laser manufactures to perform effective failure analysis of packaged semiconductor lasers.

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Tanbakuchi, Hassan. "Nanoscale Non-Destructive Semiconductor Dopant Characterization and Failure Analysis." ECS Transactions 27, no. 1 (December 17, 2019): 151–56. http://dx.doi.org/10.1149/1.3360611.

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7

McDonald, Robert C., A. John Mardinly, and David W. Susnitzky. "Imaging and Analytical Challenges for Nanoscale Semiconductor Technology: Breakthrough Needs for Development and Manufacturing." Microscopy and Microanalysis 3, S2 (August 1997): 449–50. http://dx.doi.org/10.1017/s1431927600009132.

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The complexity of today’s commercial semiconductors has contributed to tremendous gains in device performance; millions of transistors are now packed into each square centimeter of silicon. The reduction of scale occurring within the semiconductor industry places extraordinary new demands on transmission electron microscopy: TEM is becoming a required precision measurement tool for manufacturing and a necessary analytical tool for R&D and failure analysis support. This paper reviews the industry’s needs for advanced TEM sample preparation, imaging and microanalysis and outlines the challenges presented to the TEM community as device dimensions continue along the National Technology Roadmap.In the semiconductor industry, TEM is applied to process debugging, yield engineering, tool qualifications, single-bit failure analyses, and new process development. A large fraction of the analysis effort focuses on transistor, metal, interconnect and dielectric structures grown on and into the Si wafer. Fig. 1 shows a TEM image of a multilayer metal in a near-current generation microprocessor to illustrate the scale and nature of complexity.

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8

Ding, Siew Hong, Nur Amalina Muhammad, Nur Hanisah Zulkurnaini, Amanina Nadia Khaider, and Shahru Kamaruddin. "Production System Improvement by Integration of FMEA with 5-Whys Analysis." Advanced Materials Research 748 (August 2013): 1203–7. http://dx.doi.org/10.4028/www.scientific.net/amr.748.1203.

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With the rapid growth of semiconductor industry, manufacturers are always seeking for improvement to produce better product quality with lower cost in order to survive under competitive marketing environment. However, these matters are easily affected by the failures occurred on the machines. Thus, this paper proposes framework using failure mode and effect analysis (FMEA) with 5-Whys analysis to discover the root cause of the failure furthermore to identify the effective solutions. Drilling machine has been used to justify the practicability of the proposed framework.

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9

Ozguc, Murat Kubilay, Eymen Ipek, Kadir Aras, and Koray Erhan. "Comprehensive Analysis of Pre-Charge Sequence in Automotive Battery Systems." Transactions on Environment and Electrical Engineering 4, no. 1 (December 25, 2019): 1. http://dx.doi.org/10.22149/teee.v4i1.136.

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<p>Electric vehicles (EV) have brought promising technologies for future mobility solutions. As one of the key components of EVs, battery systems have fundamental functions which disconnect the battery during parking and in case of failure. To provide a safe system, specialized high voltage (HV) electromechanical switches are used to perform these major functions such as switch on, switch off or pre-charging. Due to these components can be easily damaged, expensive, heavy and bulky, a solution based on pure semiconductors may be desired to accomplish these operations. Many studies were exhibited on EV battery systems regarding developing solid-state systems for HV switchgear. Developing technology on semiconductor devices allows to make a safety concept based on only solidstate components. This study presents a comprehensive analysis off pre-charge sequences between conventional and semiconductor switchgear to be used in electric vehicle battery systems. Spice simulations are presented to investigate advantages and drawbacks of these systems.</p>

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10

Glacet, J. Y., and G. Guerri Dall'oro. "Low-cost physical analysis techniques for the failure analysis of semiconductor components." Quality and Reliability Engineering 8, no. 2 (1992): 93–98. http://dx.doi.org/10.1002/qre.4680080204.

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11

Leo, Jacobus, Hao Tan, Yinzhe Ma, Shreyas M. Parab, Yamin Huang, Dandan Wang, Lei Zhu, Jeffrey Lam, and Zhihong Mai. "Key Issues for Implementing Smart Polishing in Semiconductor Failure Analysis." Journal of Applied Mathematics and Physics 05, no. 09 (2017): 1668–77. http://dx.doi.org/10.4236/jamp.2017.59139.

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12

Inuzuka, Eiji. "Failure analysis of semiconductor devices by means of photon emission." JOURNAL OF THE ILLUMINATING ENGINEERING INSTITUTE OF JAPAN 75, Appendix (1991): 241–42. http://dx.doi.org/10.2150/jieij1980.75.appendix_241.

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13

Ebersberger, B., A. Olbrich, and C. Boit. "Application of Scanning Probe Microscopy techniques in Semiconductor Failure Analysis." Microelectronics Reliability 41, no. 9-10 (September 2001): 1449–58. http://dx.doi.org/10.1016/s0026-2714(01)00187-1.

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14

Barry, D. M. "Reliability Analysis and Failure Cause Determination in Encapsulated Semiconductor Devices." International Journal of Quality & Reliability Management 2, no. 2 (February 1985): 33–46. http://dx.doi.org/10.1108/eb002847.

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15

Sun, Peipei, Zhirong Wang, Yawei Lu, Shuoxun Shen, Rongrong Yang, Anxue Xue, Trent Parker, Jian Wang, and Qingsheng Wang. "Analysis of the corrosion failure of a semiconductor polycrystalline distillation column." Process Safety and Environmental Protection 135 (March 2020): 244–56. http://dx.doi.org/10.1016/j.psep.2020.01.007.

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16

Amy Hunt, C. "Comparison of Precision XTEM Specimen Preparation Techniques for Semiconductor Failure Analysis." Microscopy and Microanalysis 3, S2 (August 1997): 357–58. http://dx.doi.org/10.1017/s1431927600008679.

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The demand for TEM analysis in semiconductor failure analysis is rising sharply due to the shrinking size of devices. A well-prepared sample is a necessity for getting meaningful results. In the past decades, a significant amount of effort has been invested in improving sample preparation techniques for TEM specimens, especially precision cross-sectioning techniques. The most common methods of preparation are mechanical dimpling & ion milling, focused ion beam milling (FIBXTEM), and wedge mechanical polishing. Each precision XTEM technique has important advantages and limitations that must be considered for each sample.The concept for both dimpling & ion milling and wedge specimen preparation techniques is similar. Both techniques utilize mechanical polishing to remove the majority of the unwanted material, followed by ion milling to assist in final polishing or cleaning. Dimpling & ion milling produces the highest quality samples and is a relatively easy technique to master.

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17

Engelmann, H. J., H. Saage, and E. Zschech. "Application of analytical TEM for failure analysis of semiconductor device structures." Microelectronics Reliability 40, no. 8-10 (August 2000): 1747–51. http://dx.doi.org/10.1016/s0026-2714(00)00107-4.

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18

Uenoyama, Soh, Yu Takiguchi, Koji Takahashi, Kazuyoshi Hirose, Hirotoshi Terada, and Akiyoshi Watanabe. "Contact metalens for high-resolution optical microscope in semiconductor failure analysis." Optics Letters 45, no. 22 (November 10, 2020): 6218. http://dx.doi.org/10.1364/ol.410376.

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19

Hofmann, S. "Surface and Thin Film Analysis of Metals and Semiconductors using X-Ray Photoelectron Spectroscopy." Advances in X-ray Analysis 35, B (1991): 883–97. http://dx.doi.org/10.1154/s0376030800013094.

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AbstractX-ray excited Photoelectron Spectroscopy (XPS) has become an indispensable tool for the study of metals and semiconductors. Due to the small mean free path of the photoelectrons In solids of the order of a few nanometers for energies in the keV range, it is a surface analysis technique. Its capability of quantitative analysis of all elements except hydrogen and helium and their chemical bonding states has recently been combined with small area and imaging analysis to typical spatial resolutions of about 10 μm. After a brief survey of the basic capabilities and limitations of XPS, some illustrative examples in typical metals and semiconductor research areas are presented, such as surface contamination and failure analysis in microelectronics, oxidation and corrosion, segregation at surfaces and interfaces, oxide/metal and oxide/semiconductor interfaces, and thin film analysis using angle resolved XPS and sputter depth profiling. Recent developments emphasize improved data evaluation and quantification schemes as well as instrumental capabilities with respect to both high spatial and energy resolution, and high power excitation sources such as synchrotron radiation.

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20

Fragoudakis, Roselita, Michael A. Zimmerman, and Anil Saigal. "Application of a Ag Ductile Layer in Minimizing Si Die Stresses in LDMOS Packages." Key Engineering Materials 605 (April 2014): 372–75. http://dx.doi.org/10.4028/www.scientific.net/kem.605.372.

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Lateral Diffused Metal Oxide Semiconductors (LDMOS) normally have a Cu-W flange, whose CTE is matched to Si. Low cost Cu substrate material provides 2X high thermal conductivity, and along with a AuSi eutectic solder is recommended for optimal thermal performance. However, the CTE mismatch between Cu and Si can lead to failure of the semiconductor as a result of die fracture, due to thermal stresses developed during the soldering step of the manufacturing process. Introducing a Ag ductile layer is very important in minimizing such thermal stresses and preventing catastrophic failure of the semiconductor. Ag is a ductile material electroplated on the Cu substrate to absorb stresses developed during manufacturing due to the CTE mismatch between Si and Cu. The Ag layer thickness affects the magnitude of the resulting thermal stresses. This study attempts to measure the yield strength of the Ag layer, and examines the optimal layer thickness to minimize die stresses and prevent failure. The yield stress of the ductile layer deposited on a Cu flange was measured by nanoindentation. The Oliver and Pharr method was applied to obtain modulus of elasticity and yield depth of Ag. A finite element analysis of the package was performed in order to map die stress distribution for various ductile layer thicknesses. The analysis showed that increasing the ductile layer thickness up to 0.01 - 0.02 mm, decreases the Si die stresses.

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21

Zschech, Ehrenfried, Eckhard Langer, Hans-Juergen Engelmann, and Kornelia Dittmar. "Physical failure analysis in semiconductor industry—challenges of the copper interconnect process." Materials Science in Semiconductor Processing 5, no. 4-5 (August 2002): 457–64. http://dx.doi.org/10.1016/s1369-8001(02)00124-5.

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22

ABDULLAH, SHAHRUM, AHMAD KAMAL ARIFFIN, CHE KU EDDY NIZWAN, MOHAMAD FAIZAL ABDULLAH, AZMAN JALAR, and MOHD FARIDZ MOD YUNOH. "FAILURE ANALYSIS OF A SEMICONDUCTOR PACKAGING LEADFRAME USING THE SIGNAL PROCESSING APPROACH." International Journal of Modern Physics B 24, no. 01n02 (January 20, 2010): 175–82. http://dx.doi.org/10.1142/s0217979210064101.

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This paper presents a durability analysis of two types of copper leadframe, i.e. the un-oxidised leadframe and the oxidised leadframe. Both leadframe types were used in the fabrication process of a Quad Flat No-Lead (QFN) package, which can be said as a recent type of the 3D stacked die semiconductor package. This study involved the durability test and analysis on QFN packages when these packages were subjected under constant cyclic loadings. In order to perform the cyclic test, the procedure of the three-point cyclic bending test has been employed on the packages. In addition, a strain gauge which was connected to the dynamic data acquisition system was used for each tested QFN package for determining the response of the captured cyclic strain signal. It has been found that the variable amplitude pattern of signal response has been obtained during the constant cyclic test. The obtained response signals for both type of leadframe were then analysed using the approaches of signal processing technique, which is relatively new in this field. The collected response signal were analysed using the normal statistical methods, the Power Spectrum Density (PSD) calculation and also the time-frequency localization analysis. From the detail signal analysis, it has been found that the un-oxidised leadframe showed a lower range of strain response compared to the oxidised leadframe, indicating higher lifetime. As a result, this finding lead to the durability conclusion, for which the un-oxidised leadframe has more durability effects and it also has higher lifetime compared to the oxidised leadframe. Finally, a micro-crack phenomenon at the epoxy interface between the die and the leadframe was also observed for the QFN package with the oxidised leadframe.

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23

Ko, Po Sheng, and Cheng Chung Wu. "Manufacturing Process Planning to Evaluation on Failure Causes for Lithography Machine: Analytic Hierarchy Process." Advanced Materials Research 213 (February 2011): 450–53. http://dx.doi.org/10.4028/www.scientific.net/amr.213.450.

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This study conducted hierarchical analysis on the evaluation item of the stability index of the lithography machine, and established a set of evaluation mechanism for failure prediction, in order to provide references and indicators of troubleshooting for lithography machine. The results showed, when the lithography machine is out of order, the possible failure causes are mainly be found based on the past experiences. Moreover, engineers’ skills in maintenance of lithography machine should be also considered. It is clear that, technology-centered is the current trend in today's semiconductor technology processing. In the weight analysis of rating index for complexity in broken Wafer, the most important problem is the lithography machine error due to failure in its components. Good design and configuration of semiconductor lithography process in the early stage can enhance the rapid maintenance of lithography machine in case of malfunctioning effectively. For timely maintenance, maintaining the organization stringency needs to be improved. This study also found that, under the good configuration of maintenance system, adequate information is closely associated a good system. As for lithography process in semiconductor industry, the complexity of broken Wafer is first considered. Thus, the overall lithography process of semiconductor relies on engineers’ experience. More specifically, a quick error interpretation and repair are required in field maintenance. As in a competitive market of semiconductor processing with high-tech and high-cost, a timely maintenance in the lithography machine is urgent and requested.

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24

Qin, Guoshuai, Chunsheng Lu, Xin Zhang, and Minghao Zhao. "Electric Current Dependent Fracture in GaN Piezoelectric Semiconductor Ceramics." Materials 11, no. 10 (October 16, 2018): 2000. http://dx.doi.org/10.3390/ma11102000.

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In this paper, the fracture behavior of GaN piezoelectric semiconductor ceramics was investigated under combined mechanical and electric loading by using three-point bending tests and numerical analysis. The experimental results demonstrate that, in contrast to traditional insulating piezoelectric ceramics, electric current is a key factor in affecting the fracture characteristics of GaN ceramics. The stress, electric displacement, and electric current intensity factors were numerically calculated and then a set of empirical formulae was obtained. By fitting the experimental data, a fracture criterion under combined mechanical and electrical loading was obtained in the form of an ellipsoid function of intensity factors. Such a fracture criterion can be extended to predict the failure behavior of other piezoelectric semiconductors or devices with a crack, which are useful in their reliability design and applications.

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25

Henning, A. K., and T. Hochwitz. "Scanning probe microscopy for 2-D semiconductor dopant profiling and device failure analysis." Materials Science and Engineering: B 42, no. 1-3 (December 1996): 88–98. http://dx.doi.org/10.1016/s0921-5107(96)01688-1.

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26

Yeoh, Terence S., John A. Chaney, Martin S. Leung, Neil A. Ives, Z. D. Feinberg, James G. Ho, and Jianguo Wen. "Three-dimensional failure analysis of high power semiconductor laser diodes operated in vacuum." Journal of Applied Physics 102, no. 12 (December 15, 2007): 123104. http://dx.doi.org/10.1063/1.2821151.

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27

Tan, S. L., K. W. Chang, S. J. Hu, and Ken K. S. Fu. "Failure analysis of die-attachment on static random access memory (SRAM) semiconductor devices." Journal of Electronic Materials 16, no. 1 (January 1987): 7–11. http://dx.doi.org/10.1007/bf02667785.

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28

Khong, Benjamin, Marc Legros, Philippe Dupuy, Colette Levade, and Guy Vanderschaeve. "On the Failure of Intelligent Power Devices Induced by Extreme Electro-Thermal Fatigue. A Microstructural Analysis." Solid State Phenomena 131-133 (October 2007): 523–28. http://dx.doi.org/10.4028/www.scientific.net/ssp.131-133.523.

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Microstructural analysis of power devices were carried out on components from Freescale Semiconductor that underwent extreme electro-thermal fatigue. Several destructive and non destructive techniques were used. It is shown that the main cause of devices failure is delamination between the heat sink and the power die. Additional causes of failure are identified. The fatigue-induced modifications of the structure of the metallization layer (grain growth, grain boundary grooving) is also discussed.

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29

Rastayesh, Sima, Sajjad Bahrebar, Amir Sajjad Bahman, John Dalsgaard Sørensen, and Frede Blaabjerg. "Lifetime Estimation and Failure Risk Analysis in a Power Stage Used in Wind-Fuel Cell Hybrid Energy Systems." Electronics 8, no. 12 (November 26, 2019): 1412. http://dx.doi.org/10.3390/electronics8121412.

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This paper presents a methodology based on the failure mode and effect analysis (FMEA) to analyze the failures in the power stage of wind-fuel cell hybrid energy systems. Besides, fault tree analysis (FTA) is applied to describe the probabilistic failures in the vital subcomponents. Finally, the reliability assessment of the system is carried out for a five-year operation that is guaranteed by the manufacturer. So, as the result, the reliability analysis proves that the metal oxide semiconductor field effect transistor (MOSFET) and electrolytic capacitor are the most critical components that introduce damages in the power circuit. Moreover, a comparative study on the reliability assessment by the exponential distribution and the Weibull distribution show that the B1 lifetime obtained by the Weibull distribution is closer to reality.

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30

Wu, Dong Yan, Zhi Liang Tan, Li Yun Ma, and Peng Hao Xie. "The Failure Modeling Analysis of Bipolar Silicon Transister Device Caused by ESD." Applied Mechanics and Materials 427-429 (September 2013): 929–32. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.929.

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With the development of electronic technology, the electronic threats faced by microwave semiconductor devices was increasingly serious.In order to study the electrostatic discharge damage mechanism of bipolar silicon transistors, this paper analyzed the basic physical characteristics of bipolar transistor in electrostatic discharge, such as kirk effect and current crowding effect. Through analysis the human body electrostatic discharge model, established the ESD electric injury model of bipolar silicon transistor. If we knew the production process parameter of devices, we can calculate the ESD damage threshold for designing bipolar silicon device and providing a theoretical basis of parameter optimization. Finally the common ESD damage criterion were analyzed from different angles.

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31

Deshmukh, Manthan, Rohan Dumbre, Shubham Anekar, Heramb Kulkarni, and Sushant Pawar. "Condition Monitoring and Predictive Maintenance of Process Equipments." ITM Web of Conferences 40 (2021): 01003. http://dx.doi.org/10.1051/itmconf/20214001003.

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Industry 4.0 the proclaimed fourth industrial revolution is unfolding at the moment. It is characterized by interconnectedness and vast amounts of available information. Industrial production has evolved enormously over the last centuries due to modern instruments. Hence issue of the instrument failure is very paramount in any industry. Even if one machine fails it halts the whole production. Overall, it may cost us with more man-hours, project delay, process latency and all this sums up as a huge loss. The life of the instruments should be taken care by continuously monitoring its health. Any faulty or unnatural disturbance in usage of the instrument may lead to its failure. Every instrument needs proper maintenance, even with the slight negligence towards the anomaly it may lead to instrument failure. In, predictive maintenance historic data is utilized and analyzed with the help of advance analytics and modelling techniques using Machine learning, moreover we can predict failures and can schedule the maintenance beforehand and predict failure in advance. With the help of relevant sensor dataset, we can estimate the remaining runtime of the instruments. This maintenance approach helps to lower the costs which are incurred due to system shut downs. It also ease the scheduling and maintenance activities.In this work, three different industrial case studies are considered like shell and tube type heat exchanger, plate type heat exchanger, and semiconductor manufacturing process.Here the predictive maintenance is carried out for heat exchanger by utilizing the concept of multi linear regression and time series analysis. For the semiconductor manufacturing dataset, support vector machine algorithm is implemented to find out the good and bad quality of semiconductor production slots.

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32

Wu, Jun Hui, Quan Zhou, Qiang Zhou, Jie Chen, Hui Ping Si, Kai Yan Lin, and Chi Bin Zhang. "Thermal Design, Analysis and Verification of Chip-Level MCM with Properties of Semiconductor Materials." Advanced Materials Research 625 (December 2012): 280–86. http://dx.doi.org/10.4028/www.scientific.net/amr.625.280.

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A lot of practice had proved that the failure rate can be used as the reliability indicators of MCM (Multi-Chip Module). The lower the junction temperature of the semiconductor integrated circuit device in MCM, the lower the failure rate of components was, thus the higher the reliability of MCM. Therefore, in order to measure the junction temperature of the semiconductor components of MCM, computer simulation is needed in the stage of design，which was essential for improving the reliability of MCM’s encapsulation and even the whole electronic machine system. In this paper, we tried to thermal design the high-power heating devices-MCM of the multi-functional electronic devices. First, the cooling principles of MCM encapsulation were introduced. And then based on the design principles and precautions of MCM, we designed an MCM encapsulation for cooling analyses of ANSYS. The results of finite element analyses showed the reasonableness of the design of MCM, and combined with the different substrate materials and circuit board materials, further discusses about improved cooling capability of MCM were expressed in this paper. At last, we got the desired effect.

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33

Sato, Soshi, Kikuo Yamabe, Tetsuo Endoh, and Masaaki Niwa. "Failure Analysis of a SiC MOS Capacitor with a Poly-Si Gate Electrode." Materials Science Forum 858 (May 2016): 485–88. http://dx.doi.org/10.4028/www.scientific.net/msf.858.485.

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The failure mechanism of a SiC metal-oxide-semiconductor capacitor with a poly-Si gate electrode was investigated by time-dependent dielectric breakdown testing under a 200-nA constant current stress. The capacitor exhibited both hard and soft breakdowns. After dielectric breakdown in both cases, adjacent concaves were observed on the capacitor with a field-emission scanning electron microscope. Additional optical beam-induced resistance changes and photo-emission analysis of a capacitor after hard-breakdown located a failure point on the periphery of a group of adjacent concaves. Cross-sectional scanning transmission electron microscope observation revealed that a narrow, vertical defect had formed at this point on the SiC substrate.

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34

Chin, Jiann Min, Vinod Narang, Xiaole Zhao, Meng Yeow Tay, Angeline Phoa, Venkat Ravikumar, Lwin Hnin Ei, et al. "Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview." Microelectronics Reliability 51, no. 9-11 (September 2011): 1440–48. http://dx.doi.org/10.1016/j.microrel.2011.06.061.

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35

Paul, Erik, Holger Herzog, Sören Jansen, Christian Hobert, and Eckhard Langer. "SEM-based nanoprobing on 32 and 28nm CMOS devices challenges for semiconductor failure analysis." Microelectronics Reliability 54, no. 9-10 (September 2014): 2115–17. http://dx.doi.org/10.1016/j.microrel.2014.07.133.

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36

Shimoda, Yoshio, and Hidetaka Satoh. "Waveform Dependence of Surge-handling Capability and Failure Analysis for Semiconductor Lightning Surge Protectors." Japanese Journal of Applied Physics 34, Part 1, No. 11 (November 15, 1995): 5993–97. http://dx.doi.org/10.1143/jjap.34.5993.

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37

Basaran, C., and R. Chandaroy. "Nonlinear Dynamic Analysis of Surface Mount Interconnects: Part I—Theory." Journal of Electronic Packaging 121, no. 1 (March 1, 1999): 8–11. http://dx.doi.org/10.1115/1.2792663.

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Solder joints are commonly used in surface mount technology microelectronics packaging. It is well known that the dominant failure mode for solder joints is thermal fatigue. When semiconductor devices are used in a vibrating environment, such as in automotive and military applications, dynamic stresses contribute to the failure mechanism and in certain circumstances they can become the dominant failure cause. In this paper a unified constitutive model for Pb40/Sn60 solder joints is developed and then implemented in a finite element dynamic analysis procedure. The purpose of the material model and the implementation is to study the contribution of vibration induced strains to the fatigue life of solder interconnects in low cycle and high cycle fatigue. The proposed material model, which is based on the disturbed state concept (DSC), is used for a dynamic analysis of a solder joint in the following paper, Part II, Basaran and Chandaroy (1998).

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38

Valentine, Nathan, Diganta Das, Bhanu Sood, and Michael Pecht. "Failure Analyses of Modern Power Semiconductor Switching Devices." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000690–95. http://dx.doi.org/10.4071/isom-2015-tha56.

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Power semiconductor switches such as Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) continue to be a leading cause of failure in power electronics systems. With the continued expansion of the power electronics market, reliable switching devices are of utmost importance in maintaining reliable operation of high power electronic systems. An overview of the failure mechanisms of power semiconductor switches identified by two failure analyses at CALCE is presented. The specific applications of power semiconducting switches have a wide range and include semiconductors found in converters for AC/DC power supplies and home appliance motor control board. All observed failures were from devices which experienced a short circuit between the collector and emitter terminals. The causes of the failures are hypothesized to be a combination of manufacturing defects and poor thermal management.

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Lakshminarayanan, V., and N. Sriraam. "Proposed Solution to the Problem of Thermal Stress Induced Failures in Medical Electronic Systems." International Journal of Biomedical and Clinical Engineering 3, no. 2 (July 2014): 33–41. http://dx.doi.org/10.4018/ijbce.2014070103.

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The concept of miniaturization has propagated to all types of electronic applications. The complexity of electronic systems has been increasing due to increase in the number of functions and features offered to the users. At the same time the number of devices working per unit volume of the system has increased enormously, due to which the power density per unit volume has increased. Dissipating high power in small volumes has increased the thermal problems in all types of electronic systems, including medical gadgets. Thermal stress has been identified to be the major cause of failure of electronic devices in electronic systems, based on the analysis of failures, based on research work. The causative mechanism of failure of semiconductor device package due to thermal overstress in medical electronic systems is the differential expansion between plastic and metal parts of the device which causes a differential strain and package failure. Selection of materials with similar coefficient of thermal expansion is important to prevent thermal overstress caused failures. In this paper, we discuss a technique which uses mathematical analysis to provide a solution to this problem of selecting the suitable material to prevent differential thermal stress failures in medical electronics systems.

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Khanna, Sumeer, Patrick McCluskey, Avram Bar-Cohen, Bao Yang, and Michael Ohadi. "Thin Thermally Efficient ICECool Defense Semiconductor Power Amplifiers." Journal of Microelectronics and Electronic Packaging 14, no. 3 (July 1, 2017): 77–93. http://dx.doi.org/10.4071/imaps.456518.

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Abstract Traditional power electronics for military and fast computing applications are bulky and heavy. The “mechanical design” of electronic structure and “materials” of construction of the components have limitations in performance under very high temperature conditions. The major concern here is “thermal management.” To be more specific, this refers to removal of high-concentration hotspot heat flux >5 kW/cm2, background heat flux >1 kW/cm2, and “miniaturization” of device within a substrate thickness of <100 μm. We report on the novel applications of contact-based thermoelectric cooling (TEC) to successful implementations of high-conductivity materials - diamond substrate grown on gallium nitride (GaN)/AlGaN transistors to keep the hotspot temperature rise of device below 5 K. The requirement for smarter and faster functionality along with a compact design is considered here. These efforts have focused on the removal of higher levels of heat flux, heat transfer across interface of junction and substrate, advanced packaging and manufacturing concepts, and integration of TEC of GaN devices to nanoscale. The “structural reliability” is a concern and we have reported the same in terms of mean time to failure (cycles) of SAC305 (96.5% tin, 3% silver, 0.5% cu) solder joint by application of Engelmaier's failure model and evaluation of stresses in the structure. The mathematical equation of failure model incorporates the failure phenomena of fatigue and creep in addition to the dwell time, average solder temperature, and plastic strain accumulation. The approach to this problem is a nonlinear finite element analysis technique, which incorporates thermal, mechanical, and thermoelectric boundary conditions.

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Rastayesh, Sima, Sajjad Bahrebar, Frede Blaabjerg, Dao Zhou, Huai Wang, and John Dalsgaard Sørensen. "A System Engineering Approach Using FMEA and Bayesian Network for Risk Analysis—A Case Study." Sustainability 12, no. 1 (December 20, 2019): 77. http://dx.doi.org/10.3390/su12010077.

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This paper uses a system engineering approach based on the Failure Mode and Effect Analysis (FMEA) methodology to do risk analysis of the power conditioner of a Proton Exchange Membrane Fuel Cell (PEMFC). Critical components with high risk, common cause failures and effects are identified for the power conditioner system as one of the crucial parts of the PEMFCs used for backup power applications in the telecommunication industry. The results of this paper indicate that the highest risk corresponds to three failure modes including high leakage current due to the substrate interface of the metal oxide semiconductor field effect transistor (MOSFET), current and electrolytic evaporation of capacitor, and thereby short circuit, loss of gate control, and increased leakage current due to gate oxide of the MOSFET. The MOSFETs, capacitors, chokes, and transformers are critical components of the power stage, which should be carefully considered in the development of the design production and implementation stage. Finally, Bayesian networks (BNs) are used to identify the most critical failure causes in the MOSFET and capacitor as they are classified from the FMEA as key items based on their Risk Priority Numbers (RPNs). As a result of BNs analyses, high temperature and overvoltage are distinguished as the most crucial failure causes. Consequently, it is recommended for designers to pay more attention to the design of MOSFETs’ failure due to high leakage current owing to substrate interface, which is caused by high temperature. The results are emphasizing design improvement in the material in order to be more resistant from high temperature.

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Huang, Feng. "Cause Analysis and Countermeasures of a Breakdown Failure of Flexible 110 kV Cable Terminal." E3S Web of Conferences 38 (2018): 04004. http://dx.doi.org/10.1051/e3sconf/20183804004.

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disintegration examination and analysis are employed in flexible terminal breakdown of 110 kV XLPE insulated cables. It is considered that the main reason of breakdown is the separation of the stress cone of the terminal and the fracture of the semi- conductive layer of the cable insulation. Therefore, the finite element method is used to electric field model and simulate the dislocation fault of internal stress cone and outer semiconductor layer of cable insulation. The distribution of the electric field intensity is calculated and compared. The simulation and calculation results verify the validity of the breakdown mechanism analysis, and put forward some practical suggestions.

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Mena, Manolo G. "Analysis of Dendrite Images Formed by Electrochemical Migration in a Semiconductor Sensor." Materials Science Forum 916 (March 2018): 207–11. http://dx.doi.org/10.4028/www.scientific.net/msf.916.207.

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Dendrites were observed in the failure of semiconductor sensor devices. EDX analysis showed that the dendrites grown from bare sensor dice consisted of tin metal. The tin dendrites exhibited massive and dense branches. Dendrites grown from mechanically decapped parts consisted of silver. The silver dendrites exhibited delicate, lace-like structure. Binary and grey scale images of dendrites were analyzed for fractal dimension number and branch density. The tin dendrites had a higher, statistically significant branch density number than silver, due to tin’s more intricate branching pattern. Fractal numbers can be used to differentiate between tin and silver dendrites, even in the absence of EDX analysis equipment.

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Rai, Raghaw S., and Swaminathan Subramanian. "Role of transmission electron microscopy in the semiconductor industry for process development and failure analysis." Progress in Crystal Growth and Characterization of Materials 55, no. 3-4 (September 2009): 63–97. http://dx.doi.org/10.1016/j.pcrysgrow.2009.09.002.

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Litz-Montanaro, Lisa. "The Art of Tungsten Etching in Semiconductor Chips." Microscopy Today 7, no. 2 (March 1999): 24–25. http://dx.doi.org/10.1017/s1551929500063902.

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In the course of both physical and failure analysis of semiconductor chips (i.e., verifying what you actually deposited as a layer, vs, what caused the circuit to fail), it is essential to have appropriate deprocessing tools at your disposal in order to evaluate complex semiconductor structures, Deprocessing techniques are developed for each product manufactured and involve multi-step procedures that reveal the layer-by-layer secrets of the chip, These techniques require constant tweaking in duration and procedure as the manufacturing process imposes changes and as the architecture of the semiconductor changes. While there are many tools that assist in these analytical pursuits, such as RIE (reactive ion etching - a dry etching technique), ion milling, and microcleaving, the wet chemical etching of tungsten is sometimes more reproducible than RIE techniques.

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Asghar, Muhammad Talal, Thomas Frank, and Frank Schwierz. "Failure Analysis of Wire Bonding on Strain Gauge Contact Pads Using FIB, SEM, and Elemental Mapping." Engineering Proceedings 6, no. 1 (May 17, 2021): 53. http://dx.doi.org/10.3390/i3s2021dresden-10142.

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Stacks consisting of titanium, platinum, and gold layers constitute a popular metallization system for the bond pads of semiconductor chips. Wire bonding on such layer stacks at different temperatures has extensively been investigated in the past. However, reliable information on the bondability of this metallization system after a high-temperature sintering process is still missing. When performing wire bonding after pressure sintering (at, e.g., 875 °C), bonding failures may occur that must be identified and analyzed. In the present study, a focused ion beam (FIB), scanning electron microscopy (SEM), and elemental mapping are utilized to characterize the root cause of failure. As a probable root cause, the infusion of metallization layers is found which causes an agglomerate formation at the interface of approximately 2 μm height difference on strain gauge contact pads and possibly an inhomogeneous mixing of layers as a consequence of the high-temperature sintering process. Potential treatment to tackle this agglomeration with the removal of the above-mentioned height difference during the process of contact pad structuring and alternative electrical interconnect methodologies are hereby suggested in this paper.

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Subramaniam, Srinivas, and Kevin Johnson. "Optimization of High Current Xenon Plasma Ion Beams for Applications in Semiconductor Failure Analysis and Development." Microscopy and Microanalysis 20, S3 (August 2014): 296–97. http://dx.doi.org/10.1017/s1431927614003201.

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Gireta, C., D. Brua, D. Faurea, C. Alia, M. Razania, and D. Gobleda. "Electrical characteristics measurement of transistors by 4 tips-0.2 micron probing technique in Semiconductor Failure Analysis." Microelectronics Reliability 42, no. 9-11 (September 2002): 1723–27. http://dx.doi.org/10.1016/s0026-2714(02)00220-2.

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Tan, Shida, Richard Livengood, Paul Hack, Roy Hallstein, Darryl Shima, John Notte, and Shawn McVey. "Nanomachining with a focused neon beam: A preliminary investigation for semiconductor circuit editing and failure analysis." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 29, no. 6 (November 2011): 06F604. http://dx.doi.org/10.1116/1.3660797.

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Blinov, Andrei, Roman Kosenko, Andrii Chub, and Volodymyr Ivakhno. "Analysis of Fault-Tolerant Operation Capabilities of an Isolated Bidirectional Current-Source DC–DC Converter." Energies 12, no. 16 (August 20, 2019): 3203. http://dx.doi.org/10.3390/en12163203.

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Reliable and predictable operation of power electronics is of increasing importance due to continuously growing penetration of such systems in industrial applications. This article focuses on the fault-tolerant operation of the bidirectional secondary-modulated current-source DC–DC converter. The study analyzes possible topology reconfigurations in case an open- or short-circuit condition occurs in one of the semiconductor devices. In addition, multi-mode operation based on topology-morphing is evaluated to extend the operating range of the case study topology. The influence of post-failure modes on the functionality and performance is analyzed with a 300 W converter prototype. It is demonstrated that failure of one transistor in the current-source side can be mitigated without dramatic loss in the efficiency at maximum power, while preserving bidirectional operation capability.

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