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Journal articles on the topic 'Semiconductor device modeling'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Vasileska, D., D. Mamaluy, H. R. Khan, K. Raleva, and S. M. Goodnick. "Semiconductor Device Modeling." Journal of Computational and Theoretical Nanoscience 5, no. 6 (June 1, 2008): 999–1030. http://dx.doi.org/10.1166/jctn.2008.2538.

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2

Schöll, Eckehard. "Modeling Nonlinear and Chaotic Dynamics in Semiconductor Device Structures." VLSI Design 6, no. 1-4 (January 1, 1998): 321–29. http://dx.doi.org/10.1155/1998/84685.

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We review the modeling and simulation of electrical transport instabilities in semiconductors with a special emphasis on recent progress in the application to semiconductor microstructures. The following models are treated in detail: (i) The dynamics of current filaments in the regime of low-temperature impurity breakdown is studied. In particular we perform 2D simulations of the nascence of a filament upon application of a bias voltage. (ii) Vertical electrical transport in layered semiconductor structures like the heterostructure hot electron diode is considered. Periodic as well as chaotic spatio-temporal spiking of the current is obtained. In particular we find long transients of spatio-temporal chaos preceding regular spiking.

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3

IÑIGUEZ, BENJAMIN, TOR A. FJELDLY, MICHAEL S. SHUR, and TROND YTTERDAL. "SPICE MODELING OF COMPOUND SEMICONDUCTOR DEVICES." International Journal of High Speed Electronics and Systems 09, no. 03 (September 1998): 725–81. http://dx.doi.org/10.1142/s0129156498000312.

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We review recent advances in the modeling of novel and advanced semiconductor devices, including state-of-the-art MESFET and HFETs, heterodimensional FETs, resonant tunneling devices, and wide-bandgap semiconductor transistors. We emphasize analytical, physics-based modeling incorporating the important effects present in modern day devices, including deep sub-micrometer devices. Such an approach is needed in order to accurately describe and predict both stationary and dynamic device behavior and to make the models suitable for implementation in advanced computer aided design tool including circuit simulators such as SPICE.

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4

Górecki, Paweł. "Compact Thermal Modeling of Power Semiconductor Devices with the Influence of Atmospheric Pressure." Energies 15, no. 10 (May 12, 2022): 3565. http://dx.doi.org/10.3390/en15103565.

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The efficiency of the heat dissipation process generated in semiconductor devices depends on many factors, related both to the parameters of the cooling system and environmental factors. Regarding the latter factors, ambient temperature and volume in which the device operates are typically indicated as the most important. However, in the case of the operation of semiconductor devices in non-standard conditions, e.g., in stratospheric airships, the thermal parameters of the device are significantly affected by a low value of atmospheric pressure. This paper presents a compact thermal model of a semiconductor device, considering the effects of reduced atmospheric pressure along with its experimental verification under various cooling conditions, thus obtaining high compliance for computation and measurement results. The formulated model is dedicated to circuit-level simulations, and it enables computations of the junction temperature of the semiconductor device in a short time. It is also shown that lowering atmospheric pressure can double the value of the junction-ambient thermal resistance.

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5

Mantooth, H. A., S. Ahmed, and S. S. Ang. "Power Semiconductor Device Modeling and Simulation." ECS Transactions 58, no. 4 (August 31, 2013): 391–98. http://dx.doi.org/10.1149/05804.0391ecst.

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6

Geistlinger, Helmut. "Device modeling of semiconductor gas sensors." Sensors and Actuators B: Chemical 14, no. 1-3 (June 1993): 685–86. http://dx.doi.org/10.1016/0925-4005(93)85144-y.

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7

Hurst, S. L. "Introduction to semiconductor device yield modeling." Microelectronics Journal 24, no. 5 (August 1993): 589. http://dx.doi.org/10.1016/0026-2692(93)90136-3.

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8

Dimitrijev, S., and N. Stojadinović. "Introduction to semiconductor device yield modeling." Microelectronics Journal 25, no. 3 (May 1994): 249. http://dx.doi.org/10.1016/0026-2692(94)90016-7.

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9

Prijić, Z. D., and S. Z. Mijalković. "Advanced semiconductor device physics and modeling." Microelectronics Journal 25, no. 8 (November 1994): 768. http://dx.doi.org/10.1016/0026-2692(94)90142-2.

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10

Dimitrijev, S., and N. Stojadinović. "Introduction to semiconductor device yield modeling." Microelectronics Reliability 34, no. 10 (October 1994): 1696. http://dx.doi.org/10.1016/0026-2714(94)90056-6.

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11

Wang, Ke, George W. Pan, R. Techentin, and B. Gilbert. "Semiconductor nonlinear device modeling using multiwavelets." Microwave and Optical Technology Letters 37, no. 6 (April 30, 2003): 436–40. http://dx.doi.org/10.1002/mop.10942.

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12

Sano, N., A. Hiroki, and K. Matsuzawa. "Device modeling and simulations toward sub-10 nm semiconductor devices." IEEE Transactions on Nanotechnology 1, no. 1 (March 2002): 63–71. http://dx.doi.org/10.1109/tnano.2002.1005427.

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13

Abe, Katsumi, Kazuki Ota, and Takeshi Kuwagaki. "Device modeling of amorphous oxide semiconductor TFTs." Japanese Journal of Applied Physics 58, no. 9 (June 6, 2019): 090505. http://dx.doi.org/10.7567/1347-4065/ab21a5.

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14

FJELDLY, TOR A., and MICHAEL S. SHUR. "SIMULATION AND MODELING OF COMPOUND SEMICONDUCTOR DEVICES." International Journal of High Speed Electronics and Systems 06, no. 01 (March 1995): 237–84. http://dx.doi.org/10.1142/s0129156495000079.

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We review the simulation and modeling techniques used for popular compound semiconductor devices such as the Heterostructure Field Effect Transistor (HFET), the Metal Semiconductor Field Effect Transistor (MESFET), and the Heterostructure Bipolar Transistor (HBT). Starting with the basic transport theory and the numerical simulation techniques based on this theory, we proceed to give examples of Monte Carlo simulations and of 2D balance equation simulations for investigating fundamental device properties and for exploring new design concepts. Next, we present analytical HFET and MESFET models suitable for circuit simulations. These models are based on the so-called universal FET modeling concept, and accurately reproduce FET I-V and C-V characteristics. Finally, we review basic simulation and modeling issues for HBTs.

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15

Shen, Min, Ming-C. Cheng, and J. J. Liou. "A Generalized Finite Element Method for Hydrodynamic Modeling of Short-channel Devices." VLSI Design 13, no. 1-4 (January 1, 2001): 79–84. http://dx.doi.org/10.1155/2001/36165.

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A finite element method based on the least-squares scheme is developed for hydrodynamic simulation of two-dimensional short-channel semiconductor devices. Although this general-purpose finite element method has been shown in fluid dynamics to be more universal to flow problems than other finite element approaches and has been applied in recent years to a wide range of problems in fluid dynamics, it is still unfamiliar to the semiconductor device community. Application of the developed hydrodynamic least squares finite element method (LSFEM) to simulation of a 2D MESFET with a deep-submicron gate has demonstrated its robustness and effectiveness for the hydrodynamic device simulation.

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16

De, S. S., and A. K. Ghosh. "A new scaling length for semiconductor-device modeling." Canadian Journal of Physics 69, no. 2 (February 1, 1991): 142–45. http://dx.doi.org/10.1139/p91-021.

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Through the use of an approximate solution of Poisson's equation, a new scaling length has been introduced that is appropriate to semiconductor-device modeling of surface problems or step-junction problems in regions where the fixed charges are dominant.

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17

Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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18

Malahanov, Aleksey, and Dmitriy Medvedev. "MODELING POWER CHARACTERISTICS OF SCHOTTKY DIODE UNDER EXTREME OPERATION MODES." Automation and modeling in design and management 2022, no. 2 (June 22, 2022): 92–100. http://dx.doi.org/10.30987/2658-6436-2022-2-92-100.

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The results of device-technological modelling of static current-voltage characteristics (CVC), as well as the dependences of differential resistance and power dissipation for the structure of a silicon carbide Schottky diode in Synopsys Sentaurus TCAD are presented. As a result of the research and modelling, the design and technological parameters of the Schottky diode are selected, on the basis of which the current-voltage characteristics are obtained, comparable with the specified accuracy with the physical experiment (the anode current is not less than 100 A, the breakdown voltage is not less than 1400 V at a temperature of 77 K). Verifying the static characteristics of the Schottky diode obtained by the instrumental-technological modelling is carried out by comparing the results of a computational experiment with a physical study of the Cree C4D20120D diode for a temperature range from 300 K to 77 K. The novelty of the work lies in developing an instrument-technological model (ITM) of a semiconductor device that takes into consideration a crystal self-heating effect; obtaining results reflecting the characteristics of a semiconductor device in the normal and extreme temperature operating conditions; in obtaining dependences reflecting the change in differential resistance and power dissipation; in having the possibility to use the results of the developed ITM for the industrial implementation of the silicon carbide Schottky diode at Russian enterprises in the form of discrete semiconductor devices, or elements as part of semiconductor power modules.

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19

Gardner, Carl L. "VLSI Design Special Issue on Semiconductor Device Modeling." VLSI Design 15, no. 4 (January 1, 2002): 679. http://dx.doi.org/10.1080/1065514021000012282.

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20

Gaofeng Wang, Xiaoning Qi, and Zhiping Yu. "Device level modeling of metal-insulator-semiconductor interconnects." IEEE Transactions on Electron Devices 48, no. 8 (2001): 1672–82. http://dx.doi.org/10.1109/16.936590.

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21

Jingsong Xie and M. Pecht. "Reliability prediction modeling of semiconductor light emitting device." IEEE Transactions on Device and Materials Reliability 3, no. 4 (December 2003): 218–22. http://dx.doi.org/10.1109/tdmr.2003.820294.

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22

Zhang, Lei, and Qi-Jun Zhang. "Neuro-space mapping technique for semiconductor device modeling." Optimization and Engineering 9, no. 4 (November 10, 2007): 393–405. http://dx.doi.org/10.1007/s11081-007-9024-0.

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23

CAREY, G. F., and M. SHARMA. "SEMICONDUCTOR DEVICE MODELING USING FLUX UPWIND FINITE ELEMENTS." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 8, no. 4 (April 1989): 219–34. http://dx.doi.org/10.1108/eb010063.

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24

Liu, Teng, Tianlong Wen, Wentong Zhang, Nailong He, Sen Zhang, and Hua Song. "Design of LDMOS Device Modeling Method Based on Neural Network." Computational Intelligence and Neuroscience 2022 (August 10, 2022): 1–10. http://dx.doi.org/10.1155/2022/4988636.

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The rapid development of power semiconductor devices is helping to realize a low-carbon society and provide a better life for everyone. Power semiconductors not only are used in many large-scale industrial control fields such as power transmission and control in power grids, rail transit traction systems, and defense weapons and equipment, but also play a vital role in daily equipment such as home appliances, medical electronics, and electronic communications; all devices such as power steering in cars, battery chargers, cell phones, and microwave ovens utilize power electronics. This research mainly focuses on the high-voltage LDMOS device model and its implementation. Based on the in-depth study of the structure and physical mechanism of high-voltage LDMOS devices, with the help of BSIM4 core model, which is now very mature and widely used in industry, the drift region of high-voltage LDMOS is mainly modeled, and the drift region of LDMOS is modeled as a variable resistance controlled by voltage. Finally, Verilog-A language and neural network method are used to establish a compact model of LDMOS. The improved model is applied to LDMOS and can better fit the output characteristics with self-heating effect.

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25

Cai, J., H. L. Cui, E. H. Lenzing, R. Pastore, D. L. Rhodes, and B. S. Perlman. "Hydrodynamic Device Modeling with Band Nonparabolicity." VLSI Design 6, no. 1-4 (January 1, 1998): 181–83. http://dx.doi.org/10.1155/1998/28708.

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A semiconductor device model based on a set of quantum mechanically derived hydrodynamic balance equations are presented. This model takes full account of band nonparabolicity, in addition to its other useful features such as the explicit evaluation of momentum and energy relaxation rates, in the form of frictional force and energy loss rate, within the model, and inclusion of carrier-carrier interaction effects, such as dynamical screening. Numerical results of one-dimensional device simulations are presented and compared with parabolic approximations.

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26

Kerr, Daniel C., Neil Goldsman, and Isaak D. Mayergoyz. "Three-Dimensional Hydrodynamic Modeling of MOSFET Devices." VLSI Design 6, no. 1-4 (January 1, 1998): 261–65. http://dx.doi.org/10.1155/1998/60859.

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The hydrodynamic (HD) model of semiconductor devices is solved numerically in three-dimensions (3-D) for the MOSFET device. The numerical instabilities of the HD model are analyzed to develop a stable discretization. The formulation is stabilized by using a new, higher-order discretization for the relaxation-time approximation (RTA) term of the energy-balance (EB) equation. The developed formulation is used to model the MOSFET.

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27

Obregon, Ovier, David Barba, and Miguel A. Dominguez. "Modeling of the Density of States in Field-Effect Zinc Oxide Semiconductor Devices Fabricated by Ultrasonic Spray Pyrolysis on Plastic Substrates." Engineering Proceedings 4, no. 1 (April 14, 2021): 12. http://dx.doi.org/10.3390/micromachines2021-09552.

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In this work, using a physically based simulator, the modeling of the density of states (DOS) through the fitting of the electrical characteristics in field-effect devices is presented. The transfer characteristic of zinc oxide (ZnO) thin-film transistors is simulated, along with the capacitance–voltage curves in metal-insulator-semiconductor capacitors using ZnO as an active layer. The ZnO semiconductor devices were fabricated by high-frequency ultrasonic spray pyrolysis on polyethylene terephthalate plastic substrates. Different aspects were considered and discussed to model the device interfaces.

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28

Mishra, Brijendra, Vivek Singh Kushwah, and Rishi Sharma. "MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR." International Journal of Engineering Technologies and Management Research 5, no. 2 (May 4, 2020): 294–300. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.659.

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In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metaloxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better device will be formed with the help of new technology, with high operating speed low and power consumption, which can be the future of electronics industry. A methodology for the electric simulation of MOS/SET hybrid circuits will be developed. As a result of this, a functional model for the single-electron transistor will obtain and Implement Switched Capacitor Filter with the help of designed hybrid MOS. The SET model can be easily coded in any hardware description language.

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29

Liu, Wenyuan, Lin Zhu, Feng Feng, Wei Zhang, Qi-Jun Zhang, Qian Lin, and Gaohua Liu. "A Time Delay Neural Network Based Technique for Nonlinear Microwave Device Modeling." Micromachines 11, no. 9 (August 31, 2020): 831. http://dx.doi.org/10.3390/mi11090831.

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This paper presents a nonlinear microwave device modeling technique that is based on time delay neural network (TDNN). The proposed technique can accurately model the nonlinear microwave devices when compared to static neural network modeling method. A new formulation is developed to allow for the proposed TDNN model to be trained with DC, small-signal, and large signal data, which can enhance the generalization of the device model. An algorithm is formulated to train the proposed TDNN model efficiently. This proposed technique is verified by GaAs metal-semiconductor-field-effect transistor (MESFET), and GaAs high-electron mobility transistor (HEMT) examples. These two examples demonstrate that the proposed TDNN is an efficient and valid approach for modeling various types of nonlinear microwave devices.

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30

Tseng, A. A. "Thermal Analysis of a New IMPATT Semiconductor Device." Journal of Electronic Packaging 111, no. 2 (June 1, 1989): 135–42. http://dx.doi.org/10.1115/1.3226518.

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In many cases, functions of semiconductor devices are limited by thermal rather than electronic considerations. A microcomputer code has been developed to analyze the steady-state thermal behavior of a new multilayered IMPATT device. A two-step modeling approach which can reduce the computer memory needed for computation was employed to allow the present study to be conducted in a microcomputer. The new device was originally designed for electronic purposes. However, the present study found that the multilayer design can provide a favorable thermal environment to improve the heat dissipation rate. The present results also indicate that an increase of the operating frequency increases the thermal resistance which is consistent with most observations. Since the detailed information on temperature distributions throughout the device as well as the proposed packaging (heat sink) is available, the present study can contribute not only to better understanding of the device’s thermal characteristics but also to better design of the packaging.

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31

VOGLER, THOMAS, and DIERK SCHRÖDER. "PHYSICAL MODELING OF POWER SEMICONDUCTORS FOR THE CAE-DESIGN OF POWER ELECTRONIC CIRCUITS." Journal of Circuits, Systems and Computers 05, no. 03 (September 1995): 411–28. http://dx.doi.org/10.1142/s0218126695000254.

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CAE-tools can help to develop any traditional or novel power conversion topology more efficiently, by providing both the possibilities of investigation without the risk of destruction and of access to each signal in the circuit. However, a prerequisite are trustworthy simulation results both qualitatively for operation observation and quantitatively for power dissipation examination as well as for SOA control. This implies that precise power semiconductor models have to be used. In the variety of different possible modeling strategies there is only the strictly physical way which offers topology independent accurate results. In this paper a new class of physical high performance and high accuracy circuit models for today's relevant power semiconductors (Power-Diode, GTO, IGBT, Power-MOSFET) is presented. A modular concept, handling typical features of power devices like ν-zones, MOSFET controlling units or diffusion zones as basic structures, is used which allows a considerable flexibility to model future devices time efficiently. The core of this modular concept, constituted by a module of the ν-zone, employs a universal and powerful solution technique of the ambipolar diffusion equation. This technique is the only possibility for circuit models to consider physically semiconductor technology measures for improving device characteristics, such as particle irradiation for lifetime reduction, step doping of substrate or epitaxial layers as well as double diffused layers.

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32

Lee, Gi-Young, Min-Shin Cho, and Rae-Young Kim. "Lumped Parameter Modeling Based Power Loop Analysis Technique of Power Circuit Board with Wide Conduction Area for WBG Semiconductors." Electronics 10, no. 14 (July 18, 2021): 1722. http://dx.doi.org/10.3390/electronics10141722.

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With the development of wide-bandgap (WBG) power semiconductor technology, such as silicon carbide (SiC) and gallium nitride (GaN), the technology of power converters with high efficiency and high-power density is rapidly developing. However, due to the high rate-of-rise of voltage (dv/dt) and of current (di/dt), compared to conventional Si-based power semiconductor devices, the reliability of the device is greatly affected by the parasitic inductance component in the switching loop. In this paper, we propose a power loop analysis method based on lumped parameter modeling of a power circuit board with a wide conduction area for WBG power semiconductors. The proposed analysis technique is modeled based on lumped parameters, so that power loops with various current paths can be analyzed; thus, the analysis is intuitive, easy to apply and realizes dynamic power loop analysis. Through the proposed analysis technique, it is possible to derive the effective parasitic inductance component for the main points in the power circuit board. The effectiveness of the lumped parameter model is verified through PSpice and Ansys Q3D simulation results.

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33

Vasileska, D., W. J. Gross, V. Kafedziski, and D. K. Ferry. "Convergence Properties of the Bi-CGSTAB Method for the Solution of the 3D Poisson and 3D Electron Current Continuity Equations for Scaled Si MOSFETs." VLSI Design 8, no. 1-4 (January 1, 1998): 301–5. http://dx.doi.org/10.1155/1998/21494.

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As semiconductor technology continues to evolve, numerical modeling of semiconductor devices becomes an indispensible tool for the prediction of device characteristics. The simple drift-diffusion model is still widely used, especially in the study of subthreshold behavior in MOSFETs. The numerical solution of these two equations offers difficulties in small devices and special methods are required for the case when dealing with 3D problems that demand large CPU times. In this work we investigate the convergence properties of the Bi-CGSTAB method. We find that this method shows superior convergence properties when compared to more commonly used ILU and SIP methods.

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34

Waltl, Michael. "Reliability of Miniaturized Transistors from the Perspective of Single-Defects." Micromachines 11, no. 8 (July 29, 2020): 736. http://dx.doi.org/10.3390/mi11080736.

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To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed.

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35

Rahmouni, M. `., and S. Belarbi. "Defect Pool Numerical Model in Amorphous Semiconductor Device Modeling Program." Journal of Nano- and Electronic Physics 11, no. 2 (2019): 02008–1. http://dx.doi.org/10.21272/jnep.11(2).02008.

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36

Obrecht, M. S., E. L. Heasell, and M. I. Elmasry. "COMPARISON OF COUPLED AND DECOUPLED METHODS FOR SEMICONDUCTOR DEVICE MODELING." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, no. 4 (April 1994): 785–94. http://dx.doi.org/10.1108/eb051895.

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37

Lugli, P. "The Monte Carlo method for semiconductor device and process modeling." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 11 (1990): 1164–76. http://dx.doi.org/10.1109/43.62753.

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38

Gore, D. A., and D. A. Drew. "The one-dimensional inverse doping problem in semiconductor device modeling." Inverse Problems in Engineering 1, no. 1 (October 1994): 27–43. http://dx.doi.org/10.1080/174159794088027571.

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39

Hong, Yuxi, Dongsheng Ma, and Zuochang Ye. "Multivariate rational regression and its application in semiconductor device modeling." Journal of Semiconductors 39, no. 9 (September 2018): 094010. http://dx.doi.org/10.1088/1674-4926/39/9/094010.

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40

Mnatsakanov, Tigran T., Alexey G. Tandoev, Michael E. Levinshtein, and Sergey N. Yurkov. "Physical limitations of the diffusive approximation in semiconductor device modeling." Solid-State Electronics 56, no. 1 (February 2011): 60–67. http://dx.doi.org/10.1016/j.sse.2010.11.001.

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41

Tolstikhin, Valery I. "Optical properties of semiconductor heterostructures for active photonic device modeling." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 18, no. 2 (March 2000): 605–9. http://dx.doi.org/10.1116/1.582235.

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42

De, S. S., and A. K. Ghosh. "An approximate solution of Poisson's equation for semiconductor device modeling." Solid-State Electronics 32, no. 7 (July 1989): 517–19. http://dx.doi.org/10.1016/0038-1101(89)90106-8.

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43

GILDENBLAT, G., and D. FOTY. "LOW TEMPERATURE MODELS OF METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS." International Journal of High Speed Electronics and Systems 06, no. 02 (June 1995): 317–73. http://dx.doi.org/10.1142/s0129156495000092.

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We review the modeling of silicon MOS devices in the 10–300 K temperature range with an emphasis on the specifics of low-temperature operation. Recently developed one-dimensional models of long-channel transistors are discussed in connection with experimental determination and verification of the effective channel mobility in a wide temperature range. We also present analytical pseudo-two-dimensional models of short-channel devices which have been proposed for potential use in circuit simulators. Several one-, two-, and three-dimensional numerical models are discussed in order to gain insight into the more subtle details of the low-temperature device physics of MOS transistors and capacitors. Particular attention is paid to freezeout effects which, depending on the device design and the ambient temperature range, may or may not be important for actual device operation. The numerical models are applied to study the characteristic time scale of freezeout transients in the space-charge regions of silicon devices, to the analysis and suppression of delayed turn-off in MOS transistors with compensated channel, and to the temperature dependence of three-dimensional effects in short-channel, narrow-channel MOSFETs.

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Wu, Dong Yan, Zhi Liang Tan, Li Yun Ma, and Peng Hao Xie. "The Failure Modeling Analysis of Bipolar Silicon Transister Device Caused by ESD." Applied Mechanics and Materials 427-429 (September 2013): 929–32. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.929.

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With the development of electronic technology, the electronic threats faced by microwave semiconductor devices was increasingly serious.In order to study the electrostatic discharge damage mechanism of bipolar silicon transistors, this paper analyzed the basic physical characteristics of bipolar transistor in electrostatic discharge, such as kirk effect and current crowding effect. Through analysis the human body electrostatic discharge model, established the ESD electric injury model of bipolar silicon transistor. If we knew the production process parameter of devices, we can calculate the ESD damage threshold for designing bipolar silicon device and providing a theoretical basis of parameter optimization. Finally the common ESD damage criterion were analyzed from different angles.

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Li, Kai, Zhi You Guo, Mei Jiao Li, and Ming Jun Zhu. "Modeling of Vertical GaN Based Resonant Cavity Light-Emitting Diode." Applied Mechanics and Materials 389 (August 2013): 409–14. http://dx.doi.org/10.4028/www.scientific.net/amm.389.409.

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Vertical structure of resonant cavity light-emitting diode (RCLED) is presented in this paper to further improve the photoelectric performance of the device. Modeling and 2D simulation have been proceeded with Crosslight APSYS[, the analysis and modeling software for semiconductor devices. Main results of the simulation are listed and discussed. The peak wavelength locates at about 550 nm with half-wave width of about 10 nm and its output power has been enhanced by 25% than the conventional one. The results prove that vertical RCLED is a considerable source for POF-based fiber communication.

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Haussener, Sophia. "(Invited) Multi-Scale and Multi-Physics Modeling for Advancing Photoelectrochemical and Photocatalytic Material and Device Research." ECS Meeting Abstracts MA2018-01, no. 31 (April 13, 2018): 1856. http://dx.doi.org/10.1149/ma2018-01/31/1856.

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Modelling can efficiently support the choice of the most interesting conceptual design approaches, material choices, and operating conditions for photoelectrochemical and photocatalytic devices. Here, I will discuss modeling of three different ideas for versatile and cheap solar hydrogen and syngas production: i) photocatalytic particle suspended in a solution, ii) semiconductor particle-based photoelectrodes (PEs) fabricated by scalable dipping procedures, and iii) high-temperature approaches to photoelectrochemistry. Modeling of scalable photocatalysis suspensions require understanding of the single particle band energetics and kinetics and coupling it to the heat, mass and charge transport processes in a complete suspension. I will show how we use and couple 1D single particle models and 2D suspension simulations to provide material and design guidance of photocatalytic suspension approaches. Modeling of complicated particle-based PEs, on the other hand, requires full 3D multi-scale device models accounting for the morphological details of the nano-scale and then coupling them through homogenization theory to the macroscopic device model. I will show how we utilized nano-tomography to obtain the exact nano-scale morphology and how this morphology is incorporated into direct pore-level modeling to predict inhomogeneity in the variable fields and corresponding underutilization of parts of the PE. Finally, I will show how we use advanced 2D heat transfer models and detailed 1D junction models for mixed electron and ion conductor interfaces to model and explore high temperature approaches to photoelectrochemistry. I will end with a general outlook on modeling of photo-driven devices.

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Wang, Xiao, and Ananth Dodabalapur. "Modeling of thin-film transistor device characteristics based on fundamental charge transport physics." Journal of Applied Physics 132, no. 4 (July 28, 2022): 044501. http://dx.doi.org/10.1063/5.0083876.

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A model is described that enables the calculation of thin-film transistor (TFT) characteristics starting from fundamental considerations of charge transport. Starting from scattering mechanisms and trap distribution in a semiconductor, electric field and charge density distributions are calculated along the channel length direction. Output and transfer characteristics of a TFT can be calculated at any temperature. The model is quasi-two-dimensional and is based on multiple trap and release transport in the semiconductor active layer. Importantly, the charge transport models that constitute the basis of this paper are very sophisticated and operate at a level of depth and detail that go beyond most other studies on thin-film transistors. Contact resistance effects, often very important in TFTs, are included in the model. Simulation results are presented for several representative TFT dimensions and parameter sets. The model is designed for convenient use by the research community, and the source code as well as instructions are publicly available. The modular nature of the models allows for ease in changing the semiconductor parameters, transport mechanisms, contact barriers, etc.

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Gil-Tomàs, Gracia-Morán, Saiz-Adalid, and Gil-Vicente. "Fault Modeling of Graphene Nanoribbon FET Logic Circuits." Electronics 8, no. 8 (July 31, 2019): 851. http://dx.doi.org/10.3390/electronics8080851.

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Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

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Landheer, D., Z. M. Li, S. P. McAlister, and D. A. Aruliah. "Modeling of ultrafast metal–semiconductor–metal photodetectors." Canadian Journal of Physics 69, no. 3-4 (March 1, 1991): 520–26. http://dx.doi.org/10.1139/p91-085.

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We have simulated the transient response of metal–semiconductor–metal (MSM) photodetectors to an optical impulse, using a two-dimensional (2-D) drift-diffusion model that incorporates deep traps and appropriate boundary conditions. We incorporate the external circuit using a method originally developed to describe photoconductors in transmission lines. Initially a one-dimensional (1-D) simulation is used to verify our model comparing our results to previous 1-D calculations and experimental results for GaAs MSM detectors. Then a full 2-D analysis is used to predict the performance of a novel MSM wave-guide photodetector whose structure incorporates a Si–Si0.5Ge0.5 strained-layer superlattice. We show that this device can have a response as fast as 50 ps, although pulse pile-up due to slow diffusion of carriers may be a problem at high duty cycles.

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Subash, T. D., T. Gnanasekaran, and P. Deepthi Nair. "Analytical modeling of AlInSb/InSb MOS gate HEMT structure with improved performance." International Journal of Modeling, Simulation, and Scientific Computing 07, no. 03 (August 23, 2016): 1672001. http://dx.doi.org/10.1142/s1793962316720016.

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The performance of AlInSb/InSb heterostructure with various parameters is considered with T-Cad simulation. As the heterojunctions are having more advantageous properties that is a real support for so many application such as solar cells, semiconductor cells and transistors. Special properties of semiconductors are discussed here with various parameters that are depending up on the performance of accurate device [Pardeshi H., Pati S. K., Raj G., Mohankumar N., Sarkar C. K., J. Semicond. 33(12):124001-1–124001-7, 2012]. The maximum drain current density is achieved with improving the density of two-dimensional electron gas (2DEG) and with high velocity. High electron mobility transistor (HEMT) structure is used with the different combinations of layers which have different bandgaps. Parameters such as electron mobility, bandgap, dielectric constant, etc., are considered differently for each layer [Zhang A., Zhang L., Tang Z., IEEE Trans. Electron Devices 61(3):755–761, 2014]. The high electron mobility electrons are now widely used in so many applications. The proposed work of AlInSb/InSb heterostructure implements the same process which will be a promise for future research works.

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