Dissertations / Theses on the topic 'Scan testing'
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Hassan, Abu S. M. (Abu Saleem Mahmudul). "Testing of board interconnects using boundary scan architecture." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74304.
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The testing of printed circuit board (PCB) interconnects is a complex task that requires enormous amount of resources. With the increasing use of new technologies like surface mounting technology (SMT), testing PCB interconnects using the available techniques, like in-circuit testing and functional testing, is becoming very difficult. To make testing manageable, it must be considered earlier in the design process. This is known as 'design for testability' (DFT). A hierarchical DFT approach known as boundary scan architecture has recently become an increasingly attractive solution for PCB interconnect testing problems. This framework provides a scan path for electronic access to the interconnect test points, thus removing the need for accessibility through electro-mechanical contacts known as 'bed of nails'.In the recent past, several researchers have proposed different schemes for PCB interconnect testing based on the boundary scan architecture.
In this dissertation, a new approach, based on the concept of built-in self-test (BIST), is developed using the boundary scan architecture for PCB interconnect testing. BIST, at the component level, generally consists of incorporating additional circuitry on the chip to generate test patterns and to compact the response of the circuit under test into a reference signature. For the PCB level BIST, the board is considered as the unit under test. A family of BIST schemes are developed for board interconnect testing utilizing the properties of the boundary scan architecture. The BIST approach has removed the dependence on automatic test equipment (ATE) for generation of test vector sets and analysis of output data sets. Techniques are developed for the generation of test vector sets which require very simple test generation hardware. Test vector sets are shown to be independent of the order of the input/output (I/O) scan cells in the boundary scan chain and of the structural complexity of the interconnects under test. Response compaction techniques proposed in the schemes are such that fault detection and diagnosis can be done independent of the topological information about the interconnects. These response compaction techniques can be implemented within each boundary scan cell or outside the boundary scan chain, providing a trade-off in terms of test time and hardware complexity. The various uses of the boundary scan architecture make the proposed schemes more attractive and advantageous than the existing approaches for board interconnect testing.
Moreover, a family of interconnect testing schemes is proposed for a partial boundary scan environment. Partial boundary scan environment refers to a board with a mix of boundary scan and non-boundary scan components. Such an environment is more complex compared to a complete boundary scan environment. The proposed schemes are BIST-able despite the inherently complex test environment. However, fault coverage is limited because of the reduced accessibility of the partial boundary scan environment.
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McBean, David P. O. "Board interconnect testing in a boundary scan environment." Thesis, University of Oxford, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333253.
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Panda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.
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Jayaram, Vinay B. "Experimental Study of Scan Based Transition Fault Testing Techniques." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31146.
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The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed load delay test (Launch-from-shift). Each method has its own drawbacks and many practical issues are associated with pattern generation and application. Our work focuses on the implementation and comparison of these transition fault testing techniques on multiple industrial ASIC designs. In this thesis, we present results from multiple designs and compare the two techniques with respect to test coverage, pattern volume and pattern generation time. For both methods, we discuss the effects of multiple clock domains, tester hardware considerations, false and multi-cycle paths and the implications of using a low cost tester. We then consider the implications of pattern volume on testing both stuck-at and transition faults and the effects of using transition fault patterns to test stuck-at faults. Finally, we present results from our analysis on switching activity of nets in the design, while executing transition fault patterns.Master of Science
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Xu, Gefu Singh Adit D. "Delay Test Scan Flip-Flop c(DTSFF) design and its applications for scan based delay testing." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Fall%20Dissertations/Xu_Gefu_18.pdf.
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Mahmoud, Ahmed Gamal Mohamed. "Boundary-scan for High-speed Serial Links." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018.
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The complexity of integrated circuit (IC) designs continues to increase with the constant advancement of process technology and decrease of feature size in a relentless effort to achieve better performance and reach new milestones. However, with the increasing density and complexity comes a higher probability of defects occurring as well as a higher impact of these defects on the overall performance. Testing, thus, proves essential in order to guarantee defect-free designs. Effective and efficient testing in terms of both cost and time becomes essential as well because of the continually rising cost of testing.
Abstract Serializer-deserializer (SerDes) devices or serial-link transceivers, which represent the device-under-test (DUT) in this thesis, are no different. Since the interface is the bottleneck in the performance of various systems, efforts continue to push for faster, smaller, and more power-efficient SerDes, leaving it with stringent specifications to meet. This leads to it being susceptible to the higher defect probability we just mentioned. As these are wireline transceivers, the robustness of the interconnects is especially critical. These defects that affect the interconnects are troublesome due to the fact that it is relatively easy for the fault to be masked which would indicate a non-existent fault within the design itself. In this thesis, we propose a test receiver that is capable of putting the interconnects under test in both DC-coupled and AC-coupled scenarios in compliance with the IEEE-1149.1 and IEEE-1149.6 standards.
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Krug, Margrit Reni. "Aumento da testabilidade do hardware com auxilio de técnicas de teste de software." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12672.
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O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técnicas, ferramentas e métodos empregados, não estão livres de erros que podem levar ao mau funcionamento do produto final. Estes erros podem ocorrer durante a especificação do projeto, como também em estágios finais do desenvolvimento ou no processo de manufatura. A fim de minimizar prejuízos é necessário garantir a qualidade do sistema a partir da verificação do projeto, da validação de protótipo e do teste de fabricação. Por muito tempo o teste de hardware e o teste de software foram estudados como disciplinas completamente independentes. Porém, similaridades entre o desenvolvimento de software e o projeto de hardware já foram exploradas com sucesso em adaptações de técnicas originalmente desenvolvidas para um sendo utilizadas por outro. Um exemplo é a cobertura de código, que foi inicialmente desenvolvida para o teste de software, e agora é comumente utilizada na verificação de hardware. Visto que dispositivos são descritos em linguagem de descrição de hardware, e estas possuem características semelhantes às linguagens de programação, parece uma boa alternativa valer-se desta semelhança para utilizar os métodos propostos pela engenharia de software para garantir a qualidade do hardware desenvolvido. Utilizar tais métodos para gerar padrões de teste para dispositivos de hardware descritos em HDL (Hardware Description Language) e identificar nestas descrições características que, alteradas, aumentem a testabilidade dos mesmos, são os principais objetivos desta tese.Both software and hardware designs require several tasks to increase reliability and ensure high quality of the final system. Although different techniques, tools and methods can be applied, error free products are difficult to be achieved. Errors may occur on design specification, on development stages and also during manufacturing process. To increase system quality and minimize costs it is mandatory to perform design verification, prototype validation and manufacturing test. For a long time hardware and software tests were studied as disciplines completely apart. However, similarities between software development and hardware design have already been explored successfully by adapting techniques originally developed for one of them, and applying to the other. For instance, code coverage concept and methods were firstly developed for software testing, but nowadays are commonly used in hardware verification. Due to the high similarity observed between software programming languages and hardware description languages (HDL), it seems to be a valuable approach applying software engineering techniques to help ensuring a high quality hardware device. Therefore, the main purpose of this thesis is to use such techniques to extract test patterns from HDL descriptions of hardware devices and to identify at these descriptions means to increase hardware testability.
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Greher, Michael R. "Measuring attention: An evaluation of the Search and Cancellation of Ascending Numbers (SCAN) and the short form of the Test of Attentional and Interpersonal Style (TAIS)." Thesis, University of North Texas, 2000. https://digital.library.unt.edu/ark:/67531/metadc2529/.
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This study found a relationship between the Search and Cancellation of Ascending Numbers (SCAN), Digit Span, and Visual Search and Attention Test (VSAT). Data suggest the measures represent a common construct interpreted to be attention. An auditory distracter condition of the SCAN did not distract participants, while the measure exhibited ample alternate forms reliability. The study also found that the Test of Attentional and Interpersonal Style (TAIS) short form poorly predicted performance on the Digit Span, VSAT, and SCAN. Although the TAIS exhibited good internal consistency, the items likely measure the subjective perception of attention. Furthermore, discriminant and convergent validity of the TAIS were found to be poor.
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Poulos, Konstantinos. "NEW TECHNIQUES ON VLSI CIRCUIT TESTING & EFFICIENT IMPLEMENTATIONS OF ARITHMETIC OPERATIONS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1872.
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Testing is necessary factor to guarantee that ICs operate according to specifications before being delivered to customers. Testing is a process used to identify ICs containing imperfections or manufacturing defects that may cause failures. Inaccuracy and imperfections can be introduced during the fabrication of the chips due to the complex mechanical and chemical steps required during the manufacturing processes. The testing process step applies test patterns to circuits and analyzes their responses. This work focuses on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification.There has been a massive increase in the number of transistors integrated in a chip, and the complexity of the circuit is increasing along with it. This growth has become a bottleneck for the test developers. The proposed ATPG tool was designed for testing sequential circuits. Scan Chains in Design For Testability (DFT) gained more prominence due to the increase in the complexity of the modern circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods are needed. Even though scan chains implementation effectively increases observability and controllability, a big portion of the time is wasted while shifting in and shifting out the test patterns through the scan chain. Additionally, the modern applications require operating speed at higher frequencies and there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications.With the modern applications requiring operating speed at higher frequencies, there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications. Two main problems have been associated when using external test equipment to test high frequency circuits; the effect of the resistance and capacitance of the probe on the performance of the circuit under test which leads to a faulty evaluation; and the cost of a dedicated high frequency tester. To solve these problems innovative test techniques are needed such as Built In Test (BIT) where self-evaluation takes place with a small area overhead and reduced requirements for external equipment. In the proposed methodology a Built In Test (BIT) detection circuit provides an efficient way to transform the high frequency response of the circuit under test into a DC signal.This work is focused in two major fields. The first topic is on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification as explained. The second topic is focused on efficient implementations of arithmetic operations in arbitrary long numbers with emphasis to addition. Arbitrary-Precision arithmetic refers to a set of data structures and algorithms which allows to process much greater numbers that exceed the standard data types. . An application example where arbitrary long numbers are widely used is cryptography, because longer numbers offer higher encryption security. Modern systems typically employ up to 64-bit registers, way less than what an arbitrary number requires, while conventional algorithms do not exploit hardware characteristics as well. Mathematical models such as weather prediction and experimental mathematics require high precision calculations that exceed the precision found in most Arithmetic Logic Units (ALU). In this work, we propose a new scalable algorithm to add arbitrary long numbers. The algorithm performs bitwise logic operations rather than arithmetic on 64-bit registers. We propose two approaches of the same algorithm that utilize the same basic function created according to the rules of binary addition
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GHOSH, SWAROOP. "SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670.
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Jamialahmadi, Arsalan. "Experimental and numerical analysis of the dynamic load distribution in a corrugated packaging system." Thesis, KTH, Solid Mechanics (Div.), 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-11385.
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It is well known that transportation means high and varying loads for products as well as packages. To develop corrugated boxes with optimal design and efficient use of raw materials is crucial. Vibrations and shocks acting on pallets during transportation are transferred to the corrugated boxes and considerably reduce the integrity and life time of the boxes. The development of experimental and analytical tools for measurement and prediction of the influence of dynamic loads on the box performance, such as stacking strength and conservation of stacking pattern would therefore be of large practical importance. In order to develop such tools, it is important to know the load distribution between different boxes. This master thesis presents a technique for investigating these stresses based on a pressure sensitive film, which gives many data points. A series of tests using random and sinusoidal vibration testing have been done utilising this technique and results are presented for different positions on the pallet and for different box filling methods. Investigations performed on the vibrations of the boxes also demonstrate a pitch type of motion. A level-crossing study on the forces existing between the boxes shows a Rayleigh force distribution. A mathematical model is also proposed for simulation of a stacking system. Advantages and disadvantages with this technique and with the model are described. Comparison between the experimental and numerical results shows a proper correlation. Using the pressure sensitive film as a quantitative sensor and applying the recorded data for the statistical study of the contact forces existing in a stack of boxes gives useful and important results for further analysis of the fatigue life and vulnerable positions of boxes.
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Telrandhe, Mangesh. "Fabrication And Testing Of A Cylindrical Ion Trap Microarray For Tunable Mass Spectrometers." Scholar Commons, 2004. https://scholarcommons.usf.edu/etd/1267.
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This research presents a novel microfabrication approach and testing methodology for cylindrical ion trap (CIT) microarray tunable for mass- spectrometers. The growing interest in cylindrical ion trap (CIT) mass-spectrometers is primarily due to ease with which cylindrical geometry can be realized as compared to hyperbolic surfaces found in conventional quadrupole ion traps. Also due to the fact that the potential at the center of hyperbolic electrode in quadrupole ion trap and cylindrical electrode in cylindrical ion trap (CIT) does not differ significantly[2].
Since the RF voltage required to eject a given mass-to-charge ion scales as the square of the ion trap radius, a decrease in ion trap dimensions provides a significant reduction in electronics requirements, thereby providing a pathway for overall system miniaturization. The reduction in sensitivity due to reduced ion storage capacity as a result of miniaturization can be improved by employing an array of identically sized ion traps. Microfabrication approach promises excellent uniformity in the fabrication of identically sized holes which in turn leads to low-cost high performance CIT microarray for mass spectrometers[1,2].
The criterion used for the determination of trap diameter was to ensure that the hole to be 1.09 times the wafer thickness to provide optimal potential to trap ions[1]. The end- plates were designed to optimize the electron and ion transmission into and out of the ion trap and provide a high quality electric field definition within each cylindrical ion trap (CIT)[3]. Two different approaches, namely deep reactive ion etching (DRIE) and mechanical drilling using ultrasonic disc cutter were proposed and used for the fabrication of ring-electrode which forms the main body of the ion trap. Excellent uniformity in hole diameter was observed in both the approaches. The end-plates were fabricated using deep reactive ion etching (DRIE) which provided high transmission rigid grid structure for ions and electrons. Standard Bosch process was used for deep reactive ion etching (DRIE). The two electrodes were metallized using electroless plating which provides excellent uniformity of coating even on end-plate structures with 5micro m through holes. CYTOP[trademark], a cyclized perfluoro polymer, was used as an insulation layer and intermediate bonding layer between the ring electrode and end-plates. The breakdown voltage for a released 16 micro m thick CYTOP[trademark] layer was found to be 1.47KV. An assembly for testing miniature cylindrical ion trap (CIT) was designed and built. An electron impact ionization source was used for generation of ions. Mass selective instability scan was used to selectively eject ions with different mass-to-charge ratio. A cylindrical ion trap (CIT) with 4mm diameter was fabricated and tested for analyte gases such as krypton and xenon.
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Ahlström, Daniel. "Minimizing memory requirements for deterministic test data in embedded testing." Thesis, Linköping University, Linköping University, Department of Computer and Information Science, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54655.
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Embedded and automated tests reduce maintenance costs for embedded systems installed in remote locations. Testing multiple components of an embedded system, connected on a scan chain, using deterministic test patterns stored in a system provide high fault coverage but require large system memory. This thesis presents an approach to reduce test data memory requirements by the use of a test controller program, utilizing the observation of that there are multiple components of the same type in a system. The program use deterministic test patterns specific to every component type, which is stored in system memory, to create fully defined test patterns when needed. By storing deterministic test patterns specific to every component type, the program can use the test patterns for multiple tests and several times within the same test. The program also has the ability to test parts of a system without affecting the normal functional operation of the rest of the components in the system and without an increase of test data memory requirements. Two experiments were conducted to determine how much test data memory requirements are reduced using the approach presented in this thesis. The results for the experiments show up to 26.4% reduction of test data memory requirements for ITC´02 SOC test benchmarks and in average 60% reduction of test data memory requirements for designs generated to gain statistical data.
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Liu, Zhi-Hong. "Mixed-signal testing of integrated analog circuits and modules." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181174339.
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Tománek, Jakub. "Testovací rozhraní integrovaných obvodů s malým počtem vývodů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-320175.
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This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
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Cavanagh, Daniele. "Developing soft tissue thickness values for South African black females and testing its accuracy." Diss., University of Pretoria, 2010. http://hdl.handle.net/2263/25716.
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In forensic science one frequently has to deal with unidentified skeletonised remains. When conventional methods of identification have proven unsuccessful, forensic facial reconstruction (FFR) may be used, often as a last resort, to assist the process. FFR relies on the relationships between the facial features, subcutaneous soft tissues and underlying bony structure of the skull. The aim of this study was to develop soft tissue thickness (STT) values for South African black females for application to FFR, to compare these values to existing literature or databases, and to test the accuracy and recognisability of reconstructions using these values. It also established whether population-specific STT values are necessary for FRR. Computerised tomography scanning was used to determine average populationspecific STT values at 28 facial landmarks of 154 black females. The Manchester method of facial reconstruction was employed to build faces, for which antemortem photographs were available, on two skulls that were provided by the South African Police Service’s (SAPS) Forensic Science Laboratory. Different data sets of STT values, namely values from this study, two sets of data from American blacks and a South African mixed ancestry group, were used to build four faces for each of the skulls. Two identification sessions were then held. In the first session, 30 observers were asked to select matches from a random group of 20 photographs of black females which included the two actual images. The identification rates calculated for each photograph revealed that the highest rates of a positive match were for the reconstructions based on South African values. In the second session another group of 30 volunteers were asked to match to each photograph the most similar of the four reconstructions made of that particular individual. The reconstructions with STT values from the current (South African) study were selected more often than the other data sets. Although shortcomings do exist, the identification sessions indicated that FFR can be of value. Furthermore, population-specific STT values are important, since skulls reconstructed using these values were selected or identified statistically significantly more often than the others. AFRIKAANS : In forensiese wetenskap het mens dikwels te doen met ongeïdentifiseerde skeletmateriaal. Wanneer die konvensionele metodes van identifikasie onsuksesvol is, mag forensiese gesigsrekonstruksie (FGR) gebruik word, dikwels as `n laaste uitweg, om die proses te help. FGR is afhanklik van die verhouding tussen die gelaatstrekke, subkutane sagte weefsels en onderliggende benige struktuur van die skedel. Die doel van hierdie studie was om sagte weefsel dikte (SWD) waardes vir Suid-Afrikaanse swart vroue te ontwikkel vir gebruik met FGR, om hierdie waardes te vergelyk met bestaande literatuur of databasisse, en die akkuraatheid en herkenbaarheid van rekonstruksies waar hierdie waardes gebruik was te toets. Dit is gedoen ten einde vas te stel of bevolking-spesifieke SWD waardes nodig is vir FGR. Gerekenariseerde tomografie skandering is gebruik om die gemiddelde bevolkingspesifieke SWD waardes op 28 gesigslandmerke van 154 swart vroue te bepaal. Die Manchester metode van gesigsrekonstruksie is gebruik om twee skedels, waarvan antemortem foto’s beskikbaar was en wat voorsien is deur die Suid Afrikaanse Polisie Diens (SAPD) se Forensiese Wetenskap Laboratorium, op te bou. Verskeie data stelle vir SWD waardes, naamlik waardes verkry in hierdie studie, twee stelle Amerikaanse waardes vir swart vroue en `n Suid Afrikaanse groep van gemengde afkoms, is vir hierdie studie gebruik om vier gesigte van elk van die skedels te bou. Twee identifikasie sessies is gehou. In die eerste sessie is 30 deelnemers gevra om passende foto’s uit `n algemene versameling van 20 foto’s van swart vroue te kies. Dit het die twee ware gesigte ingesluit. Die identifikasie waardes wat bereken is vir elke foto het getoon dat die hoogste waardes vir die werklike foto’s verkry is op rekonstruksies gebasseer op Suid-Afrikaanse waardes. In die tweede sessie was `n ander groep van 30 vrywillgers gevra om die mees soortgelyke van die vier rekonstruksies by die foto van die betrokke individu te pas. Die rekonstruksies met SWD waardes van die huidige (Suid Afrikaanse) studie was meer dikwels gekies as die van ander data stelle. Hoewel verskeie tekortkominge bestaan, het die identifikasie sessies getoon dat FGR van waarde kan wees. Verder is bevolking-spesifieke SWD waardes belangrik, aangesien skedels wat opgebou is met hierdie waardes statisties beduidend meer dikwels gekies of geïdentifiseer is as die ander.Dissertation (MSc)--University of Pretoria, 2011.
Anatomy
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Zhang, Zhong Yi. "Visualisation and quantification of the defects in glass-fibre reinforced polymer composite materials using electronic speckle pattern interferometry." Thesis, Loughborough University, 1999. https://dspace.lboro.ac.uk/2134/22078.
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Non-destructive testing (NDT) of glass-fibre reinforced polyester (GRP) composite materials has been becoming increasingly important due to their wide applications in engineering components and structures. Electronic Speckle Pattern Interferometry (ESPI) has promising potential in this context because it is a non-contact, whole-field and real-time measurement system. This potential has never been fully exploited and there is only limited knowledge and understanding available in this area. This reality constrains the wide popularity and acceptance of ESPI as a novel NDT technique. Therefore it is of considerable importance to develop an understanding of the capability of ESPI with respect to damage evaluation in GRP composite materials. The research described in this thesis is concerned with an investigation into the applicability of ESPI in the NDT of GRP composite materials. Firstly, a study was carried out to determine excitation techniques in terms of practicality and effectiveness in the ESPI system. Three categories of defects were artificially introduced in GRP composite materials, namely holes, cracks and delaminations each with different geometrical features. ESPI was then employed to evaluate the three kinds of defects individually. It has been found that cracks and holes on back surfaces can be defined when the technique is used in conjunction with thermal excitation. Internal Temperature Differential (ITD) induced fringe patterns were more efficient than External Thermal Source (ETS) induced fringe patterns with regard to detecting the presence of holes and cracks. In the case of delamination, ESPI was found to be capable of detecting the damage when used in combination with mechanical excitation originating from a force transducer hammer. The geometrical features and magnitudes of delaminations were also established as being quantifiable. The validation of ESPI as an NDT technique was carried out in an attempt to establish a better understanding of its suitability and have more confidence in its applications. Four damaged specimens were Subjected to ESPI examination in conjunction with visual inspection, ultrasonic C-scan and sectioning techniques. The geometrical features and magnitudes of damage evaluated using ESPI showed a good correlation with those evaluated by conventional techniques. Poor visibility and readability is an inherent problem associated with ESP! due to an overlapping between the noise and signal frequencies. An improvement of image quality is expected in an attempt to achieve a wide acceptance of ESPI as a novel NDT technique. It has also been demonstrated that this problem can be tackled using optical phase stepping techniques in which optical phase data can be extracted from the intensity fringes. A three-frame optical phase stepping technique was employed to produce the "wrapped" and "unwrapped" phase maps which are capable of indicating internal damage with high visibility and clarity. Finally ESPI was practically employed to evaluate damage in GRP composites introduced by quasi-static and dynamic mechanical loading. It was found that ESP! was capable of monitoring the progressive damage development of specimens subjected to incremental flexural loading. The initial elastic response, damage initiation, propagation and ultimate failure of specimens were clearly characterised by the abnormal fringe pattern variations. In a similar manner, ESPI was employed to evaluate the low velocity falling weight impact induced damage. A correlation was established between the magnitude of damage and the impact event parameters as well as the residual flexural properties.
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Chakraborty, Rajat Subhra. "Hardware Security through Design Obfuscation." Cleveland, Ohio : Case Western Reserve University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481.
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Thesis (Doctor of Philosophy)--Case Western Reserve University, 2010Department of EECS - Computer Engineering Title from PDF (viewed on 2010-05-25) Includes abstract Includes bibliographical references and appendices Available online via the OhioLINK ETD Center
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Rathi, Nakul H. "Comparing the Accuracy of Intra-Oral Scanners for Implant Level Impressions Using Different Scanable Abutments." The Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1407200647.
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Jenkins, Robert Donald. "NPS-SCAT systems engineering and payload subsystem design, integration, and testing of NPS' first CubeSat /." Thesis, Monterey, California : Naval Postgraduate School, 2010. http://edocs.nps.edu/npspubs/scholarly/theses/2010/Jun/10Jun%5FJenkins.pdf.
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Thesis (M.S. in Astronautical Engineering)--Naval Postgraduate School, June 2010.Thesis Advisor(s): Newman, James H. ; Romano, Marcello. "June 2010." Description based on title screen as viewed on July 14, 2010. Author(s) subject terms: 1U, COTS, CubeSat, CubeSat Kit, Falcon 1e, Integration, I-V Curve, NPS-SCAT, Naval Postgraduate School, P-POD, Printed Circuit Board, Satellite, Space Shuttle, Solar Cell, Solar Cell Array Tester, Space Systems, Sun Sensor, Systems Engineering, Temperature Sensor, Testing, Thermal Vacuum. Includes bibliographical references (p. 153-161). Also available in print.
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Smith, Kerry D. "Environmental testing and thermal analysis of the NPS Solar Cell Array Tester (NPS-SCAT) Cubesat." Thesis, Monterey, California. Naval Postgraduate School, 2011. http://hdl.handle.net/10945/5654.
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Approved for public release; distribution is unlimited.This thesis describes the development of a working thermal model of the Naval Postgraduate School's first CubeSat called NPS-SCAT and the accomplishment of environmental testing that has been completed to date in preparation for space launch. The primary mission of NPS-SCAT is to act as a Solar Cell Array Tester (SCAT), providing data on solar cell performance of various solar cells in Low Earth Orbit (LEO). As part of the satellite development process, a detailed test plan was developed and environmental modeling and testing were completed to test SCAT's ability to survive and function in the space environment. A thermal finite element model (FEM) was developed in NX-6 I-deas to analyze and predict the component thermal response to the space environment. Environmental tests, including thermal vacuum (TVAC) and vibration testing, have been completed using profiles determined by the expected launch and on-orbit conditions. The data obtained from these tests validated the thermal model and proved that SCAT would survive the launch conditions and could successfully operate in the space environment.
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Berkowitz, Danielle Claire. "Development of a SCA7 patient-derived lymphoblast cell model for testing RNAi knock-down of the disease-causing gene." Master's thesis, University of Cape Town, 2011. http://hdl.handle.net/11427/10123.
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Includes bibliographical references (leaves 106-116).Spinocerebellar ataxia type 7 (SCA7) is an inherited neurodegenerative disease caused by the expansion of a CAG repeat within the ataxin-7 gene. The South African SCA7 population has been shown to have arisen due to a founder effect, and a single nucleotide polymorphism (SNP) within ataxin-7 has been linked to the SCA7 mutation in all South African patients genotyped to date. Recently, this SNP has been exploited in a potential allele-specific RNA interference (RNAi) based therapy, in order to knock down the expression of the mutant transcript in heterozygous patients. Although this approach has been tested in an artificial cellbased model of SCA7, focus has shifted towards testing the therapy in SCA7 patient-derived transformed lymphoblast cell lines
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Lubaszewski, Marcelo Soares. "Le test unifié de cartes appliqué à la conception de systèmes fiables." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1994. http://hdl.handle.net/10183/26862.
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Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente.On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.
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Brummitt, Marissa. "Development of CubeSat Vibration Testing Capabilities for the Naval Postgraduate School and Cal Poly San Luis Obispo." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/470.
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The Naval Postgraduate School is currently developing their first CubeSat, the Solar Cell Array Tester CubeSat, or NPS-SCAT. Launching a CubeSat, such as NPS-SCAT, requires environmental testing to ensure not only the success of the mission, but also the safety of other CubeSats housed in the same deployer. This thesis will address the development of CubeSat vibration testing methodology at NPS, including subsystem testing, engineering unit qualification, and flight unit testing. In addition, the new Cal Poly CubeSat Test POD Mk III will be introduced and evaluated based upon comparison with the Poly Picosatellite Orbital Deployer (P-POD). Using examples from the development of NPS-SCAT and test data from Cal Poly’s Test POD Mk III and P-POD, the current CubeSat testing methodology will be verified and an improved method for NPS CubeSat subsystem testing will be presented.
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Lysoněk, Milan. "Systém pro automatické filtrování testů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2020. http://www.nusl.cz/ntk/nusl-417281.
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Cílem této práce je vytvořit systém, který je schopný automaticky určit množinu testů, které mají být spuštěny, když dojde v ComplianceAsCode projektu ke změně. Navržená metoda vybírá množinu testů na základě statické analýzy změněných zdrojových souborů, přičemž bere v úvahu vnitřní strukturu ComplianceAsCode. Vytvořený systém je rozdělen do čtyř částí - získání změn s využitím verzovacího systému, statická analýza různých typů souborů, zjištění souborů, které jsou ovlivněny těmi změnami, a výpočet množiny testů, které musí být spuštěny pro danou změnu. Naimplementovali jsme analýzu několika různých typů souborů a náš systém je navržen tak, aby byl jednoduše rozšiřitelný o analýzy dalších typů souborů. Vytvořená implementace je nasazena na serveru, kde automaticky analyzuje nové příspěvky do ComplianceAsCode projektu. Automatické spouštění informuje přispěvatelé a vývojáře o nalezených změnách a doporučuje, které testy by pro danou změnu měly být spuštěny. Tím je ušetřen čas strávený při kontrole správnosti příspěvků a čas strávený spouštěním testů.
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Chia-Hung, Tsai. "Power Reduction for Scan Testing Based on Scan Cell Ordering Power Reduction for Scan Testing Based on Scan Cell Ordering." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611303340.
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Ching-Hua, Chiu. "Scan Cell Ordering for Power Reduction during Scan Testing." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611332527.
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Chiu, Ching-Hua, and 邱清華. "Scan Cell Ordering for Power Reduction during Scan Testing." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/44105113962893031493.
Full textAbstract:
碩士元智大學
資訊工程學系
93
Low power consumption during test application has become increasingly important in the present VLSI design. Scan-based architectures are expensive in power consumption during scanning in test vectors. Excessive power consumption during test application may result in increased product cost and decrease of overall yield. Hence, minimizing power consumption during scan test will prevent from yield loss and thus reduce product cost. The purpose of this thesis is to minimize power consumption during scan test by appropriately ordering the scan cells. In this thesis, we use an induced activity function to measure the impact of reducing the transition density at a selected pseudo input on totally switching activity in CUT. We order the scan cells in descending order according to the values of the induced activity function. We also exploit the unspecified values in the test vectors to maximize the reduction of switching activity during scan test. Besides, layout constraint is an important consideration during ordering scan cells. Hence, we develop a procedure to order scan cell without violating layout constraint. Experimental results show that the proposed approach can reduce power consumption significantly during test.
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Tsai, Jung-Chien, and 蔡榮鍵. "SOC Integration Testing With Low Power Scan Testing Circuit." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/34086587871390274110.
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碩士中華大學
電機工程學系(所)
96
In the past，the system must be integrated on circuit board but due to the great development of IC technology，it can implement on signal chip now，it is naming system on chip （SOC）。In order to improve system performance and reduce the cost，SOC has already become the development trend of IC industry。 Because Intelligently Property and Memories are two major elements of SOC，so IP re-use deriving out a lot of difficulty and challenge for SOC integration test 。For SOC design ，it will increase the test cost，if use a large of varies memories 。Under test mode，the test is too hot，power dissipation is higher than normal operation mode（peak power up to 20X，average power up to 2-5X）。SOC integration test become prime cost during SOC development 。In this thesis ，we use lower power scan-based method and integrate IEEE1149.1 and IEEE1500 architecture to test and control SOC design 。Finally we do a experiment using Verilog to implement the integration architecture and check the waveform to verify the function. We can provide a complete and simple SOC test architecture for SoC integration designer.
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Ptak, Alan. "Fault tolerance and testing with boundary scan." 1990. http://hdl.handle.net/1993/17201.
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Tsai, Chia-Hung, and 蔡嘉鴻. "Power Reduction for Scan Testing Based on Scan Cell Ordering 降低掃瞄試期間之功率消耗Power Reduction for Scan Testing Based on Scan Cell Ordering." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/08722003069959744814.
Full textAbstract:
碩士元智大學
資訊工程學系
94
Scan-based circuit structure is widely used in circuit test design. The power consumption of a CUT (Circuit Under Test), however, arises during the test procedure. Excessive power consumption during test procedure may increase the cost of product and results in the decrease of overall yield. An effective solution is proposed in this thesis to overcome this problem by using a three-stage methodology. Firstly, we define the influence degree contributed by each scan cell in CUT when the test vector is shifting. Then we apply a weight for each pairs of scan cell according to transition degrees in different orders. In the third stage, a transition graph with directions is constructed and a search algorithm is applied to find the optima path, which has the lowest cost, to determine the orders of scan cells. In addition, layout constraints are also adopted as constrains in the search algorithm, thus it will not violate the layout rules in deciding the order of each pair of scan cells. We verified our proposed method via benchmark circuits, and the result shows obviously lower power consumption when comparing to the results of other papers that ignored influence degree of each scan cell under shifting.
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Lee, Jinkyu. "Low power scan testing and test data compression." Thesis, 2006. http://hdl.handle.net/2152/2568.
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Hu, Jia-Wei, and 胡家瑋. "Low-Power Transition Testing in Partial Scan Design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/71493630957278295158.
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碩士中原大學
電子工程研究所
97
In this thesis, we propose a method of selecting partial flip-flops for testing transition delay faults. As compared to full-scan design, this partial-scan method can achieve higher fault coverage and lower testing power. Scan flip-flops are selected based on controllability and observability of input signals and output gates of flip-flops. The non-scan flip-flops are controlled by another clock to freeze partial circuit during shift operation of scan testing. Experimental results on ISCAS89 benchmarks show that the proposed technique can reduce both average and peak power in shift and capture cycle than full-scan design. In addition, the method can also provide higher LOC transition fault coverage and utilize lower area overhead.
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范姜弘宇. "The Testing of Micropipeline with New Scan Registers." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/22764132877487725330.
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Huang, Chien-Fu, and 黃建輔. "Reconfigurable Scan Chain Design for Delay Fault Testing." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/49251464621904773593.
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碩士國立成功大學
電機工程學系碩博士班
94
Enhancing coverage for delay fault testing has becoming more important for deep sub-micron designs. The general method in delay fault testing is by scan-based approach. Although the fault coverage of general circuits can be up to at least 60~70 percent, there are still a large portions of faults which can’t be detected. The larger losses in coverage, the more risk of test-escape is induced. In order to gain higher fault coverage, we proposed a new idea that implements two different scan orders by reconfigurable architecture. We generate first scan ordering and second scan ordering with the heuristic algorithms. By our method, for most of sequential elements, we just add a simple multiplexer in hardware realization. Experimental results show the superior of this approach which demonstrates more than 90 percent fault coverage for most of circuits.
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Huang, Shun-Jie, and 黃順傑. "Reducing Static and Dynamic Power in Scan Testing." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/67029547627699981970.
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碩士國立中興大學
資訊科學與工程學系
96
Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique for static and dynamic power reduction in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current in the scan shift process. The proposed method is simulated by SPICE with BPTM 22nm technology, and the results show that on the average 15% total power reduction is achievable by the proposed method. By our analysis, because of large amount of the inverters, and no matter in which input signal the leakage current of an inverter is quite large, so the reduced amount of average power is restrained.
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Sangkaralingam, Ranganathan. "Techniques for reducing power dissipation during scan testing." Thesis, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3110687.
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Xie, Zheng-Yi, and 謝政益. "Scan Chain Partitioning for Low Capture Power Testing." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/56590246246816639292.
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碩士元智大學
資訊工程學系
98
Power consumption is an important issue for circuit testing. In this paper, we fo-cus on reducing capture power for multiple scan chains testing. This method reduces capture power by disabling as many scan chains as possible while keeping the fault coverage high. Identifying the response data captured for each test pattern, only few of them are specified bits. Only those scan cells that capture specified bits contribute to the fault coverage. The basic idea of this method is to construct multiple scan chains based on the analysis of the criticality of each scan cell so that, in the capture mode, the overall number of scan chains disabled is maximized. Experimental results for the large ISCAS’89 circuits have shown that this method can achieve an average reduction in capture power over 40%.
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Lee, Cherng-Hann, and 李承翰. "Chain Decision for Low-Power Multiple Scan Testing." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/60383327710231964956.
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碩士中原大學
電子工程研究所
100
In this paper, we propose a method of chain decision for low-power multiple scan chain testing on transition delay faults (TDF). We generated and analyzed the patterns of launch-off-capture (LOC) testing for TDF. These patterns are designed for the multiple scan testing framework, in which each pattern need to shift, launch, and capture data on only one scan chain. Accordingly the flip-flops are selected into separate groups. We revised a previous multiple scan chain division method for stuck-at faults testing with additional consideration of transition bits between the first and second patterns of TDFs. In this method, each pattern produces one active scan chain only, therefore making low-power LOC testing be possible. Currently we have experimented on a part of ISCAS98 circuits to prove the feasibility of proposed method. In the future we will analyze the effect of power reduction on testing, and apply the method to larger ISCAS98 circuits.
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Min-Hao, Chiu. "Jump Scan: A DFT Technique for Low Power Testing." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2207200500092800.
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Chiu, Min-Hao, and 邱銘豪. "Jump Scan: A DFT Technique for Low Power Testing." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/52041775619598250286.
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碩士國立臺灣大學
電子工程學研究所
93
This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by 67% compared to the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability (DFT) methodology and needs no extra computation. The penalties are area overhead and speed degradation.
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Lin, Hsiu-Ting, and 林修霆. "Low Power Test Pattern Generation for Scan-based Testing." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/56294630876466355137.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
96
Power dissipation is a serious problem for scan-based testing because it can cause catastrophic damaging of circuit under test or degrade power integrity during test. This thesis proposes two effective low power automatic test pattern generation (ATPG) flows to reduce the peak power during scan-based testing. The first technique is CASPR, Capture and Shift Power Reduction. It includes parity backtrace, confined fault propagation, dynamic controllability, X-filling procedure for both shift and capture, and test regeneration and all techniques of CASPR can be integrated to conventional test generation flow. The experimental data on ISCAS89 benchmark circuits show that CASPR succeed to reduce the peak capture power by 31% and peak shift power by 26% in single stuck at fault test pattern generation with only 11.2% test length overhead. The second technique called CASTR, Capture and Shift Toggle Reduction, proposes a new low power test generation flow to handle the exceeded power noise problem during testing. Exceeded power noise can degrade power integrity and increase the probability of yield loss. We combine both pseudo boolean optimization and random simulation flow into X-Constraint ATPG. Moreover, a modified test regeneration procedure based X-identification techniques is also introduced to further improve the results. In the experimental results, we can reduction the peak shift flip-flop transition count (FFTC), which is showed to be highly correlation with power noise, by 35% with negligible test length overhead by CASTR. The same technique can also be applied for peak capture FFTC reduction.
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Lin, Hsiu-Ting. "Low Power Test Pattern Generation for Scan-based Testing." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0107200811431900.
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Li, Tsung-Yeh, and 李宗燁. "AC+ Scan Based Delay Testing and Characterization over HOY Platform." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/36839372017509198465.
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碩士國立清華大學
電機工程學系
97
Small delay defects, often escaping from traditional delay testing, could cause a device to function abnormally in the field. Therefore detecting these defects is often necessary in modern delay testing. To address this issue, we propose three test modes in a new methodology called AC+ scan, meaning that the resolution of traditional AC scan test can be enhanced by embedding an All-Digital Phase-Locked Loop (ADPLL) into a circuit under test (CUT). AC+ scan can be executed by a next-generation test platform, HOY platform. The first test mode of our AC+ scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that this method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips will be more likely to cause failure in the field. The third test mode is to extract the waveform of each flip-flop’s output in a real chip. This is made possible by taking advantage of the almost unlimited test memory on HOY test platform, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debug. We have successfully manufactured a Viterbi decoder chip with feature of AC+ scan inside to demonstrate its capability.
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Hu, Kai-Shun, and 胡凱舜. "A Low Power Test Pattern Generation Methodology for Scan Testing." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/10268214800467270201.
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碩士國立臺灣大學
電機工程學研究所
95
Average and peak power management has become a serious challenge for scan-based testing. This thesis proposes a test pattern generation methodology that reduces the power dissipation during the shift and capture cycles of conventional scan testing. The proposed methodology utilizes a power-constrained ATPG engine and a dynamic compaction scheme to generate partially specified low power patterns. Then, X-filling together with test pattern ordering is employed to enhance the achievable power reduction. Besides, a mechanism of integration with commercial ATPG is proposed which iteratively replaces the high power consumption patterns with low power ones. Furthermore, the proposed low power test pattern generation methodology can be extent to various fault models, different test application scheme, and different test application conditions. The proposed technique is validated using ISCAS89 benchmark circuits.
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Ho, Chia-Ming, and 何嘉銘. "Novel Scan Techniques for Low Power and Low Cost Testing." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/53753819128553217409.
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碩士國立成功大學
電機工程學系碩博士班
93
With the progress of very large scale integration (VLSI) techniques, the circuit complexity increases dramatically. To enhance the testability of the circuit, many design for testability (DFT) techniques are developed. Scan technique is one of these techniques and is widely used in industry. However, excess power dissipation and large test cost are two critical problems of scan testing. The test cost is composed of three main factors, namely test application time, test data volume and the number of test pins. In the power aspect, recently the multiple capture orders technique has been used to reduce both average and peak power dissipation. The technique, however, requires long test generation time. In this thesis, we propose a modified test pattern generation procedure to shorten the test pattern generation time. Furthermore, we propose a novel scan technique to reduce the test application time, test data volume, and test power dissipation simultaneously. The basic idea is to analyze the compatibility of scan flip-flops and construct multiple scan chains with single scan input without any fault coverage degradation. This technique can be directly applied to the configuration of multiple scan inputs according to the number of available test channels. Besides, we also give a low power technique applied to our scan architecture. Experimental results for large ISCAS’89 benchmark circuits show that with single scan input, the proposed method can reduce the test application time and test data volume by 90%, and reduce power dissipation by 96.3% in average compared with conventional scan methodology. As described above, we can efficiently reduce the test power dissipation and can reduce the test application time and test data volume without extra test pins. Hence, the two critical problems of scan testing can be solved.
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Hu, Kai-Shun. "A Low Power Test Pattern Generation Methodology for Scan Testing." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2507200711194500.
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Chen, Tsung-Tang, and 陳宗塘. "X-Filling Methodology for Power-Aware At-Speed Scan Testing." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/46630519415611587303.
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碩士淡江大學
電機工程學系碩士班
97
ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). Adjacent Backtracing fill, in which both the adjacent and backtracing filling algorithm are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of unknown value (x) bits as in test compression, and it is a low capture power and considering the shift power test pattern. Experimental results for ISCAS’89 benchmark circuits show that the proposed scheme respectively outperforms previous method in capture power.
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Liu, Yu-Ping, and 劉裕平. "Improving Speed-Path Diagnosis Resolution for At-Speed Scan Testing." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/97853845666519797857.
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碩士國立臺灣大學
電子工程學研究所
100
The operating clock frequency is an important performance metric of a high performance VLSI (very large-scale integration) product. Pushing clock frequency to a higher level through several design iterations (or design stepping) has become an important part of design process. In design stepping, speed-path is the path that limits the performance of a chip. The speed-path has different definition from critical path. Critical path is the path with longest delay in the nominal design, whereas there can be many speed-paths after manufacturing. The speed-path identification plays a critical role for design performance optimization. However, as the chip density keeps growing, it becomes challenging to find speed-paths of one chip from all sensitized paths with at-speed scan test patterns. In this work, we use the method in [1] to generate an initial speed-path candidate (or suspect) set which has been proved to contain all real speed-paths. At first we derive a methodology to find conclusive speed-path by observing the relationship between the speed-path suspects. Then for the other speed-paths suspects called inconclusive speed-paths, we use a novel Boolean expression algorithm to provide a solution set for all possible combinations that describe the observed failing bits. By dealing with these Boolean expressions, we can remove fake speed-paths that cannot result in errors on the output. Finally we can feedback the conclusive speed-path and the remaining speed-paths to debug engineer to do design fix and performance optimization.
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Bing-Ling, Tsai. "A Test Vector Ordering Approach for Power Reduction during Scan Testing." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611294168.
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