Academic literature on the topic 'Scan testing'
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Journal articles on the topic "Scan testing"
Maunder, Colin. "Boundary-scan testing." Microprocessors and Microsystems 17, no. 5 (June 1993): 258. http://dx.doi.org/10.1016/0141-9331(93)90001-n.
Full textSachdev, M. "Testing Defects in Scan Chains." IEEE Design and Test of Computers 12, no. 4 (1995): 45. http://dx.doi.org/10.1109/mdt.1995.473312.
Full textSachdev, M. "Testing defects in scan chains." IEEE Design & Test of Computers 12, no. 4 (1995): 45–51. http://dx.doi.org/10.1109/54.491237.
Full textArvaniti, Efi, and Yiorgos Tsiatouhas. "Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique." Journal of Electronic Testing 30, no. 3 (May 22, 2014): 329–41. http://dx.doi.org/10.1007/s10836-014-5453-9.
Full textMojtabavi Naeini, Mahshid, and Chia Yee Ooi. "A Novel Scan Architecture for Low Power Scan-Based Testing." VLSI Design 2015 (April 22, 2015): 1–13. http://dx.doi.org/10.1155/2015/264071.
Full textTouati, Aymen, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, and Etienne Auvray. "Scan-Chain Intra-Cell Aware Testing." IEEE Transactions on Emerging Topics in Computing 6, no. 2 (April 1, 2018): 278–87. http://dx.doi.org/10.1109/tetc.2016.2624311.
Full textXijiiang Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli. "High-frequency, at-speed scan testing." IEEE Design & Test of Computers 20, no. 5 (September 2003): 17–25. http://dx.doi.org/10.1109/mdt.2003.1232252.
Full textDervisoglu, B. I. "Scan-path architecture for pseudorandom testing." IEEE Design & Test of Computers 6, no. 4 (August 1989): 32–48. http://dx.doi.org/10.1109/54.32420.
Full textKavousianos, Xrysovalantis, Dimitris Bakalis, and Dimitris Nikolos. "Efficient partial scan cell gating for low-power scan-based testing." ACM Transactions on Design Automation of Electronic Systems 14, no. 2 (March 2009): 1–15. http://dx.doi.org/10.1145/1497561.1497571.
Full textLi, Jia, Yu Hu, and XiaoWei Li. "Scan chain design for shift power reduction in scan-based testing." Science China Information Sciences 54, no. 4 (February 28, 2011): 767–77. http://dx.doi.org/10.1007/s11432-011-4205-z.
Full textDissertations / Theses on the topic "Scan testing"
Hassan, Abu S. M. (Abu Saleem Mahmudul). "Testing of board interconnects using boundary scan architecture." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74304.
Full textIn the recent past, several researchers have proposed different schemes for PCB interconnect testing based on the boundary scan architecture.
In this dissertation, a new approach, based on the concept of built-in self-test (BIST), is developed using the boundary scan architecture for PCB interconnect testing. BIST, at the component level, generally consists of incorporating additional circuitry on the chip to generate test patterns and to compact the response of the circuit under test into a reference signature. For the PCB level BIST, the board is considered as the unit under test. A family of BIST schemes are developed for board interconnect testing utilizing the properties of the boundary scan architecture. The BIST approach has removed the dependence on automatic test equipment (ATE) for generation of test vector sets and analysis of output data sets. Techniques are developed for the generation of test vector sets which require very simple test generation hardware. Test vector sets are shown to be independent of the order of the input/output (I/O) scan cells in the boundary scan chain and of the structural complexity of the interconnects under test. Response compaction techniques proposed in the schemes are such that fault detection and diagnosis can be done independent of the topological information about the interconnects. These response compaction techniques can be implemented within each boundary scan cell or outside the boundary scan chain, providing a trade-off in terms of test time and hardware complexity. The various uses of the boundary scan architecture make the proposed schemes more attractive and advantageous than the existing approaches for board interconnect testing.
Moreover, a family of interconnect testing schemes is proposed for a partial boundary scan environment. Partial boundary scan environment refers to a board with a mix of boundary scan and non-boundary scan components. Such an environment is more complex compared to a complete boundary scan environment. The proposed schemes are BIST-able despite the inherently complex test environment. However, fault coverage is limited because of the reduced accessibility of the partial boundary scan environment.
McBean, David P. O. "Board interconnect testing in a boundary scan environment." Thesis, University of Oxford, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333253.
Full textPanda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.
Full textJayaram, Vinay B. "Experimental Study of Scan Based Transition Fault Testing Techniques." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31146.
Full textMaster of Science
Xu, Gefu Singh Adit D. "Delay Test Scan Flip-Flop c(DTSFF) design and its applications for scan based delay testing." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Fall%20Dissertations/Xu_Gefu_18.pdf.
Full textMahmoud, Ahmed Gamal Mohamed. "Boundary-scan for High-speed Serial Links." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018.
Find full textKrug, Margrit Reni. "Aumento da testabilidade do hardware com auxilio de técnicas de teste de software." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12672.
Full textBoth software and hardware designs require several tasks to increase reliability and ensure high quality of the final system. Although different techniques, tools and methods can be applied, error free products are difficult to be achieved. Errors may occur on design specification, on development stages and also during manufacturing process. To increase system quality and minimize costs it is mandatory to perform design verification, prototype validation and manufacturing test. For a long time hardware and software tests were studied as disciplines completely apart. However, similarities between software development and hardware design have already been explored successfully by adapting techniques originally developed for one of them, and applying to the other. For instance, code coverage concept and methods were firstly developed for software testing, but nowadays are commonly used in hardware verification. Due to the high similarity observed between software programming languages and hardware description languages (HDL), it seems to be a valuable approach applying software engineering techniques to help ensuring a high quality hardware device. Therefore, the main purpose of this thesis is to use such techniques to extract test patterns from HDL descriptions of hardware devices and to identify at these descriptions means to increase hardware testability.
Greher, Michael R. "Measuring attention: An evaluation of the Search and Cancellation of Ascending Numbers (SCAN) and the short form of the Test of Attentional and Interpersonal Style (TAIS)." Thesis, University of North Texas, 2000. https://digital.library.unt.edu/ark:/67531/metadc2529/.
Full textPoulos, Konstantinos. "NEW TECHNIQUES ON VLSI CIRCUIT TESTING & EFFICIENT IMPLEMENTATIONS OF ARITHMETIC OPERATIONS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1872.
Full textGHOSH, SWAROOP. "SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670.
Full textBooks on the topic "Scan testing"
K, Cheung Peter Y., ed. Boundary-scan interconnect diagnosis. Boston: Kluwer Academic, 2001.
Find full textParker, Kenneth P. The Boundary-Scan handbook. Boston: Kluwer Academic Publishers, 1992.
Find full textThe boundary-scan handbook. 3rd ed. Boston, Mass: Kluwer Academic Publishers, 2003.
Find full textSousa, José T. de. Boundary-scan interconnect diagnosis. Boston: Kluwer Academic Publishers, 2001.
Find full textJardine, P. N. The boundary-scan architecture standard IEEE-1149.1 (1990): The technology and its use. Leatherhead, Surrey, England: ERA Technology, 1993.
Find full textParker, Kenneth P. The boundary-scan handbook: Analog and digital. 2nd ed. Boston: Kluwer Academic Publishers, 1998.
Find full textParker, Kenneth P. The boundary-scan handbook: Analog and digital. 2nd ed. New York: Kluwer Academic, 2002.
Find full textden, Eijnden Peter van, and Jong Frans de, eds. Boundary-scan test: A practical approach. Dordrecht: Kluwer Academic Publishers, 1993.
Find full textParker, Kenneth P. The Boundary-Scan Handbook. 3rd ed. Springer, 2003.
Find full textSousa, José T. de, and Peter Y. K. Cheung. Boundary-Scan Interconnect Diagnosis. Springer, 2010.
Find full textBook chapters on the topic "Scan testing"
Bleeker, Harry, Peter van den Eijnden, and Frans de Jong. "PCB Testing." In Boundary-Scan Test, 1–17. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3132-6_1.
Full textParker, Kenneth P. "Boundary-Scan Testing." In The Boundary-Scan Handbook, 97–141. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2142-3_3.
Full textParker, Kenneth P. "Boundary-Scan Testing." In The Boundary — Scan Handbook, 107–47. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0367-5_3.
Full textParker, Kenneth P. "Boundary-Scan Testing." In The Boundary-Scan Handbook, 109–48. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-01174-5_3.
Full textParker, Kenneth P. "Advanced Boundary-Scan Testing." In The Boundary-Scan Handbook, 143–61. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2142-3_4.
Full textMcDermid, John. "Structural Testing." In Analog and Mixed-Signal Boundary-Scan, 127–50. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4499-6_6.
Full textParker, Kenneth P. "Design for Boundary-Scan Testing." In The Boundary-Scan Handbook, 163–99. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2142-3_5.
Full textGlaz, Joseph, Joseph Naus, and Sylvan Wallenstein. "Testing for Clustering Superimposed on a Nonuniform Density and Related Generalizations of Ballot Problems." In Scan Statistics, 261–72. New York, NY: Springer New York, 2001. http://dx.doi.org/10.1007/978-1-4757-3460-7_15.
Full textParker, Kenneth P. "IEEE 1149.6: Testing Advanced I/O." In The Boundary — Scan Handbook, 267–318. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0367-5_8.
Full textParker, Kenneth P. "IEEE 1149.6: Testing Advanced I/O." In The Boundary-Scan Handbook, 269–320. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-01174-5_8.
Full textConference papers on the topic "Scan testing"
Paramasivam, K., K. Gunavathi, and A. Nirmalkumar. "Modified scan architecture for an effective scan testing." In TENCON 2008 - 2008 IEEE Region 10 Conference (TENCON). IEEE, 2008. http://dx.doi.org/10.1109/tencon.2008.4766794.
Full textSatya Valibaba, D., S. Sivanantham, P. S. Mallick, and J. Raja Paul Perinbam. "Reduction of testing power with pulsed scan flip-flop for scan based testing." In 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN). IEEE, 2011. http://dx.doi.org/10.1109/icsccn.2011.6024608.
Full textWestcott, Mark. "Corrective surface aspherizing to optimize scan lens distortion." In Optical Fabrication and Testing. Washington, D.C.: OSA, 2000. http://dx.doi.org/10.1364/oft.2000.otuc1.
Full textHilla, S. C. "Boundary scan testing for multichip modules." In Proceedings International Test Conference 1992. IEEE, 1992. http://dx.doi.org/10.1109/test.1992.527823.
Full textXinning Liu, Jun Yang, and Xiaojing Wen. "A Novel Multi-Capture Scan Testing." In 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415806.
Full textSingh, Adit D. "Scan Delay Testing of Nanometer SoCs." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.134.
Full textDong Xiang, Kai wei Li, and Hideo Fujiwara. "Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops." In Proceedings. 14th Asian Test Symposium. IEEE, 2005. http://dx.doi.org/10.1109/ats.2005.46.
Full textPomeranz, Irith. "Random limited-scan to improve random pattern testing of scan circuits." In the 38th conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/378239.378385.
Full textHirase, J., Y. Goi, and Y. Tanaka. "IDDQ Testing Method using a Scan Pattern for Production Testing." In 14th Asian Test Symposium (ATS'05). IEEE, 2005. http://dx.doi.org/10.1109/ats.2005.66.
Full textWooheon Kang, Hyunyul Lim, and Sungho Kang. "Scan cell reordering algorithm for low power consumption during scan-based testing." In 2014 International SoC Design Conference (ISOCC). IEEE, 2014. http://dx.doi.org/10.1109/isocc.2014.7087659.
Full textReports on the topic "Scan testing"
LaMothe, Margaret E. Repetitive Cyclic Potentiodynamic Polarization Scan Results for Reduced Sample Volume Testing. Office of Scientific and Technical Information (OSTI), March 2016. http://dx.doi.org/10.2172/1241885.
Full textCarlson, Damian, Jennifer De Lurio, Andrea Druga, Randy Hulshizer, Marcus Lynch, and Misha Mehta. PCORI COVID-19 Scan: Isolation Bags for Safe CT Imaging, Population-wide Antibody Testing (June 25-July 8, 2020). Patient-Centered Outcomes Research Institute (PCORI), July 2020. http://dx.doi.org/10.25302/bcs4.2020.7.
Full textTom, Joe, Marcelo Garcia, and Haode Wang. Review of Methodologies to Assess Bridge Safety During and After Floods. Illinois Center for Transportation, May 2022. http://dx.doi.org/10.36501/0197-9191/22-008.
Full textMancini, T., C. Cameron, and V. Goldberg. The feasibility of testing NASA's SCAD concentrator on earth. Office of Scientific and Technical Information (OSTI), July 1991. http://dx.doi.org/10.2172/5652585.
Full textPCORI COVID-19 Scan: College, University, and Employee Testing Programs (September 17-30, 2020). Patient-Centered Outcomes Research Institute (PCORI), October 2020. http://dx.doi.org/10.25302/bcs10.2020.10.
Full textPCORI Biweekly COVID-19 Scan: Testing Impact Calculator, Ellume Home Test (December 24, 2020-January 8, 2021). Patient-Centered Outcomes Research Institute (PCORI), January 2021. http://dx.doi.org/10.25302/bcs17.2021.1.
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