Relevant bibliographies by topics / Scan testing

Academic literature on the topic 'Scan testing'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Scan testing"

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Maunder, Colin. "Boundary-scan testing." Microprocessors and Microsystems 17, no. 5 (June 1993): 258. http://dx.doi.org/10.1016/0141-9331(93)90001-n.

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Sachdev, M. "Testing Defects in Scan Chains." IEEE Design and Test of Computers 12, no. 4 (1995): 45. http://dx.doi.org/10.1109/mdt.1995.473312.

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Sachdev, M. "Testing defects in scan chains." IEEE Design & Test of Computers 12, no. 4 (1995): 45–51. http://dx.doi.org/10.1109/54.491237.

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Arvaniti, Efi, and Yiorgos Tsiatouhas. "Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique." Journal of Electronic Testing 30, no. 3 (May 22, 2014): 329–41. http://dx.doi.org/10.1007/s10836-014-5453-9.

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Mojtabavi Naeini, Mahshid, and Chia Yee Ooi. "A Novel Scan Architecture for Low Power Scan-Based Testing." VLSI Design 2015 (April 22, 2015): 1–13. http://dx.doi.org/10.1155/2015/264071.

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Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.
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Touati, Aymen, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, and Etienne Auvray. "Scan-Chain Intra-Cell Aware Testing." IEEE Transactions on Emerging Topics in Computing 6, no. 2 (April 1, 2018): 278–87. http://dx.doi.org/10.1109/tetc.2016.2624311.

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Xijiiang Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli. "High-frequency, at-speed scan testing." IEEE Design & Test of Computers 20, no. 5 (September 2003): 17–25. http://dx.doi.org/10.1109/mdt.2003.1232252.

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Dervisoglu, B. I. "Scan-path architecture for pseudorandom testing." IEEE Design & Test of Computers 6, no. 4 (August 1989): 32–48. http://dx.doi.org/10.1109/54.32420.

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Kavousianos, Xrysovalantis, Dimitris Bakalis, and Dimitris Nikolos. "Efficient partial scan cell gating for low-power scan-based testing." ACM Transactions on Design Automation of Electronic Systems 14, no. 2 (March 2009): 1–15. http://dx.doi.org/10.1145/1497561.1497571.

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Li, Jia, Yu Hu, and XiaoWei Li. "Scan chain design for shift power reduction in scan-based testing." Science China Information Sciences 54, no. 4 (February 28, 2011): 767–77. http://dx.doi.org/10.1007/s11432-011-4205-z.

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Dissertations / Theses on the topic "Scan testing"

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Hassan, Abu S. M. (Abu Saleem Mahmudul). "Testing of board interconnects using boundary scan architecture." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74304.

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The testing of printed circuit board (PCB) interconnects is a complex task that requires enormous amount of resources. With the increasing use of new technologies like surface mounting technology (SMT), testing PCB interconnects using the available techniques, like in-circuit testing and functional testing, is becoming very difficult. To make testing manageable, it must be considered earlier in the design process. This is known as 'design for testability' (DFT). A hierarchical DFT approach known as boundary scan architecture has recently become an increasingly attractive solution for PCB interconnect testing problems. This framework provides a scan path for electronic access to the interconnect test points, thus removing the need for accessibility through electro-mechanical contacts known as 'bed of nails'.
In the recent past, several researchers have proposed different schemes for PCB interconnect testing based on the boundary scan architecture.
In this dissertation, a new approach, based on the concept of built-in self-test (BIST), is developed using the boundary scan architecture for PCB interconnect testing. BIST, at the component level, generally consists of incorporating additional circuitry on the chip to generate test patterns and to compact the response of the circuit under test into a reference signature. For the PCB level BIST, the board is considered as the unit under test. A family of BIST schemes are developed for board interconnect testing utilizing the properties of the boundary scan architecture. The BIST approach has removed the dependence on automatic test equipment (ATE) for generation of test vector sets and analysis of output data sets. Techniques are developed for the generation of test vector sets which require very simple test generation hardware. Test vector sets are shown to be independent of the order of the input/output (I/O) scan cells in the boundary scan chain and of the structural complexity of the interconnects under test. Response compaction techniques proposed in the schemes are such that fault detection and diagnosis can be done independent of the topological information about the interconnects. These response compaction techniques can be implemented within each boundary scan cell or outside the boundary scan chain, providing a trade-off in terms of test time and hardware complexity. The various uses of the boundary scan architecture make the proposed schemes more attractive and advantageous than the existing approaches for board interconnect testing.
Moreover, a family of interconnect testing schemes is proposed for a partial boundary scan environment. Partial boundary scan environment refers to a board with a mix of boundary scan and non-boundary scan components. Such an environment is more complex compared to a complete boundary scan environment. The proposed schemes are BIST-able despite the inherently complex test environment. However, fault coverage is limited because of the reduced accessibility of the partial boundary scan environment.
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McBean, David P. O. "Board interconnect testing in a boundary scan environment." Thesis, University of Oxford, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333253.

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Panda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.

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Jayaram, Vinay B. "Experimental Study of Scan Based Transition Fault Testing Techniques." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31146.

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The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed load delay test (Launch-from-shift). Each method has its own drawbacks and many practical issues are associated with pattern generation and application. Our work focuses on the implementation and comparison of these transition fault testing techniques on multiple industrial ASIC designs. In this thesis, we present results from multiple designs and compare the two techniques with respect to test coverage, pattern volume and pattern generation time. For both methods, we discuss the effects of multiple clock domains, tester hardware considerations, false and multi-cycle paths and the implications of using a low cost tester. We then consider the implications of pattern volume on testing both stuck-at and transition faults and the effects of using transition fault patterns to test stuck-at faults. Finally, we present results from our analysis on switching activity of nets in the design, while executing transition fault patterns.
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Xu, Gefu Singh Adit D. "Delay Test Scan Flip-Flop c(DTSFF) design and its applications for scan based delay testing." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Fall%20Dissertations/Xu_Gefu_18.pdf.

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Mahmoud, Ahmed Gamal Mohamed. "Boundary-scan for High-speed Serial Links." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018.

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The complexity of integrated circuit (IC) designs continues to increase with the constant advancement of process technology and decrease of feature size in a relentless effort to achieve better performance and reach new milestones. However, with the increasing density and complexity comes a higher probability of defects occurring as well as a higher impact of these defects on the overall performance. Testing, thus, proves essential in order to guarantee defect-free designs. Effective and efficient testing in terms of both cost and time becomes essential as well because of the continually rising cost of testing. Abstract Serializer-deserializer (SerDes) devices or serial-link transceivers, which represent the device-under-test (DUT) in this thesis, are no different. Since the interface is the bottleneck in the performance of various systems, efforts continue to push for faster, smaller, and more power-efficient SerDes, leaving it with stringent specifications to meet. This leads to it being susceptible to the higher defect probability we just mentioned. As these are wireline transceivers, the robustness of the interconnects is especially critical. These defects that affect the interconnects are troublesome due to the fact that it is relatively easy for the fault to be masked which would indicate a non-existent fault within the design itself. In this thesis, we propose a test receiver that is capable of putting the interconnects under test in both DC-coupled and AC-coupled scenarios in compliance with the IEEE-1149.1 and IEEE-1149.6 standards.
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Krug, Margrit Reni. "Aumento da testabilidade do hardware com auxilio de técnicas de teste de software." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12672.

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O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técnicas, ferramentas e métodos empregados, não estão livres de erros que podem levar ao mau funcionamento do produto final. Estes erros podem ocorrer durante a especificação do projeto, como também em estágios finais do desenvolvimento ou no processo de manufatura. A fim de minimizar prejuízos é necessário garantir a qualidade do sistema a partir da verificação do projeto, da validação de protótipo e do teste de fabricação. Por muito tempo o teste de hardware e o teste de software foram estudados como disciplinas completamente independentes. Porém, similaridades entre o desenvolvimento de software e o projeto de hardware já foram exploradas com sucesso em adaptações de técnicas originalmente desenvolvidas para um sendo utilizadas por outro. Um exemplo é a cobertura de código, que foi inicialmente desenvolvida para o teste de software, e agora é comumente utilizada na verificação de hardware. Visto que dispositivos são descritos em linguagem de descrição de hardware, e estas possuem características semelhantes às linguagens de programação, parece uma boa alternativa valer-se desta semelhança para utilizar os métodos propostos pela engenharia de software para garantir a qualidade do hardware desenvolvido. Utilizar tais métodos para gerar padrões de teste para dispositivos de hardware descritos em HDL (Hardware Description Language) e identificar nestas descrições características que, alteradas, aumentem a testabilidade dos mesmos, são os principais objetivos desta tese.
Both software and hardware designs require several tasks to increase reliability and ensure high quality of the final system. Although different techniques, tools and methods can be applied, error free products are difficult to be achieved. Errors may occur on design specification, on development stages and also during manufacturing process. To increase system quality and minimize costs it is mandatory to perform design verification, prototype validation and manufacturing test. For a long time hardware and software tests were studied as disciplines completely apart. However, similarities between software development and hardware design have already been explored successfully by adapting techniques originally developed for one of them, and applying to the other. For instance, code coverage concept and methods were firstly developed for software testing, but nowadays are commonly used in hardware verification. Due to the high similarity observed between software programming languages and hardware description languages (HDL), it seems to be a valuable approach applying software engineering techniques to help ensuring a high quality hardware device. Therefore, the main purpose of this thesis is to use such techniques to extract test patterns from HDL descriptions of hardware devices and to identify at these descriptions means to increase hardware testability.
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Greher, Michael R. "Measuring attention: An evaluation of the Search and Cancellation of Ascending Numbers (SCAN) and the short form of the Test of Attentional and Interpersonal Style (TAIS)." Thesis, University of North Texas, 2000. https://digital.library.unt.edu/ark:/67531/metadc2529/.

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This study found a relationship between the Search and Cancellation of Ascending Numbers (SCAN), Digit Span, and Visual Search and Attention Test (VSAT). Data suggest the measures represent a common construct interpreted to be attention. An auditory distracter condition of the SCAN did not distract participants, while the measure exhibited ample alternate forms reliability. The study also found that the Test of Attentional and Interpersonal Style (TAIS) short form poorly predicted performance on the Digit Span, VSAT, and SCAN. Although the TAIS exhibited good internal consistency, the items likely measure the subjective perception of attention. Furthermore, discriminant and convergent validity of the TAIS were found to be poor.
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Poulos, Konstantinos. "NEW TECHNIQUES ON VLSI CIRCUIT TESTING & EFFICIENT IMPLEMENTATIONS OF ARITHMETIC OPERATIONS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1872.

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Testing is necessary factor to guarantee that ICs operate according to specifications before being delivered to customers. Testing is a process used to identify ICs containing imperfections or manufacturing defects that may cause failures. Inaccuracy and imperfections can be introduced during the fabrication of the chips due to the complex mechanical and chemical steps required during the manufacturing processes. The testing process step applies test patterns to circuits and analyzes their responses. This work focuses on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification.There has been a massive increase in the number of transistors integrated in a chip, and the complexity of the circuit is increasing along with it. This growth has become a bottleneck for the test developers. The proposed ATPG tool was designed for testing sequential circuits. Scan Chains in Design For Testability (DFT) gained more prominence due to the increase in the complexity of the modern circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods are needed. Even though scan chains implementation effectively increases observability and controllability, a big portion of the time is wasted while shifting in and shifting out the test patterns through the scan chain. Additionally, the modern applications require operating speed at higher frequencies and there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications.With the modern applications requiring operating speed at higher frequencies, there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications. Two main problems have been associated when using external test equipment to test high frequency circuits; the effect of the resistance and capacitance of the probe on the performance of the circuit under test which leads to a faulty evaluation; and the cost of a dedicated high frequency tester. To solve these problems innovative test techniques are needed such as Built In Test (BIT) where self-evaluation takes place with a small area overhead and reduced requirements for external equipment. In the proposed methodology a Built In Test (BIT) detection circuit provides an efficient way to transform the high frequency response of the circuit under test into a DC signal.This work is focused in two major fields. The first topic is on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification as explained. The second topic is focused on efficient implementations of arithmetic operations in arbitrary long numbers with emphasis to addition. Arbitrary-Precision arithmetic refers to a set of data structures and algorithms which allows to process much greater numbers that exceed the standard data types. . An application example where arbitrary long numbers are widely used is cryptography, because longer numbers offer higher encryption security. Modern systems typically employ up to 64-bit registers, way less than what an arbitrary number requires, while conventional algorithms do not exploit hardware characteristics as well. Mathematical models such as weather prediction and experimental mathematics require high precision calculations that exceed the precision found in most Arithmetic Logic Units (ALU). In this work, we propose a new scalable algorithm to add arbitrary long numbers. The algorithm performs bitwise logic operations rather than arithmetic on 64-bit registers. We propose two approaches of the same algorithm that utilize the same basic function created according to the rules of binary addition
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GHOSH, SWAROOP. "SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670.

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Books on the topic "Scan testing"

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K, Cheung Peter Y., ed. Boundary-scan interconnect diagnosis. Boston: Kluwer Academic, 2001.

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Parker, Kenneth P. The Boundary-Scan handbook. Boston: Kluwer Academic Publishers, 1992.

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The boundary-scan handbook. 3rd ed. Boston, Mass: Kluwer Academic Publishers, 2003.

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Sousa, José T. de. Boundary-scan interconnect diagnosis. Boston: Kluwer Academic Publishers, 2001.

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Jardine, P. N. The boundary-scan architecture standard IEEE-1149.1 (1990): The technology and its use. Leatherhead, Surrey, England: ERA Technology, 1993.

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Parker, Kenneth P. The boundary-scan handbook: Analog and digital. 2nd ed. Boston: Kluwer Academic Publishers, 1998.

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Parker, Kenneth P. The boundary-scan handbook: Analog and digital. 2nd ed. New York: Kluwer Academic, 2002.

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den, Eijnden Peter van, and Jong Frans de, eds. Boundary-scan test: A practical approach. Dordrecht: Kluwer Academic Publishers, 1993.

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Parker, Kenneth P. The Boundary-Scan Handbook. 3rd ed. Springer, 2003.

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Sousa, José T. de, and Peter Y. K. Cheung. Boundary-Scan Interconnect Diagnosis. Springer, 2010.

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Book chapters on the topic "Scan testing"

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Bleeker, Harry, Peter van den Eijnden, and Frans de Jong. "PCB Testing." In Boundary-Scan Test, 1–17. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3132-6_1.

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Parker, Kenneth P. "Boundary-Scan Testing." In The Boundary-Scan Handbook, 97–141. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2142-3_3.

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Parker, Kenneth P. "Boundary-Scan Testing." In The Boundary — Scan Handbook, 107–47. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0367-5_3.

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Parker, Kenneth P. "Boundary-Scan Testing." In The Boundary-Scan Handbook, 109–48. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-01174-5_3.

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Parker, Kenneth P. "Advanced Boundary-Scan Testing." In The Boundary-Scan Handbook, 143–61. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2142-3_4.

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McDermid, John. "Structural Testing." In Analog and Mixed-Signal Boundary-Scan, 127–50. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4499-6_6.

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Parker, Kenneth P. "Design for Boundary-Scan Testing." In The Boundary-Scan Handbook, 163–99. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4757-2142-3_5.

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Glaz, Joseph, Joseph Naus, and Sylvan Wallenstein. "Testing for Clustering Superimposed on a Nonuniform Density and Related Generalizations of Ballot Problems." In Scan Statistics, 261–72. New York, NY: Springer New York, 2001. http://dx.doi.org/10.1007/978-1-4757-3460-7_15.

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Parker, Kenneth P. "IEEE 1149.6: Testing Advanced I/O." In The Boundary — Scan Handbook, 267–318. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0367-5_8.

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Parker, Kenneth P. "IEEE 1149.6: Testing Advanced I/O." In The Boundary-Scan Handbook, 269–320. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-01174-5_8.

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Conference papers on the topic "Scan testing"

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Paramasivam, K., K. Gunavathi, and A. Nirmalkumar. "Modified scan architecture for an effective scan testing." In TENCON 2008 - 2008 IEEE Region 10 Conference (TENCON). IEEE, 2008. http://dx.doi.org/10.1109/tencon.2008.4766794.

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Satya Valibaba, D., S. Sivanantham, P. S. Mallick, and J. Raja Paul Perinbam. "Reduction of testing power with pulsed scan flip-flop for scan based testing." In 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN). IEEE, 2011. http://dx.doi.org/10.1109/icsccn.2011.6024608.

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Westcott, Mark. "Corrective surface aspherizing to optimize scan lens distortion." In Optical Fabrication and Testing. Washington, D.C.: OSA, 2000. http://dx.doi.org/10.1364/oft.2000.otuc1.

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Hilla, S. C. "Boundary scan testing for multichip modules." In Proceedings International Test Conference 1992. IEEE, 1992. http://dx.doi.org/10.1109/test.1992.527823.

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Xinning Liu, Jun Yang, and Xiaojing Wen. "A Novel Multi-Capture Scan Testing." In 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415806.

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Singh, Adit D. "Scan Delay Testing of Nanometer SoCs." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.134.

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Dong Xiang, Kai wei Li, and Hideo Fujiwara. "Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops." In Proceedings. 14th Asian Test Symposium. IEEE, 2005. http://dx.doi.org/10.1109/ats.2005.46.

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Pomeranz, Irith. "Random limited-scan to improve random pattern testing of scan circuits." In the 38th conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/378239.378385.

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Hirase, J., Y. Goi, and Y. Tanaka. "IDDQ Testing Method using a Scan Pattern for Production Testing." In 14th Asian Test Symposium (ATS'05). IEEE, 2005. http://dx.doi.org/10.1109/ats.2005.66.

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Wooheon Kang, Hyunyul Lim, and Sungho Kang. "Scan cell reordering algorithm for low power consumption during scan-based testing." In 2014 International SoC Design Conference (ISOCC). IEEE, 2014. http://dx.doi.org/10.1109/isocc.2014.7087659.

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Reports on the topic "Scan testing"

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LaMothe, Margaret E. Repetitive Cyclic Potentiodynamic Polarization Scan Results for Reduced Sample Volume Testing. Office of Scientific and Technical Information (OSTI), March 2016. http://dx.doi.org/10.2172/1241885.

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Carlson, Damian, Jennifer De Lurio, Andrea Druga, Randy Hulshizer, Marcus Lynch, and Misha Mehta. PCORI COVID-19 Scan: Isolation Bags for Safe CT Imaging, Population-wide Antibody Testing (June 25-July 8, 2020). Patient-Centered Outcomes Research Institute (PCORI), July 2020. http://dx.doi.org/10.25302/bcs4.2020.7.

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Tom, Joe, Marcelo Garcia, and Haode Wang. Review of Methodologies to Assess Bridge Safety During and After Floods. Illinois Center for Transportation, May 2022. http://dx.doi.org/10.36501/0197-9191/22-008.

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This report summarizes a review of technologies used to monitor bridge scour with an emphasis on techniques appropriate for testing during and immediately after design flood conditions. The goal of this study is to identify potential technologies and strategies for Illinois Department of Transportation that may be used to enhance the reliability of bridge safety monitoring during floods from local to state levels. The research team conducted a literature review of technologies that have been explored by state departments of transportation (DOTs) and national agencies as well as state-of-the-art technologies that have not been extensively employed by DOTs. This review included informational interviews with representatives from DOTs and relevant industry organizations. Recommendations include considering (1) acquisition of tethered kneeboard or surf ski-mounted single-beam sonars for rapid deployment by local agencies, (2) acquisition of remote-controlled vessels mounted with single-beam and side-scan sonars for statewide deployment, (3) development of large-scale particle image velocimetry systems using remote-controlled drones for stream velocity and direction measurement during floods, (4) physical modeling to develop Illinois-specific hydrodynamic loading coefficients for Illinois bridges during flood conditions, and (5) development of holistic risk-based bridge assessment tools that incorporate structural, geotechnical, hydraulic, and scour measurements to provide rapid feedback for bridge closure decisions.
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Mancini, T., C. Cameron, and V. Goldberg. The feasibility of testing NASA's SCAD concentrator on earth. Office of Scientific and Technical Information (OSTI), July 1991. http://dx.doi.org/10.2172/5652585.

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PCORI COVID-19 Scan: College, University, and Employee Testing Programs (September 17-30, 2020). Patient-Centered Outcomes Research Institute (PCORI), October 2020. http://dx.doi.org/10.25302/bcs10.2020.10.

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PCORI Biweekly COVID-19 Scan: Testing Impact Calculator, Ellume Home Test (December 24, 2020-January 8, 2021). Patient-Centered Outcomes Research Institute (PCORI), January 2021. http://dx.doi.org/10.25302/bcs17.2021.1.

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