Journal articles: 'Scalar processor'

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Soliman, Mostafa I., and Elsayed A. Elsayed. "Simultaneous Multithreaded Matrix Processor." Journal of Circuits, Systems and Computers 24, no. 08 (August 12, 2015): 1550114. http://dx.doi.org/10.1142/s0218126615501145.

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This paper proposes a simultaneous multithreaded matrix processor (SMMP) to improve the performance of data-parallel applications by exploiting instruction-level parallelism (ILP) data-level parallelism (DLP) and thread-level parallelism (TLP). In SMMP, the well-known five-stage pipeline (baseline scalar processor) is extended to execute multi-scalar/vector/matrix instructions on unified parallel execution datapaths. SMMP can issue four scalar instructions from two threads each cycle or four vector/matrix operations from one thread, where the execution of vector/matrix instructions in threads is done in round-robin fashion. Moreover, this paper presents the implementation of our proposed SMMP using VHDL targeting FPGA Virtex-6. In addition, the performance of SMMP is evaluated on some kernels from the basic linear algebra subprograms (BLAS). Our results show that, the hardware complexity of SMMP is 5.68 times higher than the baseline scalar processor. However, speedups of 4.9, 6.09, 6.98, 8.2, 8.25, 8.72, 9.36, 11.84 and 21.57 are achieved on BLAS kernels of applying Givens rotation, scalar times vector plus another, vector addition, vector scaling, setting up Givens rotation, dot-product, matrix–vector multiplication, Euclidean length, and matrix–matrix multiplications, respectively. The average speedup over the baseline is 9.55 and the average speedup over complexity is 1.68. Comparing with Xilinx MicroBlaze, the complexity of SMMP is 6.36 times higher, however, its speedup ranges from 6.87 to 12.07 on vector/matrix kernels, which is 9.46 in average.

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Vishnekov, A. V., and E. M. Ivanova. "Simulation of the Super-scalar Processor Core Operation." Journal of Physics: Conference Series 1163 (February 2019): 012010. http://dx.doi.org/10.1088/1742-6596/1163/1/012010.

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Bassoy, Cem Savas, Svetlana Torgasin, Mei Yang, and Karl-Heinz Zimmermann. "Accelerating Scalar-Product Based Sequence Alignment using Graphics Processor Units." Journal of Signal Processing Systems 61, no. 2 (October 8, 2009): 117–25. http://dx.doi.org/10.1007/s11265-009-0409-5.

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SOLIMAN, MOSTAFA I., and ABDULMAJID F. Al-JUNAID. "SYSTEMC IMPLEMENTATION AND PERFORMANCE EVALUATION OF A DECOUPLED GENERAL-PURPOSE MATRIX PROCESSOR." Parallel Processing Letters 20, no. 02 (June 2010): 103–21. http://dx.doi.org/10.1142/s0129626410000090.

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Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation and performance evaluation of a matrix processor called Mat-Core with SystemC (system level modeling language). Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix unit. To hide memory latency, the extended matrix unit is decoupled into two components: address generation and data computation, which communicate through data queues. Like vector architectures, the data computation unit is organized in parallel lanes. However, on parallel lanes, Mat-Core can execute matrix-scalar, matrix-vector, and matrix-matrix instructions in addition to vector-scalar and vector-vector instructions. For controlling the execution of vector/matrix instructions on the matrix core, this paper extends the well known scoreboard technique. Furthermore, the performance of Mat-Core is evaluated on vector and matrix kernels. Our results show that the performance of four lanes Mat-Core with matrix registers of size 4 × 4 or 16 elements each, queues size of 10, start up time of 6 clock cycles, and memory latency of 10 clock cycles is about 0.94, 1.3, 2.3, 1.6, 2.3, and 5.5 FLOPs per clock cycle; achieved on scalar-vector multiplication, SAXPY, Givens, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication, respectively.

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Pelleh, Moshe. "Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor." Issues in Informing Science and Information Technology 6 (2009): 837–44. http://dx.doi.org/10.28945/1102.

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Park, Dong-won, Nam Su Chang, Sangyub Lee, and Seokhie Hong. "Fast Implementation of NIST P-256 Elliptic Curve Cryptography on 8-Bit AVR Processor." Applied Sciences 10, no. 24 (December 9, 2020): 8816. http://dx.doi.org/10.3390/app10248816.

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In this paper, we present a highly optimized implementation of elliptic curve cryptography (ECC) over NIST P-256 curve for an 8-bit AVR microcontroller. For improving the performance of ECC implementation, we focus on optimizing field arithmetics. In particular, we optimize the modular multiplication and squaring method exploiting the state-of-the-art optimization technique, namely range shifted representation (RSR). With optimized field arithmetics, we significantly improve the performance of scalar multiplication and set the speed record for execution time of variable base scalar multiplication over NIST P-256 curve. When compared with previous works, we achieve a performance gain of 17.3% over the best previous result on the same platform. Moreover, the execution time of our result is even faster than that over the NIST P-192 curve of the well-known TinyECC library. Our result shows that RSR can be applied to all field arithmetics and evaluate the impact of the adoption of RSR over the performance of scalar multiplication. Additionally, our implementation provides a high degree of regularity to withstand side-channel attacks.

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Huang, Wen Tzeng, Ching Kuo Wang, Guo Ming Sung, and Chiu Ching Tuan. "Design and Implementation of a Low-Cost Scalar Multiplier-on-Chip for Elliptic Curve Cryptosystem." Applied Mechanics and Materials 284-287 (January 2013): 3395–400. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.3395.

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In the ECC, scalar multiplication represents the core operation of the system. In recent years, the circuit architecture of triple processor cores or greater has been addressed in the domestic and international literature. A parallel processing concept is mainly used in this type of framework to accelerate circuit operation. In the present study, equation calculation and circuit design were employed to integrate the pipeline architecture and the parallel processing architecture and further propose an elliptic curve scalar multiplier for dual processor cores. In addition, a Xilinx XC5VLX110T FPGA was used to verify the accuracy and performance of circuit functions. The maximum frequency was 173 MHz, the number of LUTs was 14999 slices, and the time to accomplishing one scalar multiplication was only 8.8s. Compared to architectures described in recent reports, the architecture presented was faster and effectively reduced the square measure by 28%.

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SOLIMAN, MOSTAFA I., and STANISLAV G. SEDUKHIN. "PERFORMANCE EVALUATION OF BLAS ON THE TRIDENT PROCESSOR." Parallel Processing Letters 15, no. 04 (December 2005): 407–14. http://dx.doi.org/10.1142/s0129626405002325.

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Different subtasks of an application usually have different computational, memory, and I/O requirements that result in different needs for computer capabilities. Thus, the more appropriate approach for both high performance and simple programming model is designing a processor having multi-level instruction set architecture (ISA). This leads to high performance and minimum executable code size. Since the fundamental data structures for a wide variety of existing applications are scalar, vector, and matrix, our research Trident processor has three-level ISA executed on zero-, one-, and two-dimensional arrays of data. These levels are used to express a great amount of fine-grain data parallelism to a processor instead of the dynamical extraction by a complicated logic or statically with compilers. This reduces the design complexity and provides high-level programming interface to hardware. In this paper, the performance of Trident processor is evaluated on BLAS, which represent the kernel operations of many data parallel applications. We show that Trident processor proportionally reduces the number of clock cycles per floating-point operation by increasing the number of execution datapaths.

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., Rekha Halkatti. "FPGA BASED 128-BIT CUSTOMISED VLIW PROCESSOR FOR EXECUTING DUAL SCALAR/VECTOR INSTRUCTIONS." International Journal of Research in Engineering and Technology 03, no. 15 (May 25, 2014): 933–36. http://dx.doi.org/10.15623/ijret.2014.0315176.

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Gupta, Nitin, and Jitendra Kumar Nama. "An experimental investigation of scalar control-based induction motor drive using digital signal processor." International Journal of Power Electronics 10, no. 1/2 (2019): 102. http://dx.doi.org/10.1504/ijpelec.2019.096817.

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Gupta, Nitin, and Jitendra Kumar Nama. "An experimental investigation of scalar control-based induction motor drive using digital signal processor." International Journal of Power Electronics 10, no. 1/2 (2019): 102. http://dx.doi.org/10.1504/ijpelec.2019.10017312.

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LEE, BEN, and ALI R. HURSON. "A STRATEGY FOR SCHEDULING PARTIALLY ORDERED PROGRAM GRAPHS ONTO MULTICOMPUTERS." Parallel Processing Letters 05, no. 04 (December 1995): 575–86. http://dx.doi.org/10.1142/s0129626495000515.

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The issue of scalability is key to the success of massively parallel processing. Due to their distributed nature, message-passing multicomputers are appropriate for achieving scalar performance. However, the message-passing model lacks programmability due to difficulties encountered by the programmers to partition and schedule the computation over the processors and to establish efficient inter-processor communication in the user code. Therefore, this paper presents a compile-time scheduling heuristic, called BLS, that maps programs onto the processors of a message-passing multicomputer. In contrast to other methods proposed, BLS takes a more global approach in attempt to balance the tradeoff between exploiting parallelism and reducing communication overhead. To evaluate the effectiveness of BLS, simulation studies of scheduling SISAL programs are presented.

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ROSENBLUM, IRINA, JOAN ADLER, and SIMON BRANDON. "MULTI-PROCESSOR MOLECULAR DYNAMICS USING THE BRENNER POTENTIAL: PARALLELIZATION OF AN IMPLICIT MULTI-BODY POTENTIAL." International Journal of Modern Physics C 10, no. 01 (February 1999): 189–203. http://dx.doi.org/10.1142/s0129183199000139.

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We present computational aspects of Molecular Dynamics calculations of thermal properties of diamond using the Brenner potential. Parallelization was essential in order to carry out these calculations on samples of suitable sizes. Our implementation uses MPI on a multi-processor machine such as the IBM SP2. Three aspects of parallelization of the Brenner potential are discussed in depth. These are its long-range nature, the need for different parallelization algorithms for forces and neighbors, and the relative expense of force calculations compared to that of data communication. The efficiency of parallelization is presented as a function of different approaches to these issues as well as of cell size and number of processors employed in the calculation. In the calculations presented here, information from almost half of the atoms were needed by each processor even when 16 processors were used. This made it worthwhile to avoid unnecessary complications by making data from all atoms available to all processors. Superlinear speedup was achieved for four processors (by avoiding paging) with 512 atom samples, and 5ps long trajectories were calculated (for 5120 atom samples) in 53 hours using 16 processors; 514 hours would have been needed to complete this calculation using a serial program. Finally, we discuss and make available a set of routines that enable MPI-based codes such as ours to be debugged on scalar machines.

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Bellemou, A., N. Benblidia, M. Anane, and M. Issad. "MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950037. http://dx.doi.org/10.1142/s0218126619500373.

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In this paper, we present Microblaze-based parallel architectures of Elliptic Curve Scalar Multiplication (ECSM) computation for embedded Elliptic Curve Cryptosystem (ECC) on Xilinx FPGA. The proposed implementations support arbitrary Elliptic Curve (EC) forms defined over large prime field ([Formula: see text]) with different security-level sizes. ECSM is performed using Montgomery Power Ladder (MPL) algorithm in Chudnovsky projective coordinates system. At the low abstraction level, Montgomery Modular Multiplication (MMM) is considered as the critical operation. It is implemented within a hardware Accelerator MMM (AccMMM) core based on the modified high radix, [Formula: see text] MMM algorithm. The efficiency of our parallel implementations is achieved by the combination of the mixed SW/HW approach with Multi Processor System on Programmable Chip (MPSoPC) design. The integration of multi MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the exploitation of the parallelism in ECSM computation with several degrees. The Virtex-5 parallel implementations of 256-bit and 521-bis ECSM computations run at 100[Formula: see text]MHZ frequency and consume between 2,739 and 6,533 slices, 22 and 72 RAMs and between 16 and 48 DSP48E cores. For the considered security-level sizes, the delays to perform single ECSM are between 115[Formula: see text]ms and 14.72[Formula: see text]ms.

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Kohrangi, Mohsen, Paolo Bazzurro, and Dimitrios Vamvatsikos. "Vector and Scalar IMs in Structural Response Estimation, Part I: Hazard Analysis." Earthquake Spectra 32, no. 3 (August 2016): 1507–24. http://dx.doi.org/10.1193/053115eqs080m.

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A realistic assessment of building economic losses and collapse induced by earthquakes requires the monitoring of several response measures, both story-specific and global. The prediction of such response measures benefits from using multiple ground motion intensity measures (IMs) that are, in general, correlated. To allow the inclusion of multiple IMs in the risk assessment process, it is necessary to have a practical tool that computes the vector-valued hazard of all such IMs at the building site. In this paper, vector-valued probabilistic seismic hazard analysis (VPSHA) is implemented here as a post-processor to scalar PSHA results. A group of candidate scalar and vector IMs based on spectral acceleration values, ratios of spectral acceleration values, and spectral accelerations averaged over a period range are defined and their hazard evaluated. These IMs are used as structural response predictors of three-dimensional (3-D) models of reinforced concrete buildings described in a companion paper ( Kohrangi et al. 2016 ).

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Jungeblut, T., C. Puttmann, R. Dreesen, M. Porrmann, M. Thies, U. Rückert, and U. Kastens. "Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography." Advances in Radio Science 8 (December 22, 2010): 295–305. http://dx.doi.org/10.5194/ars-8-295-2010.

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Abstract. The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

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Scutariu, Adrian, Dalina Zedevei, and Mariana Jurian. "Teacher - Student Graphical User Interface For Testing And Comparing The Performance Of Adaptive Algorithms Used In Smart Antenna Networks." Balkan Region Conference on Engineering and Business Education 1, no. 1 (August 15, 2014): 537–42. http://dx.doi.org/10.2478/cplbu-2014-0093.

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AbstractSmart antenna networks are receiving a lot of interest in these days, as new advanced and fast processors are being developed. Capable of pointing the main beam in a certain desired direction and create nulls in the radiation pattern in the direction of interference, smart antenna networks are a good solution in a bandwidth limited environment as the number of users continuously grow. This technique is called beamforming. For many years smart antennas were not practical as they involve the use of a processor that runs an adaptive algorithm. Slow processors meant low speed of convergence and a slow adaptation. There are a lot of adaptive algorithms that can fur fill the job that a smart antenna system has to accomplish. The main purpose of this paper is however to present the main advantages of creating a MATLAB GUI (Graphical User Interface) in order to study these algorithms. The GUI described studies 62 adaptive algorithms, some described in literature, some propose by the authors. We will make a short description of the LMS (Least Mean Squares Algorithm), the APA (Affine Projection Algorithm) and the GASSAPA (Gradient Adaptive Scalar Step Size Affine Projection Algorithm) and compare them with the use of the graphical interface.

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Abdul-Hadi, Alaa Mohammed, Yousraa Abdul-sahib Saif-aldeen, and Firas Ghanim Tawfeeq. "Performance Evaluation of Scalar Multiplication in Elliptic Curve Cryptography Implementation using Different Multipliers Over Binary Field GF (2233)." Journal of Engineering 26, no. 9 (September 1, 2020): 45–64. http://dx.doi.org/10.31026/j.eng.2020.09.04.

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This paper presents a point multiplication processor over the binary field GF (2233) with internal registers integrated within the point-addition architecture to enhance the Performance Index (PI) of scalar multiplication. The proposed design uses one of two types of finite field multipliers, either the Montgomery multiplier or the interleaved multiplier supported by the additional layer of internal registers. Lopez Dahab coordinates are used for the computation of point multiplication on Koblitz Curve (K-233bit). In contrast, the metric used for comparison of the implementations of the design on different types of FPGA platforms is the Performance Index. The first approach attains a performance index of approximately 0.217610202 when its realization is over Virtex-6 (6vlx130tff1156-3). It uses an interleaved multiplier with 3077 register slices, 4064 lookup tables (LUTs), 2837 flip-flops (FFs) at a maximum frequency of 221.6Mhz. This makes it more suitable for high-frequency applications. The second approach, which uses the Montgomery multiplier, produces a PI of approximately 0.2228157 when its implementation is on Virtex-4 (6vlx130tff1156-3). This approach utilizes 3543 slices, 2985 LUTs, 3691 FFs at a maximum frequency of 190.47MHz. Thus, it is found that the implementation of the second approach on Virtex-4 is more suitable for applications with a low frequency of about 86.4Mhz and a total number of slices of about 12305.

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Gong, Hai Jun, Xin Zhong Li, Xue Yi Fan, Da Ming Xu, and Jing Jie Guo. "Data-Conversion and Displaying for Numerical Simulation of EMCC with FEM-FVM-Joint Method." Advanced Materials Research 418-420 (December 2011): 563–66. http://dx.doi.org/10.4028/www.scientific.net/amr.418-420.563.

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Abstract. For efficiently performing the numerical simulation of electromagnetic continues casting (EMCC) with finite element method (FEM) and finite volume method (FVM) combined scheme, a program integrates with data-format conversion and post-processing was proposed. The conversion of data format realized by linear interpolating, and the post processor developed on a Visual Fortran 6.6A platform using Fortran-95 language and the QuickWin module. Both 2-D and 3-D EM-FEM data calculated by a general-purpose FEM software, ANSYS, could be converted into FVM-data format using this program, and all FVM-data whether scalar quantities or vector ones could be displayed in the manners of cabinet drawing and normal axonometric drawing, which promises the correctness for data format conversion process of FEM/FVM-joint and the convenient analysis of transport phenomena during EMCC numerical simulation. The results of transport simulations and data format conversions indicate that the format-conversion method as well as the post processing is effective and convenient in numerical simulation with FEM/FVM-joint under various EM fields.

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Anderson, Jeffrey L., and Nancy Collins. "Scalable Implementations of Ensemble Filter Algorithms for Data Assimilation." Journal of Atmospheric and Oceanic Technology 24, no. 8 (August 1, 2007): 1452–63. http://dx.doi.org/10.1175/jtech2049.1.

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Abstract A variant of a least squares ensemble (Kalman) filter that is suitable for implementation on parallel architectures is presented. This parallel ensemble filter produces results that are identical to those from sequential algorithms already described in the literature when forward observation operators that relate the model state vector to the expected value of observations are linear (although actual results may differ due to floating point arithmetic round-off error). For nonlinear forward observation operators, the sequential and parallel algorithms solve different linear approximations to the full problem but produce qualitatively similar results. The parallel algorithm can be implemented to produce identical answers with the state variable prior ensembles arbitrarily partitioned onto a set of processors for the assimilation step (no caveat on round-off is needed for this result). Example implementations of the parallel algorithm are described for environments with low (high) communication latency and cost. Hybrids of these implementations and the traditional sequential ensemble filter can be designed to optimize performance for a variety of parallel computing environments. For large models on machines with good communications, it is possible to implement the parallel algorithm to scale efficiently to thousands of processors while bit-wise reproducing the results from a single processor implementation. Timing results on several Linux clusters are presented from an implementation appropriate for machines with low-latency communication. Most ensemble Kalman filter variants that have appeared in the literature differ only in the details of how a prior ensemble estimate of a scalar observation is updated given an observed value and the observational error distribution. These details do not impact other parts of either the sequential or parallel filter algorithms here, so a variety of ensemble filters including ensemble square root and perturbed observations filters can be used with all the implementations described.

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Fukushima, Toshio. "Parallel/Vector Integration Methods for Dynamical Astronomy." International Astronomical Union Colloquium 172 (1999): 231–41. http://dx.doi.org/10.1017/s0252921100072584.

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AbstractThis paper reviews three recent works on the numerical methods to integrate ordinary differential equations (ODE), which are specially designed for parallel, vector, and/or multi-processor-unit (PU) computers. The first is the Picard-Chebyshev method (Fukushima, 1997a). It obtains a global solution of ODE in the form of Chebyshev polynomial of large (> 1000) degree by applying the Picard iteration repeatedly. The iteration converges for smooth problems and/or perturbed dynamics. The method runs around 100-1000 times faster in the vector mode than in the scalar mode of a certain computer with vector processors (Fukushima, 1997b). The second is a parallelization of a symplectic integrator (Saha et al., 1997). It regards the implicit midpoint rules covering thousands of timesteps as large-scale nonlinear equations and solves them by the fixed-point iteration. The method is applicable to Hamiltonian systems and is expected to lead an acceleration factor of around 50 in parallel computers with more than 1000 PUs. The last is a parallelization of the extrapolation method (Ito and Fukushima, 1997). It performs trial integrations in parallel. Also the trial integrations are further accelerated by balancing computational load among PUs by the technique of folding. The method is all-purpose and achieves an acceleration factor of around 3.5 by using several PUs. Finally, we give a perspective on the parallelization of some implicit integrators which require multiple corrections in solving implicit formulas like the implicit Hermitian integrators (Makino and Aarseth, 1992), (Hut et al., 1995) or the implicit symmetric multistep methods (Fukushima, 1998), (Fukushima, 1999).

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Patra, Prashanta Kumar, and Padma Lochan Pradhan. "An Integrated Dynamic Model Optimizing the Risk on Real Time Operating System." International Journal of Information Security and Privacy 8, no. 1 (January 2014): 38–61. http://dx.doi.org/10.4018/ijisp.2014010103.

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This article provide maximum preventive control, high performance and fault tolerance at an optimal resources, cost, time with high availability and quality of services to be invested into dynamic security mechanisms deciding on the measure component of real time operating system resources (Shell, File, Memory, Processor, Kernel, Encryption key, I/O devices). The authors have to define, design, develop and deploy our valuable idea to be optimizing the technology, resource, cost and maximize the throughput, productivity of business all together at anytime and anywhere in around the globe by applying this integrated dynamic model. This dynamic model interfacing, integrating, communicating, synchroning, preventing and optimize step by step through real time algebraic method over a RTOS on distributed super scalar environment (MIMD). This proposed dynamic algebraic model would be preventing the data and services on RTOS from uncertainty, unorder, unsetup, unsafe and external hackers. Mean while this model would be identifying vulnerabilities and threats on operating system resources to achieving the highest business objectives by utilizing the efficient and reliable resources management. The authors have to optimized the system attacks and down time by verification and validation of this method on complex heterogonous infrastructure.

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Levesque, John M. "Reservoir Simulation on Supercomputers." Society of Petroleum Engineers Journal 25, no. 02 (April 1, 1985): 275–79. http://dx.doi.org/10.2118/10520-pa.

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Abstract Several important excerpts from reservoir models have been tested on the Cray-1 and Cyber 205. The timings of these kernels are examined and explained by analyzing the architectural differences of the two machines. Interesting conclusions as to the strengths and weaknesses of the two machines are drawn. Introduction In the past 2 years, the Cray-1 has asserted itself in the petroleum industry as an extremely valuable tool for petroleum industry as an extremely valuable tool for reservoir simulation and geophysical data analysis. Recent analysis of the capabilities of the Cyber 205 indicates that it also has the potential of being a very valuable tool in these areas. The intent of this paper is to analyze the differences of these two machines in light of several important computational kernels. A few architectural differences between the Cyber 205 and the Cray-1 are examined and discussion follows on how these differences show up in the actual timings of the kernels. Comparison of Architectures Both the Cray-1 and the Cyber 205 are vector processors--i.e., they obtain high performance rates from processors--i.e., they obtain high performance rates from segmented functional units, which enables them to overlap multiple operations and consequently produce one or more floating point results per click cycle. The largest difference between the two machines is that the Cyber 205 is a memory-to-memory vector processor, while the Cray-1 is a register-to-register vector processor. Figs. 1 and 2 illustrate this difference. The Cyber 205 processor. Figs. 1 and 2 illustrate this difference. The Cyber 205 actually picks up operands directly from memory and deposits them back into memory, whereas the Cray-1 prefetches its operands into vector registers of length 64, prefetches its operands into vector registers of length 64, performs calculation from register to register, and then performs calculation from register to register, and then stores the contents of the result register back into memory. This difference in the architecture is solely responsible for the major difference in performance between the two machines. A consequence of the memory-to-memory architecture is that the Cyber 205 must perform all vector operations on contiguous memory locations (but is able to get very high memory bandwidths), whereas the Cray-1, having a separate functional unit to memory, can access memory locations with a constant nonunitary stride at the same speed as a stride of one. Timing Formulas These differences show up in the formulas used to estimate the timing of each machine. Formulas are given to estimate the timing of a dyadic operation on the Cyber 205 and Cray-1. (All timings are for 64-bit operations on a two-pipe Cyber 205). Operation: X(*)=Y(*)*Z(*). Cyber 205 (clock cycle of 205 is 20 nanoseconds): + (51 + N/2)*(20 nanoseconds) * (52 + N/2)*(20 nanoseconds) / (80 + N/0.28)*(20 nanoseconds) Cray-1 (clock cycle of Cray-1 is 12.5 nanoseconds): + (33*(INT(N/64) + 1) + 3N)*(12.5 nanoseconds) * (34*(INT(N/64) + 1) + 3N)*(12.5 nanoseconds) / (53*(INT(N/64) + 1) + 4N)*(12.5 nanoseconds) For a dyad where one operand is a scalar, the Cray-1 has improved timings of: + (10 + (26*(INT(N/64) + 1) + 2N)*(12.5 nanoseconds) * (10 + (27*(INT(N/64) + 1) + 2N)*(11.4 nanoseconds) / (10 + (44*(INT(N/64) + 1) + 4N)*(11.4 nanoseconds) (S/Z(*)) For a triad operation where the operations are different, such as: Operation: X(*)=Y(*)+Z(*)*T(*) Cyber 205: (103 + N)*(20.0 nanoseconds) Cray-1: (44*(INT(N/64) + 1) + 4N)*(12.5 nanoseconds) Both machines obtain an improvement if any of the three input operations is a scalar. Cyber 205: (103 + N/2) * (20 nanoseconds) Cray-1: (10+(37*(INT(N/64) + 1) + 3N))*(12.5 nanoseconds) The interesting point shown by this analysis is that the Cray-1 has an advantage for short vectors (because of shorter startup time), whereas the Cyber 205 has a high production rate and therefore outperforms the Cray for production rate and therefore outperforms the Cray for larger vectors. Strides greater than one, as in the following DO loop, are encountered often, and these present a problem for the Cyber 205. DO 10 I= 1, M.N X(I)=X(I)+S*Z(I) 10 CONTINUE The Cray-1 has no increase in execution time since its memory functional unit accesses memory at the same rate regardless of the magnitude of the stride. SPEJ P. 275

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Morales-Sandoval, Miguel, Luis Armando Rodriguez Flores, Rene Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, and Ignacio Algredo. "A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks." Journal of Sensors 2021 (January 6, 2021): 1–13. http://dx.doi.org/10.1155/2021/8860413.

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The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyped hardware accelerator for scalar multiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of robust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the proposed hardware design is achieved by implementing a novel digit-by-digit computing approach applied at the finite field and curve level algorithms, in addition to hardware reusing, the use of embedded memory blocks in modern FPGAs, and a simpler control logic. Our hardware design targets elliptic curves defined over binary fields generated by trinomials, uses fewer area resources than other FPGA approaches, and is faster than software counterparts. Our ECC hardware accelerator was validated under a hardware/software codesign of the Diffie-Hellman key exchange protocol (ECDH) deployed in the IoT MicroZed FPGA board. For a scalar multiplication in the sect233 curve, our design requires 1170 FPGA slices and completes the computation in 128820 clock cycles (at 135.31 MHz), with an efficiency of 0.209 kbps/slice. In the codesign, the ECDH protocol is executed in 4.1 ms, 17 times faster than a MIRACL software implementation running on the embedded processor Cortex A9 in the MicroZed. The FPGA-based accelerator for binary ECC presented in this work is the one with the least amount of hardware resources compared to other FPGA designs in the literature.

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Trelewicz, J. Q., J. L. Mitchell, and M. T. Brady. "Vectorized transforms in scalar processors." IEEE Signal Processing Magazine 19, no. 4 (July 2002): 22–31. http://dx.doi.org/10.1109/msp.2002.1012347.

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Bellemou, Ahmed Mohamed, Antonio García, Encarnación Castillo, Nadjia Benblidia, Mohamed Anane, José Antonio Álvarez-Bermejo, and Luis Parrilla. "Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators." Electronics 8, no. 11 (October 30, 2019): 1238. http://dx.doi.org/10.3390/electronics8111238.

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Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem. The integration of the ARM processor enables to exploit the possibility of embedded Linux features for high system flexibility. As a result, the proposed ECC accelerator requires limited area, with only 3395 LUTs on the Zynq device used to perform high-speed, 233-bit ECSMs in 413 µs, with a 50 MHz clock. Moreover, the generation of a 384-bit TLS handshake secret key between client and server coordinators requires 67.5 ms on a low cost Zynq 7Z007S device.

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Fu, John W. C., Janak H. Patel, and Bob L. Janssens. "Stride directed prefetching in scalar processors." ACM SIGMICRO Newsletter 23, no. 1-2 (December 10, 1992): 102–10. http://dx.doi.org/10.1145/144965.145006.

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Agarwal, Ramesh C. "A super scalar sort algorithm for RISC processors." ACM SIGMOD Record 25, no. 2 (June 1996): 240–46. http://dx.doi.org/10.1145/235968.233336.

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Page, G. J. "Rapid, parallel CFD grid generation using octrees." Aeronautical Journal 117, no. 1188 (February 2013): 133–46. http://dx.doi.org/10.1017/s0001924000007910.

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Abstract As Large Eddy Simulation is increasingly applied to flows containing complex geometry, grid generation becomes difficult and time consuming when using software originally developed for RANS flow solvers. The traditional ‘pipeline’ approach of grid generation → solve → visualise entails the time consuming transfer of large files and conversion of file formats. This work demonstrates a grid generation methodology developed specifically to be integrated with parallel LES. The current approach is to use a Cartesian grid with adaptive refinement based upon geometry intersection, surface detail and surface curvature. The grid is defined by an octree data structure with the geometry defined by triangular facets using the STL file format. The result is a set of ‘cubical’ subdomains, each with identical numbers of cells and uniform distributions within the cube. Some subdomains will be entirely fluid and can be solved using straightforward CFD techniques, whilst some cubes will be cut by the surfaces. Individual cells are then tagged as ‘solid’, ‘fluid’ or ‘cut’ with the solver expected to use an immersed boundary approach to model the surface. A key feature is the design of the algorithm to be parallelisable on both shared and distributed memory systems. The distributed memory parallel dynamically partitions the grid as it is being generated, so that the partitioning is suitable for a subsequent flow solver. Grid generation testing has been carried out on a variety of input CAD files ranging up to 350,000 facets. A landing gear case shows how the grid generator correctly finds the fluid inside of the tire and other cavities within the hub. In scalar mode, a grid with 4,916 cubes and 468 million cells is generated in less than 100 seconds, whilst in parallel on 32 processor cores this can be achieved in 4·6 seconds.

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Удовиченко, С. Ю., А. Д. Писарев, А. Н. Бусыгин, and А. Н. Бобылев. "Биоморфный нейропроцессор – прототип компьютера нового поколения, являющегося носителем искусственного интеллекта. Часть 2." Nanoindustry Russia 14, no. 1 (March 5, 2021): 68–79. http://dx.doi.org/10.22184/1993-8578.2021.14.1.68.79.

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Во входном и выходном устройствах биоморфного нейропроцессора происходят первичная и конечная обработка информации. Представлены результаты по сжатию на входе цифровой информации и ее кодированию в импульсы, а также по декодированию информации об активации нейронов на выходе в цифровой двоичный код. Представлена реализация аппаратной нейросети процессора на основе оригинальной биоморфной электрической модели нейрона. Приведены результаты SPICE-моделирования и экспериментального исследования процессов обработки сигналов в режимах маршрутизации выходных импульсов нейронов на синапсы других нейронов в логической матрице, скалярного умножения матрицы чисел на вектор, а также ассоциативного самообучения в запоминающей матрице. Впервые продемонстрирована генерация новой ассоциации (нового знания) как в компьютерном моделировании, так и в изготовленном мемристорно-диодном кроссбаре, в отличие от самообучения в существующих аппаратных нейросетях с синапсами на базе дискретных мемристоров. Primary and ultimate information processing takes place in the input and output devices of the biomorphic neuroprocessor. The results are presented on the compression of digital information at the input and its coding into pulses, as well as on the decoding of information about the activation of neurons at the output into a digital binary code. An implementation of a hardware neural network of a processor based on an original biomorphic electrical model of a neuron is presented. The results of SPICE modeling and experimental research of signal processing processes in the modes of routing neuron output pulses to synapses of other neurons in a logical matrix, scalar multiplication of a matrix of numbers by a vector, and associative selflearning in a memory matrix are presented. For the first time, the generation of a new association (new knowledge) was demonstrated both in computer simulation and in a fabricated memristor-diode crossbar, in contrast to self-learning in existing hardware neural networks with synapses based on discrete memristors.

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Oh, N., P. P. Shirvani, and E. J. McCluskey. "Error detection by duplicated instructions in super-scalar processors." IEEE Transactions on Reliability 51, no. 1 (March 2002): 63–75. http://dx.doi.org/10.1109/24.994913.

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Soga, Takashi, Akihiro Musa, Koki Okabe, Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi, Shun Takahashi, Daisuke Sasaki, and Kazuhiro Nakahashi. "Performance of SOR methods on modern vector and scalar processors." Computers & Fluids 45, no. 1 (June 2011): 215–21. http://dx.doi.org/10.1016/j.compfluid.2010.12.024.

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Wang, G. H., and N. T. Clemens. "Effects of imaging system blur on measurements of flow scalars and scalar gradients." Experiments in Fluids 37, no. 2 (May 11, 2004): 194–205. http://dx.doi.org/10.1007/s00348-004-0801-7.

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Bottcher, Axel. "A visualization environment for super scalar machines." Facta universitatis - series: Electronics and Energetics 17, no. 2 (2004): 199–208. http://dx.doi.org/10.2298/fuee0402199b.

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In this paper, we introduce an environment to visualize the internal activities of super scalar processors. This seems currently to be the dominating class of processors on the market. A programmer or a compiler can produce optimized code only with a thorough understanding of the internal structures. This usefulness of this environment is then demonstrated for two aspects of program optimization: loop unrolling in situations with cold or perfectly warmed cache and instruction ordering. We use matrix multiplication as representative example to reflect signal processing code.

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Mühlbauer, Felix, Lukas Schröder, and Mario Schölzel. "Handling of transient and permanent faults in dynamically scheduled super-scalar processors." Microelectronics Reliability 80 (January 2018): 176–83. http://dx.doi.org/10.1016/j.microrel.2017.11.021.

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Javeed, Khalid, and Xiaojun Wang. "FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture." International Journal of Reconfigurable Computing 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/6371403.

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The higher computational complexity of an elliptic curve scalar point multiplication operation limits its implementation on general purpose processors. Dedicated hardware architectures are essential to reduce the computational time, which results in a substantial increase in the performance of associated cryptographic protocols. This paper presents a unified architecture to compute modular addition, subtraction, and multiplication operations over a finite field of large prime characteristicGF(p). Subsequently, dual instances of the unified architecture are utilized in the design of high speed elliptic curve scalar multiplier architecture. The proposed architecture is synthesized and implemented on several different Xilinx FPGA platforms for different field sizes. The proposed design computes a 192-bit elliptic curve scalar multiplication in 2.3 ms on Virtex-4 FPGA platform. It is 34%faster and requires 40%fewer clock cycles for elliptic curve scalar multiplication and consumes considerable fewer FPGA slices as compared to the other existing designs. The proposed design is also resistant to the timing and simple power analysis (SPA) attacks; therefore it is a good choice in the construction of fast and secure elliptic curve based cryptographic protocols.

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Hofmann, Johannes, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, and Gerhard Wellein. "Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors." Concurrency and Computation: Practice and Experience 29, no. 9 (August 3, 2016): e3921. http://dx.doi.org/10.1002/cpe.3921.

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Nicolaou, Georgios, George Livadiotis, and Mihir I. Desai. "Estimating the Polytropic Indices of Plasmas with Partial Temperature Tensor Measurements: Application to Solar Wind Protons at ~1 au." Applied Sciences 11, no. 9 (April 28, 2021): 4019. http://dx.doi.org/10.3390/app11094019.

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We examine the relationships between temperature tensor elements and their connection to the polytropic equation, which describes the relationship between the plasma scalar temperature and density. We investigate the possibility to determine the plasma polytropic index by fitting the fluctuations of temperature either perpendicular or parallel to the magnetic field. Such an application is particularly useful when the full temperature tensor is not available from the observations. We use solar wind proton observations at ~1 au to calculate the correlations between the temperature tensor elements and the scalar temperature. Our analysis also derives the polytropic equation in selected streamlines of solar wind plasma proton observations that exhibit temperature anisotropies related to stream-interaction regions. We compare the polytropic indices derived by fitting fluctuations of the scalar, perpendicular, and parallel temperatures, respectively. We show that the use of the parallel or perpendicular temperature, instead of the scalar temperature, still accurately derives the true, average polytropic index value, but only for a certain level of temperature anisotropy variability within the analyzed streamlines. The use of the perpendicular temperature leads to more accurate calculations, because its correlation with the scalar temperature is less affected by the anisotropy fluctuations.

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Cui, Chao, Yun Zhao, Yong Xiao, Weibin Lin, and Di Xu. "A Hardware-Efficient Elliptic Curve Cryptographic Architecture over GF (p)." Mathematical Problems in Engineering 2021 (May 18, 2021): 1–7. http://dx.doi.org/10.1155/2021/8883614.

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This paper proposes a hardware-efficient elliptic curve cryptography (ECC) architecture over GF(p), which uses adders to achieve scalar multiplication (SM) through hardware-reuse method. In terms of algorithm, the improvement of the interleaved modular multiplication (IMM) algorithm and the binary modular inverse (BMI) algorithm needs two adders. In addition to the adder, the data register is another optimize target. The design compiler is synthesized on 0.13 µm CMOS ASIC platform. The time range of performing scalar multiplication over 160, 192, 224, and 256 field orders under 150 MHz frequency is 1.99–3.17 ms. Moreover, the gate area required for different field orders in this design is in the range of 35.65k–59.14k, with 50%–91% hardware resource less than other processors.

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Bai, Yingying, Zhiyu Zhang, Ruoqiu Wang, Tianbao Chen, Xu Wang, and Xuejun Zhang. "Imperfections of Scalar Approximation in Calibration of Computer-Generated Holograms for Optical Surface Measurements." Applied Sciences 11, no. 15 (July 27, 2021): 6897. http://dx.doi.org/10.3390/app11156897.

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Computer-generated hologram (CGH) null correctors are used as accuracy standards for interferometric measurements of optical surfaces and optical systems. Diffractive optics calibrators (DOCs) have been developed to evaluate the phase tolerance of CGHs based on scalar approximation by measuring variations in duty cycle and etching depth. However, if the grating period of a CGH < 5λ, the scalar approximation is not accurate for phase analysis and reconstruction. In this study, the measurement errors of DOCs with small-period CGHs were investigated and experimentally verified. Results show that the imperfections of scalar approximation in CGHs cannot be ignored and the development of rigorous evaluation methods to improve the measurement accuracy of CGHs is of great practical significance.

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Pozorski, Jacek, Marta Wacławczyk, and Jean-Pierre Minier. "Scalar and joint velocity–scalar PDF modelling of near-wall turbulent heat transfer." International Journal of Heat and Fluid Flow 25, no. 5 (October 2004): 884–95. http://dx.doi.org/10.1016/j.ijheatfluidflow.2004.04.004.

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Jogi, Bhushan S., Lekrajsing R. Gour, and Nikhil Turkar. "Process Improvement Using Statistical Process Control in a Small Scale Industry." International Journal of Trend in Scientific Research and Development Volume-2, Issue-5 (August 31, 2018): 1885–92. http://dx.doi.org/10.31142/ijtsrd17144.

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Li, Xingran, Wei Yu, and Bao Li. "Parallel and Regular Algorithm of Elliptic Curve Scalar Multiplication over Binary Fields." Security and Communication Networks 2020 (June 24, 2020): 1–10. http://dx.doi.org/10.1155/2020/4087873.

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Accelerating scalar multiplication has always been a significant topic when people talk about the elliptic curve cryptosystem. Many approaches have been come up with to achieve this aim. An interesting perspective is that computers nowadays usually have multicore processors which could be used to do cryptographic computations in parallel style. Inspired by this idea, we present a new parallel and efficient algorithm to speed up scalar multiplication. First, we introduce a new regular halve-and-add method which is very efficient by utilizing λ projective coordinate. Then, we compare many different algorithms calculating double-and-add and halve-and-add. Finally, we combine the best double-and-add and halve-and-add methods to get a new faster parallel algorithm which costs around 12.0% less than the previous best. Furthermore, our algorithm is regular without any dummy operations, so it naturally provides protection against simple side-channel attacks.

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Kiørboe, Thomas. "Formation and fate of marine snow: small-scale processes with large- scale implications." Scientia Marina 65, S2 (December 30, 2001): 57–71. http://dx.doi.org/10.3989/scimar.2001.65s257.

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Vanormelingen, J., and E. Van den Bulck. "Scalar transport in plane mixing layers." Heat and Mass Transfer 35, no. 5 (October 21, 1999): 383–90. http://dx.doi.org/10.1007/s002310050340.

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Bar Kutiel, Pua, and Michael Dorman. "The Importance of Annual Plants and Multi-Scalar Analysis for Understanding Coastal Dune Stabilization Process in the Mediterranean." Applied Sciences 11, no. 6 (March 22, 2021): 2821. http://dx.doi.org/10.3390/app11062821.

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Since ecological phenomena and patterns vary with scale, scalar analysis is a developing practice in ecology. Scalar analysis is most valuable in heterogeneous environments, since habitat heterogeneity is a key factor in determining biodiversity. One such case can be seen in the changes in annual vegetation in coastal sand dune systems. Most studies in these environments are carried out at the dune scale, comparing dunes at different stabilization states. However, a broader understanding of dune stabilization processes requires analyses at the finer scales of dune slope aspects (directions of exposure to wind) and patches (under and between woody perennial species). Here, we present the results of a study that combines the three scales (dune, slope, and patch) in the Mediterranean coastal dune systems in Israel. Through this multi-scalar analysis, we are able to describe processes at the finer patch and aspect scale and explain how they shape patterns at the dune scale. The results indicate that the dune scale exposes the differences in annual plant characteristics between mobile and fixed dunes, their slopes and patches and the reorganization and spatial distribution of annual plants within mobile and fixed dunes during the stabilization process.

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Ghandhi, J. B. "Spatial resolution and noise considerations in determining scalar dissipation rate from passive scalar image data." Experiments in Fluids 40, no. 4 (January 10, 2006): 577–88. http://dx.doi.org/10.1007/s00348-005-0097-2.

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Palladino, Simone, Luca Esposito, Paolo Ferla, Renato Zona, and Vincenzo Minutolo. "Functionally Graded Plate Fracture Analysis Using the Field Boundary Element Method." Applied Sciences 11, no. 18 (September 12, 2021): 8465. http://dx.doi.org/10.3390/app11188465.

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This paper describes the Field Boundary Element Method (FBEM) applied to the fracture analysis of a 2D rectangular plate made of Functionally Graded Material (FGM) to calculate Mode I Stress Intensity Factor (SIF). The case study of this Field Boundary Element Method is the transversely isotropic plane plate. Its material presents an exponential variation of the elasticity tensor depending on a scalar function of position, i.e., the elastic tensor results from multiplying a scalar function by a constant taken as a reference. Several examples using a parametric representation of the structural response show the suitability of the method that constitutes a Stress Intensity Factor evaluation of Functionally Graded Materials plane plates even in the case of more complex geometries.

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Yuan, Mengyuan, Hengbin Zhang, and Chenning Tong. "Investigation of scalar–scalar-gradient filtered joint density function for large eddy simulation of turbulent combustion." Physics of Fluids 33, no. 3 (March 1, 2021): 035121. http://dx.doi.org/10.1063/5.0039025.

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Wang, Guanghua, and Robert S. Barlow. "Spatial resolution effects on the measurement of scalar variance and scalar gradient in turbulent nonpremixed jet flames." Experiments in Fluids 44, no. 4 (November 14, 2007): 633–45. http://dx.doi.org/10.1007/s00348-007-0423-y.

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Journal articles on the topic 'Scalar processor'

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