Relevant bibliographies by topics / Routing Deadlocks

Academic literature on the topic 'Routing Deadlocks'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Routing Deadlocks"

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Verma, Renu, Mohammad Ayoub Khan, and Amit Zinzuwadiya. "Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe." International Journal of Embedded and Real-Time Communication Systems 4, no. 2 (April 2013): 36–49. http://dx.doi.org/10.4018/jertcs.2013040102.

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Efficient routing is challenging and crucial problem in the irregular mesh NoC topologies because of increasing hardware cost and routing tables. In this paper, the authors propose an efficient deadlock-free routing algorithm for irregular mesh NoCs which reduces the latency and power consumption significantly. The problem with degree priority based routing algorithm is that it cannot remove deadlocks in irregular mesh topologies. Therefore, the authors use the extended Logic Based Distributed Routing (LBDRe) to remove deadlock situations without using any virtual channel in the degree priority based routing algorithm. The proposed LBDRe based technique also removes the dependency on routing tables. The authors further apply odd-Even routing algorithm to LBDRe to ensure that some turns are prohibited to remove deadlocks. Experimental results show that the proposed routing algorithm reduces power consumption by 9–22% and overall average latency by 8–12% with the minimum hardware cost for the irregular mesh NoC topologies.
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Romanov, Aleksandr Y., Nikolay M. Myachin, Evgenii V. Lezhnev, Alexander D. Ivannikov, and Ahmed El-Mesady. "Ring-Split: Deadlock-Free Routing Algorithm for Circulant Networks-on-Chip." Micromachines 14, no. 1 (January 5, 2023): 141. http://dx.doi.org/10.3390/mi14010141.

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This article considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). A new high-level model, Newxim, for the exploration of NoCs with any topology is presented. Two methods for solving the problem of cyclic dependencies in circulant topologies, which limit their applications for NoCs due to the increased possibility of deadlocks, are proposed. The first method of dealing with deadlocks is universal and applicable to any topology; it is based on the idea of bypassing blocked sections of the network on an acyclic subnetwork. The second method—Ring-Split—takes into account the features of circulant topologies. The results of high-level modeling and comparison of the peak throughput of NoCs for circulant and mesh topologies using deadlock-free routing algorithms are presented. It was shown that a new approach for routing in circulants (compared to mesh topology) shows up to 59% better network throughput with a uniform distribution of network load.
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KHONSARI, A., H. SARBAZI-AZAD, and M. OULD-KHAOUA. "A Performance Model of Software-Based Deadlock Recovery Routing Algorithm in Hypercubes." Parallel Processing Letters 15, no. 01n02 (March 2005): 153–68. http://dx.doi.org/10.1142/s012962640500212x.

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Recent studies have revealed that deadlocks are generally infrequent in the network. Thus the hardware resources, e.g. virtual channels, dedicated for deadlock avoidance are not utilised most of the time. This consideration has motivated the development of novel adaptive routing algorithms with deadlock recovery. This paper describes a new analytical model to predict message latency in hypercubes with a true fully adaptive routing algorithm with progressive deadlock recovery. One of the main features of the proposed model is the use of results from queueing systems with impatient customers to capture the effects of the timeout mechanism used in this routing algorithm for deadlock detection. The validity of the model is demonstrated by comparing analytical results with those obtained through simulation experiments.
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., Elavarasi, and G. Raja. "A Necessary and Sufficient Condition for Deadlock-Free Message Routing in Communication Networks." International Journal of Advance Research and Innovation 3, no. 2 (2015): 23–26. http://dx.doi.org/10.51976/ijari.321506.

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Deadlocks are an important issue in the design and analysis of communication networks. Wormhole switching is a popular switching technique in direct networks. It refers to a simple flow control system in computer network that is primarily based on fixed links. It also reduces the latency and storage requirements on each node. Deadlock analysis of routing function is a manual and complex task. In the absence of contention, latencies are proportional to the sum of the packet length and the distances to travel. We propose an algorithm to analyze the deadlock in communication networks. The deadlock-free routing algorithm is the first to automatically check a necessary and sufficient condition for deadlock-free routing. Our algorithm performs Effective analysis in this network.
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KHONSARI, A., A. SHAHRABI, and M. OULD-KHAOUA. "A PERFORMANCE MODEL OF DISHA ROUTING IN K-ARY N-CUBE NETWORKS." Parallel Processing Letters 17, no. 02 (June 2007): 213–28. http://dx.doi.org/10.1142/s0129626407002971.

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A number of analytical models for predicting message latency in k-ary n-cubes have recently been reported in the literature. Most of these models, however, have been discussed for adaptive routing algorithms based on deadlock avoidance, e.g. Duato's routing. Several research studies have empirically demonstrated that routing algorithms based on deadlock recovery offer maximal adaptivity that can result in considerable improvement in network performance. Disha is an example of a true fully adaptive routing algorithm that uses minimal hardware to implement a simple and efficient progressive method to recover from potential deadlocks. This paper proposes a new analytical model of Disha in wormhole-routed k-ary n-cubes. Simulation experiments confirm that the proposed model exhibits a good degree of accuracy for various networks sizes and under different traffic conditions.
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Shrivastava, Anurag, and Sudhir Kumar Sharma. "Efficient bus based router for NOC architecture." World Journal of Engineering 13, no. 4 (August 1, 2016): 370–75. http://dx.doi.org/10.1108/wje-08-2016-049.

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Purpose Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the network-on-chip (NOC) architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand, true fully adaptive routing algorithm provides routing of packets completely based on traffic conditions. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of a global bus beside NOC as a parallel supportive environment provides a platform to offer advantages of both features of bus and NOC. Design/methodology/approach In this research, the authors use this bus as an escaping path for deadlock recovery technique. Findings According to simulation results, this bus is a suitable platform for a deadlock recovery technique. Originality/value This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services.
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Boppana, R. V., S. Chalasani, and C. S. Raghavendra. "Resource deadlocks and performance of wormhole multicast routing algorithms." IEEE Transactions on Parallel and Distributed Systems 9, no. 6 (June 1998): 535–49. http://dx.doi.org/10.1109/71.689441.

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Dimopoulos, N. J., and R. Sivakumar. "Deadlock-preventing routing in hypercycles." Canadian Journal of Electrical and Computer Engineering 19, no. 4 (October 1994): 193–99. http://dx.doi.org/10.1109/cjece.1994.6591123.

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Flammini, Michele. "Deadlock-free interval routing schemes." Networks 34, no. 1 (August 1999): 47–60. http://dx.doi.org/10.1002/(sici)1097-0037(199908)34:1<47::aid-net5>3.0.co;2-3.

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WU, JIE, and LI SHENG. "DEADLOCK-FREE ROUTING IN IRREGULAR NETWORKS USING PREFIX ROUTING." Parallel Processing Letters 13, no. 04 (December 2003): 705–20. http://dx.doi.org/10.1142/s0129626403001616.

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We propose a deadlock-free routing scheme in irregular networks using prefix routing. Prefix routing is a special type of routing with a compact routing table associated with each node (processor). Basically, each outgoing channel of a node is assigned a special label and an outgoing channel is selected if its label is a prefix of the label of the destination node. Node and channel labeling in an irregular network is done through constructing a spanning tree. The routing process follows a two-phase process of going up and then down along the spanning tree, with a possible cross channel (shortcut) between two branches of the tree between two phases. We show that the proposed routing scheme is deadlock- and livelock-free. We also compare prefix routing with the existing up*/down* routing which has been widely used in irregular networks. Possible extensions are also discussed.
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Dissertations / Theses on the topic "Routing Deadlocks"

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Kinsy, Michel A. "Application-aware deadlock-free oblivious routing." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53316.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 67-71).
Systems that can be integrated on a single silicon die have become larger and increasingly complex, and wire designs as communication mechanisms for these systems on chip (SoC) have shown to be a limiting factor in their performance. As an approach to remove the limitation of communication and to overcome wire delays, interconnection networks or Network-on-Chip (NoC) architectures have emerged. NoC architectures enable faster data communication between components and are more scalable. In designing NoC systems, there are three key issues; the topology, which directly depends on packaging technology and manufacturing costs, dictates the throughput and latency bounds of the network; the flit control protocol, which establishes how the network resources are allocated to packets exchanged between components; and finally, the routing algorithm, which aims at optimizing network performance for some topology and flow control protocol by selecting appropriate paths for those packets. Since the routing algorithm sits on top of the other layers of design, it is critical that routing is done in a matter that makes good usage of the resources of the network. Two main approaches to routing, oblivious and adaptive, have been followed in creating routing algorithms for these systems. Each approach has its pros and cons; oblivious routing, as opposite to adaptive routing, uses no network state information in determining routes at the cost of lower performance on certain applications, but has been widely used because of its simpler hardware requirements.
(cont.) This thesis examines oblivious routing schemes for NoC architectures. It introduces various non-minimal, oblivious routing algorithms that globally allocate network bandwidth for a given application when estimated bandwidths for data transfers are provided, while ensuring deadlock freedom with no significant additional hardware. The work presents and evaluates these oblivious routing algorithms which attempt to minimize the maximum channel load (MCL) across all network links in an effort to maximize application throughput. Simulation results from popular synthetic benchmarks and concrete applications, such as an H.264 decoder, show that it is possible to achieve better performance than traditional deterministic and oblivious routing schemes.
by Michel A. Kinsy.
S.M.
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Lehman, Eric (Eric Allen) 1970. "Deadlock-free routing in a faulty hypercube." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47503.

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Holsmark, Rickard. "Deadlock Free Routing inMesh Networks on Chip with Regions." Licentiate thesis, Department of Computer and Information Science, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20284.

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There is a seemingly endless miniaturization of electronic components, which has enabled designers to build sophisticated computing structureson silicon chips. Consequently, electronic systems are continuously improving with new and more advanced functionalities. Design complexity ofthese Systems on Chip (SoC) is reduced by the use of pre-designed cores. However, several problems related to the interconnection of coresremain. Network on Chip (NoC) is a new SoC design paradigm, which targets the interconnect problems using classical network concepts. Still,SoC cores show large variance in size and functionality, whereas several NoC benefits relate to regularity and homogeneity.

This thesis studies some network aspects which are characteristic to NoC systems. One is the issue of area wastage in NoC due to cores of varioussizes. We elaborate on using oversized regions in regular mesh NoC and identify several new design possibilities. Adverse effects of regions oncommunication are outlined and evaluated by simulation.

Deadlock freedom is an important region issue, since it affects both the usability and performance of routing algorithms. The concept of faultyblocks, used in deadlock free fault-tolerant routing algorithms has similarities with rectangular regions. We have improved and adopted one suchalgorithm to provide deadlock free routing in NoC with regions. This work also offers a methodology for designing topology agnostic, deadlockfree, highly adaptive application specific routing algorithms. The methodology exploits information about communication among tasks of anapplication. This is used in the analysis of deadlock freedom, such that fewer deadlock preventing routing restrictions are required.

A comparative study of the two proposed routing algorithms shows that the application specific algorithm gives significantly higher performance.But, the fault-tolerant algorithm may be preferred for systems requiring support for general communication. Several extensions to our work areproposed, for example in areas such as core mapping and efficient routing algorithms. The region concept can be extended for supporting reuse ofa pre-designed NoC as a component in a larger hierarchical NoC.

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Kachru, Rajiv Carleton University Dissertation Computer Science. "Performance of some deadlock prevention routing algorithms for multicomputer systems." Ottawa, 1992.

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Holsmark, Rickard. "Deadlock Free Routing in Mesh Networks on Chip with Regions." Licentiate thesis, Linköping : Department of Compuuter and Information Science, Linköpings universitet, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20284.

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Khonsari, Ahmad. "Performance modelling and analysis of deadlock recovery routing algorithms in multicomputer interconnection networks." Thesis, University of Glasgow, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.398647.

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Domke, Jens. "Routing on the Channel Dependency Graph:." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-225902.

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In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions.
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Castillo, Ernesto Cristopher Villegas. "DyAFNoC: sistema dinamicamente reconfigurável baseado em redes intrachip com algoritmo de roteamento ordenado por dimensão flexibilizado." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-31122015-101031/.

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O aumento da capacidade dos Sistemas sobre Silício (SoCs do inglês, Systemon-Chip) tem levado Redes Intrachip (NoCs do inglês, Network on-Chip) a serem utilizadas como interface de comunicação de Módulos de Processamento de sistemas complexos, e particularmente em Sistemas Dinamicamente Reconguráveis a serem implementados sobre FPGAs com capacidade de reconguração parcial. Algumas estratégias de reconguração geram cenários com NoCs irregulares e indiretas, fato que força o sistema a atualizar o seu algoritmo de roteamento afim de se evitar problemas de comunicação de dados, como deadlock e livelock. O presente trabalho apresenta uma NoC Dinamicamente Recongurável (DRNoC do inglês, Dynamically Recongurable Newtwork on-Chip) utilizando o Algoritmo de Roteamento Ordenado por Dimensão Flexibilizado (FDOR do inglês, Flexible Dimension Order Routing) que se caracteriza principalmente sua simplicidade, baixa complexidade e ser livre de deadlock. No presente trabalho, foi implementada a ferramenta DRSimGen, que gera código VHDL da arquitetura da NoC associada, para ser utilizado com aplicações específicas com reconfiguração parcial dinâmica que requeiram comunicações paralelas entre seus módulos de processamento. Esta ferramenta gera os roteadores, módulos de processamento, além de um Sistema de Controle de Reconguração Parcial Dinâmica que pode ser utilizado junto com o Sistema de Reconguração do algoritmo de roteamento baseado em FDOR, já desenvolvido por outros anteriormente. A ferramenta também gera componentes de testbench para a simulação do sistema, baseados na técnica de Chaveamento Dinâmico de Circuitos; são utilizadas chaves de isolação para emularos processos de reconguração parcial dinâmica. Os resultados destes experimentos ajudaram a determinar o comportamento desejado do sistema. Também foram feitas simulações da implementação do FDOR em descrição de alto nível, com a finalidade de determinar seu desempenho na transferência de dados que ajudarão a definir o posicionamento dos módulos de processamento sobre a estrutura da rede. Os resultados dos experimentos tem demonstrado a viabilidade desta estratégia, levando à conclusão que o algoritmo FDOR é uma solução adequada para DRNoCs.
The increased capacity of Systems on-Chip (SoCs) has led Networks on-Chip (NoC) to be used as communication interface for processing modules of complex systems, and particularly in Dynamically Recongurable Systems to be implemented over partially recongurable FPGAs. Some reconguration strategies work on irregular and indirect NoCs, fact that forces the system to update its routing algorithm in order to avoid data communication problems, such as deadlockandlivelock. ThispaperpresentsaDynamicallyRecongurableNoC(DRNoC)using Flexible Dimension Order Routing Algorithm (FDOR), mainly characterized by its simplicity, low complexity and deadlock freedom In this work, the DyAFNoC tool was implemented, to generate the VHDL code of the associated NoC architecture to be used with specic applications with dynamic partial reconguration that require parallel communications between their processing modules. This tool generates routers, processing modules, and also a Partial Dynamic Reconguration Control System that can be used with the FDOR-based Reconguration System, developed elsewhere. The tool also generates testbench components for the system simulation, based on the Dynamic Circuit Switching technique that uses isolation switches to emulate the dynamic partial reconguration processes. The results of these experiments have helped to determine the desired system behavior. Simulations of the FDOR implementation were also made in high level descriptioninordertodetermineitsdatatransferperformancethatwillhelptodeneplacement of the processing modules over the network structure. The experiments results have demonstrated the feasibility of this strategy, leading to the conclusion that the FDOR algorithm is a suitable solution for DRNoC.
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Domke, Jens [Verfasser], Wolfgang E. [Akademischer Betreuer] [Gutachter] Nagel, and Tor [Gutachter] Skeie. "Routing on the Channel Dependency Graph: : A New Approach to Deadlock-Free, Destination-Based, High-Performance Routing for Lossless Interconnection Networks / Jens Domke ; Gutachter: Wolfgang E. Nagel, Tor Skeie ; Betreuer: Wolfgang E. Nagel." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://d-nb.info/1135907439/34.

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Hwang, Gwo-Jen, and 黃國貞. "Deadlock-free Multicast Routing Strategies in Wormhole-routing Hypercube Computers." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/71557479126381282037.

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碩士
國立臺灣科技大學
工程技術研究所
81
The communication latency between nodes of hypercube is a vital factor to the performance of the whole system. Multicast communication refers to the delivery of the same message from a source node to an arbitrary number of destination nodes. The deadlock-freeness and the performance improvement are the prin- cipal concern of routing algorithms. Since virtual channel is help to the expedition of message passing, this thesis employs the concept of virtual channel to avoid the deadlock and improve the performance. Deadlock-free multicast routing algorithm on path-like model is proposed. The simulation results indicate that one-path routing algo- rithm has lower traffic congestion than that of dual-path routing algorithm. Furthermore, it can also reduce the latency significantly, improving communication performance.
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Book chapters on the topic "Routing Deadlocks"

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Al-Dujaily, Ra’ed, Terrence Mak, Fei Xia, Alex Yakovlev, and Maurizio Palesi. "Run-Time Deadlock Detection." In Routing Algorithms in Networks-on-Chip, 41–68. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8274-1_3.

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von Praun, Christoph, Christoph von Praun, Jeremy T. Fineman, Charles E. Leiserson, Efstratios Gallopoulos, Marc Snir, Michael Heath, et al. "Routing (Including Deadlock Avoidance)." In Encyclopedia of Parallel Computing, 1749–56. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_314.

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Warnakulasuriya, Sugath, and Timothy Mark Pinkston. "Modeling Message Blocking and Deadlock in Interconnection Networks." In Parallel Computer Routing and Communication, 275–93. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/3-540-69352-1_23.

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Flammini, Michele. "Deadlock-free interval routing schemes." In Lecture Notes in Computer Science, 351–62. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0023472.

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Agrawal, Nidhi, and C. P. Ravikumar. "Adaptive routing based on deadlock recovery." In Euro-Par’98 Parallel Processing, 981–88. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0057957.

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López, P., J. M. Martínez, J. Duato, and F. Petrini. "On the Reduction of Deadlock Frequency by Limiting Message Injection in Wormhole Networks." In Parallel Computer Routing and Communication, 295–307. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/3-540-69352-1_24.

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Adeane, J., and V. W. Wittorff. "Deadlock Avoidance in the PNNI Routing Protocol." In Converged Networking, 1–12. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-35673-0_1.

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Samman, Faizal Arya, and Thomas Hollstein. "Efficient and Deadlock-Free Tree-Based Multicast Routing Methods for Networks-on-Chip (NoC)." In Routing Algorithms in Networks-on-Chip, 129–59. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8274-1_6.

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Swain, Jyotiranjan, and Sumanta Pyne. "Deadlock Detection in Digital Microfluidics Biochip Droplet Routing." In Communications in Computer and Information Science, 242–53. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5950-7_21.

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Adamo, J. M., and N. Alhafez. "Minimal, adaptive and deadlock-free routing for multiprocessors." In Parallel Processing: CONPAR 92—VAPP V, 815–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55895-0_503.

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Conference papers on the topic "Routing Deadlocks"

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Lienert, Thomas, and Johannes Fottner. "No More Deadlocks – Applying The Time Window Routing Method To Shuttle Systems." In 31st Conference on Modelling and Simulation. ECMS, 2017. http://dx.doi.org/10.7148/2017-0169.

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Cazenave, P., M. Khlif-Bouassida, and A. Toguyeni. "Collisions avoidance and deadlocks prevention, for dynamic routing of trains in a railway node." In 2019 6th International Conference on Control, Decision and Information Technologies (CoDIT). IEEE, 2019. http://dx.doi.org/10.1109/codit.2019.8820580.

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Olenev, V. L., and A. A. Karandashev. "METHODS FOR SELECTING THE OPTIMAL CONFIGURATION OF DEADLOCK-FREE ROUTES IN ON-BOARD SPACEWIRE NETWORKS." In Aerospace instrumentation and operational technologies. Saint Petersburg State University of Aerospace Instrumentation, 2021. http://dx.doi.org/10.31799/978-5-8088-1554-4-2021-2-293-302.

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This paper discusses the problem of choosing the best combination of deadlock-free routes of the Up/Down routing algorithm in the framework of the SANDS software. The software is designed specifically for design and simulation of SpaceWire on-board networks. The second component of SANDS allows you to set deadlock-free routes for information flows and select a configuration to present to the user. The document not only sets out the tasks and problems of this area, but also provides an overview of various solutions. In addition, an algorithm is presented that allows you to choose the best combination of deadlock-free routes. Alternative directions for further research are also indicated.
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Raksapatcharawong, Mongkol, and Timothy Mark Pinkston. "A System Demonstration of Progressive Deadlock Recovery Routing based on Optoelectronic/VLSI Chips." In Optics in Computing. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/oc.1997.othd.18.

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We present a system demonstration of a sequential deadlock recovery-based scheme [1] employing a circulating token to guarantee mutual exclusive access to deadlock buffers. This system allows us to evaluate the design and implementation of a multiprocessor network router using free-space optical interconnects. The system is designed based on our CMOS-SEED chip—OMNI [2] and GaAs-based chip—WARRP [3]. These two chips are employed to implement asynchronous optical token-based resource arbitration and deadlock recovery via channel preemption, respectively. With an external node controller, this experimental system is capable of demonstrating a high-performance bandwidth-efficient deadlock recovery-based multiprocessor network router.
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Awerbuch, Baruch, Shay Kutten, and David Peleg. "Efficient deadlock-free routing." In the tenth annual ACM symposium. New York, New York, USA: ACM Press, 1991. http://dx.doi.org/10.1145/112600.112616.

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Quintin, Jean-Noel, and Pierre Vigneras. "Transitively Deadlock-Free Routing Algorithms." In 2016 2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB). IEEE, 2016. http://dx.doi.org/10.1109/hipineb.2016.10.

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Chujo, Taichi, Kosei Nishida, and Tatsushi Nishi. "A Conflict-Free Routing Method for Automated Guided Vehicles Using Reinforcement Learning." In 2020 International Symposium on Flexible Automation. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/isfa2020-9620.

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Abstract:
Abstract In a modern large-scale fabrication, hundreds of vehicles are used for transportation. Since traffic conditions are changing rapidly, the routing of automated guided vehicles (AGV) needs to be changed according to the change in traffic conditions. We propose a conflict-free routing method for AGVs using reinforcement learning in dynamic transportation. An advantage of the proposed method is that a change in the state can be obtained as an evaluation function. Therefore, the action can be selected according to the states. A deadlock avoidance method in bidirectional transport systems is developed using reinforcement learning. The effectiveness of the proposed method is demonstrated by comparing the performance with the conventional Q learning algorithm from computational results.
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Kinsy, Michel A., Myong Hyon Cho, Tina Wen, Edward Suh, Marten van Dijk, and Srinivas Devadas. "Application-aware deadlock-free oblivious routing." In the 36th annual international symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1555754.1555782.

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Prisacari, Bogdan, German Rodriguez, Cyriel Minkenberg, and Ramon Beivide Palacio. "Performance implications of deadlock avoidance techniques in torus networks." In 2012 IEEE 13th International Conference on High Performance Switching and Routing (HPSR). IEEE, 2012. http://dx.doi.org/10.1109/hpsr.2012.6260837.

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Kurbanov, Lev, Ksenia Rozhdestvenskaya, and Elena Suvorova. "Deadlock-Free Routing in SpaceWire Onboard Network." In 2018 22nd Conference of Open Innovations Association (FRUCT). IEEE, 2018. http://dx.doi.org/10.23919/fruct.2018.8468268.

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