Dissertations / Theses on the topic 'RISC V processor'

The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.

This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.

This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.

Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2021
Cataloged from the official PDF of thesis.
Includes bibliographical references (pages 139-140).
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.
by Gloria (Yu Liang) Fang.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.

The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.

The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.

Negli ultimi anni in applicazioni come il Machine Learning la complessità degli algoritmi è in continua crescita, per migliorarne l’efficienza e velocizzarne l’esecuzione si è iniziato ad usare nuovi formati di precisione, come ad esempio il brain float il quale, presenta lo stesso numero di bit per l’esponente di un floating point a 32 bit ma tronca la mantissa in modo da rientrare in 16 bit. In questa maniera si mantiene lo stesso range dinamico del fp32 riducendo però la precisione in modo accettabile per applicazioni come near-sensor-computing e machine learning. Il vantaggio di utilizzare un formato con ridotto numero di bit si vede in termini di memory-footprint e banda, e nelle performance grazie alla vettorizzazione delle operazioni. Altri formati che possiamo trovare in algoritmi di machine learning sono fixed-point a 4, 2 ed 1 bit che vengono usati in reti neurali quantizzate in modo da permetterne l’implementazione anche in dispositivi come i microcontollori con risorse limitate. Supportare tutti questi formati su processori general-purpose può essere difficoltoso per il rischio di saturare l’encoding space e soluzioni come l’implementazione di istruzioni a lunghezza variabili rischiano di complicare troppo lo stadio di decodifica con conseguente aumento di consumi. In questa tesi si propone la progettazione e ottimizzazione di un core basato su ISA RISC-V in modo da operare a stati: per ogni tipo di istruzione floating point e SIMD fixed point si ha un unica codifica indipendentemente dal formato, dove quest’ultimo (stato) è contenuto in un registro di controllo risolvendo quindi il problema dell’encoding space. Questo ci ha permesso di supportare 15 formati per istruzioni SIMD tra cui 6 a precisioni miste. Queste modifiche hanno reso possibile l’esecuzione di kernel convoluzionali a 4 e 2 bit con performance da 3,78 a 7,78 volte superiori al core originale.

Nowadays, network processors are an integral part of information technology. With the deployment of 5G network ramping up around the world, numerous new devices are going to take advantage of their processing power and programming flexibility. Contemporary information technology providers of today such as Ericsson, spend a great amount of financial resources on licensing deals to use processors with proprietary instruction set architecture designs from companies like Arm holdings. There is a new non-proprietary instruction set architecture technology being developed known as Risc-V. There are many open source processors based on Risc-V architecture, but it is still unclear how well an open-source Risc-V processor performs network packet processing tasks compared to an Arm-based processor. The main purpose of this thesis is to design a test model simulating and evaluating how well an open-source Risc-V processor performs packet processing compared to an Arm Cortex M7 processor. This was done by designing a C code simulating some key packet processing functions processing 50 randomly generated 72 bytes data packets. The following functions were tested: framing, parsing, pattern matching, and classification. The code was ported and executed in both an Arm Cortex M7 processor and an emulated open source Risc-V processor. A working packet processing test code was built, evaluated on an Arm Cortex M7 processor. Three different open-source Risc-V processors were tested, Arianne, SweRV core, and Rocket-chip. The execution time of both cases was analyzed and compared. The execution time of the test code on Arm was 67, 5 ns. Based on the results, it can be argued that open source Risc-V processor tools are not fully reliable yet and ready to be used for packet processing applications. Further evaluation should be performed on this topic, with a more in-depth look at the SweRV core processor, at physical open-source Risc-V hardware instead of emulators.
Nätverksprocessorer är en viktig byggsten av informationsteknik idag. I takt med att 5G nätverk byggs ut runt om i världen, många fler enheter kommer att kunna ta del av deras kraftfulla prestanda och programerings flexibilitet. Informationsteknik företag som Ericsson, spenderarmycket ekonomiska resurser på licenser för att kunna använda proprietära instruktionsuppsättnings arkitektur teknik baserade processorer från ARM holdings. Det är väldigt kostam att fortsätta köpa licenser då dessa arkitekturer är en byggsten till designen av många processorer och andra komponenter. Idag finns det en lovande ny processor instruktionsuppsättnings arkitektur teknik som inte är licensierad så kallad Risc-V. Tack vare Risc-V har många propietära och öppen källkod processor utvecklats idag. Det finns dock väldigt lite information kring hur bra de presterar i nätverksapplikationer är känt idag. Kan en öppen-källkod Risc-V processor utföra nätverks databehandling funktioner lika bra som en proprietär Arm Cortex M7 processor? Huvudsyftet med detta arbete är att bygga en test model som undersöker hur väl en öppen-källkod Risc-V baserad processor utför databehandlings operationer av nätverk datapacket jämfört med en Arm Cortex M7 processor. Detta har utförts genom att ta fram en C programmeringskod som simulerar en mottagning och behandling av 72 bytes datapaket. De följande funktionerna testades, inramning, parsning, mönster matchning och klassificering. Koden kompilerades och testades i både en Arm Cortex M7 processor och 3 olika emulerade öppen källkod Risc-V processorer, Arianne, SweRV core och Rocket-chip. Efter att ha testat några öppen källkod Risc-V processorer och använt test koden i en ArmCortex M7 processor, kan det hävdas att öppen-källkod Risc-V processor verktygen inte är tillräckligt pålitliga än. Denna rapport tyder på att öppen-källkod Risc-V emulatorer och verktygen behöver utvecklas mer för att användas i nätverks applikationer. Det finns ett behov av ytterligare undersökning inom detta ämne i framtiden. Exempelvis, en djupare undersökning av SweRV core processor, eller en öppen-källkod Risc-V byggd hårdvara krävs.

The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.

Ce document presente diverses applications des circuits numeriques en arseniure de gallium (asga) dans les systemes a haut debit de communication et dans les calculateurs performants. Ces applications ont guidees l'ensemble des recherches effectuees au cours de la these dont ce document est l'aboutissement. La necessite de performances elevees, inherentes aux applications traitees, a necessite l'etude et la mise en uvre de topologies differentes qui ont donne lieu a un ensemble de solutions efficaces. Dans le but d'obtenir une marge de bruit assez elevee et de bonnes performances en vitesse, en complexite et en puissance consommee, la conception de circuit en asga souleve des themes majeurs qui se resument aux points suivants: dimentionnement de transistors, topologies de masques, strategies d'amplification et de distribution d'horloges. Ils apparaissent nettement dans les applications traites qui sont decrites ci-dessous. La premiere application de la technologie asga dans les circuits a grande vitesse concerne la conception d'un diviseur redondant a 16 chiffres binaires. Une methode purement full custom a ete utilisee pour exploiter le potentiel de la technologie. Cette methode a permis des optimisations au niveau de la vitesse, de la densite et de la consommation. Le principal probleme mis en evidence lie a cette methode, est sa lourdeur d'emploi, qui la rend pratiquement inutilisable dans le cas des circuits a grande complexite. Pour mettre rapidement sur le marche un produit en asga, nous avons choisi de mettre en application les methodes de synthese de haut niveau afin de generer un chemin de donnees destine a un microprocesseur de type risc. L'avantage en temps de conception lie aux outils de synthese comportementale s'est avere compense par une augmentation de la surface d'implantation comparee a la methode full-custom. Ceci etant un facteur determinant en asga par rapport au cmos, technologie bien meilleur marche et initialement visee par cet outil, il est donc ressorti tres clairement de cette application l'interet d'appliquer un compromis consistant a synthetiser automatiquement des parties du circuit ou la vitesse n'est pas critique, et a utiliser la methode full custom pour les parties ou la vitesse est un parametre important. Cette derniere approche a ete adoptee pour la conception d'un circuit destine a des applications atm (asynchronous transfer mode). Ce circuit a ete concu pour fonctionner a une frequence de 312 mhz. La consommation de puissance a ete estimee autour de 4w, ce qui s'avere etre une performance tout a fait competitive compte tenu du debit a assumer, par rapport aux conceptions cmos existantes

Submitted by Pedro Barros (pedro.silvabarros@ufpe.br) on 2018-08-22T19:41:45Z No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Cecil Accetti Resende de Ataíde Melo.pdf: 2769633 bytes, checksum: f491d3b88b08cb65e70c14b653034fdf (MD5)
Approved for entry into archive by Alice Araujo (alice.caraujo@ufpe.br) on 2018-08-29T21:40:28Z (GMT) No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Cecil Accetti Resende de Ataíde Melo.pdf: 2769633 bytes, checksum: f491d3b88b08cb65e70c14b653034fdf (MD5)
Made available in DSpace on 2018-08-29T21:40:28Z (GMT). No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Cecil Accetti Resende de Ataíde Melo.pdf: 2769633 bytes, checksum: f491d3b88b08cb65e70c14b653034fdf (MD5) Previous issue date: 2016-08-26
CNPq
Os sistemas de software-defined radio práticos normalmente se dividem em duas classes: arquiteturas reconfiguráveis em FPGA que implementam os algoritmos de processamento de digital de sinais, com granularidade alta e, as arquiteturas baseadas em processador. Um dos problemas no projeto de arquiteturas de processamento digital de sinais baseadas em processador é o do suporte a compiladores e linguagens de alto nível. Arquiteturas muito especializadas, com conjuntos de instruções extensos e muitos modos de endereçamento, dificultam a implementação de compiladores para linguagens de alto nível. Neste trabalho buscou-se explorar a viabilidade de um conjunto de instruções emergente, RISC-V, e uma extensão do seu conjunto de instruções para a aplicação em processamento digital de sinais de banda base, sobretudo nas funcionalidades de modem, em aplicações de software-defined radio. A análise das operações de um modem, para as modulações digitais mais utilizadas, revela que as operações feitas para modulação/ demodulação envolvem números complexos. No entanto, aritmética de complexos não é normalmente suportada pelo hardware em arquiteturas tradicionais. Além da arquitetura proposta para o processador, com suporte a novas instruções especializadas, os periféricos necessários para o front-end de rádio frequência e o software de suporte foram implementados, resultando num SoC para software defined radio.
Practical software-defined radio systems are usually classified in two main architecture classes: Reconfigurable architectures on FPGAs, that implement coarse grained digital signal processing algorithms, or processor-based architectures. One of the issues in the design of processor-based digital signal processing architectures is compiler and high-level languages support. Highly specialized architectures, with extensive instruction sets (ISA) and addressing modes turn high-level languages compiler design a complex task. In this work we explore the viability to extend the emerging RISC-V instruction set for baseband processing applications for software-defined radio, especially for modem applications. The analysis of modem functions, for the most used digital modulation schemes, reveals that the modulation/demodulation tasks involve complex number operations. Complex number arithmetic, however, is not supported on traditional architectures. The proposed platform includes a 3-stage pipelined processor with new specialized instructions, as well as the peripherals needed to the radio-frequency front-end and supporting software, resulting on a system-on-a-chip for software-defined radio applications. software-defined radio.

This thesis presents a system designed to support risk management in IT projects. The presented system is based on an in depth analysis of project and risk management in the field of information Technologies. The implementation started only after the exhaustive analyzation process. The system was implemented in programming language C#. On the database level MS SQL server is used.

This thesis is about hazardous of ETL processes in their data warehouse. In the first part of this thesis I have defined the ETL processes and the aim of this thesis. The second part is about theoretical solutions needed to create a data warehouse, the definition of ETL processes and discovering potential risks. The third part is about discovering potential risks of ETL processes using an analysis and risk assessment. This part also includes a control of the potential risks. The fourth part concentrates on modifying the ETL processes to prevent potential risks. An important part of this chapter is an emergency plan containing necessary processes which must be applied in case of a risk. The fifth part of this thesis is a summary of all knowledge found during the analysis and development.

The Diploma thesis deals with the methods of analysis of corporate indicators and their use in the context of preventive Risk management for company Skoda Auto a.s.. Based on the performed analysis is optimized current process and are proposed new corporate indicators in the context of preventive Risk management.

This thesis deals with the implementation of the Bring Your Own Device program for employee's private laptops at Telefonica Czech Republic. It describes the solution using a distributed virtualization. The private laptops are given identical system environments as standard corporate laptops. The solution of the problem is set in the environment of the real corporation. Areas focused on the establishment and operation of the program are security, technology, finance and processes.

碩士
國立交通大學
電機工程學系
105
To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. However, the number of channels will limit by chip area. ICA has much matrix operations. The complexity of matrix is O (n2~3). It is hard to extend channel out of four to eight channels. In the case of ECoG signal, the electrode patches are fixed after installation. Some of the FastICA algorithm can be reduced because of fixed electrode patches. We only need one-time singular value decomposition for eigenvalue at first time. We can implement singular value decomposition by firmware in stand of hardware to reduce area. We can have more area to get more channels. The microcontroller can implement other protocol and signal process making this chip more applicable. The performance of the chip was verified by human dataset.

Manycore heterogeneous architectures are becoming the promising choice for high-performance computing applications. Multiple parallel tasks run concurrently across different processor cores sharing the same communication and memory resources, thus providing high performance and throughput. But, with the increase in the number of cores, the complexity of the system also increases. Such systems provide very limited visibility of internal processing behaviour. This poses a challenge for a software developer as it is difficult to monitor the program in execution. Monitoring the program behaviour is required for exploiting the architecture to the maximum, debugging, security, performance analysis, and so on. REDEFINE is one such macro dataflow execution based manycore co-processor designed to accelerate the compute-intensive part of an application. In this work, we propose a static and dynamic monitoring framework in REDEFINE. First, we present a software instrumentation based approach to generate the execution traces with negligible hardware overhead. The generated trace data is processed through an offline analysis tool to get the execution graph. This graph can be utilized to analyse the program behaviour statically. Although this approach is flexible and easy to implement, the offline analysis might result in delayed detection of any unexpected program behaviour. To address this, we then present a run-time monitoring framework. In this approach, a separate hardware monitoring unit runs in parallel to the processor core. The monitor is programmed with the monitoring graph obtained from static analysis of the program binary. It matches the instructions executed with the corresponding information in the monitoring graph and flags any unintended program behaviour. This aids in the identification of any intrusion or attack that alters the control flow integrity of the program executed and further helps in the realisation of a secure computing platform that is a primary requirement today in the area of 5G network processing, autonomous vehicles and avionics applications.

Dissertação de mestrado em Engenharia Eletrónica Industrial e Computadores
Safety-critical systems deployed in harsh environments rely on fault tolerance and redundancy techniques to keep them operating even in the presence of faults. Although there are effective techniques to mitigate one side faults, they are not enough to protect the system against simultaneously multi side faults. These kinds of faults trigger the same error in faulty redundant components, which makes resulting errors invisible and undetectable for fault tolerant mechanisms. To overcome this problem, design diversity is applied in fault tolerant system to mitigate the Common-Mode Failure (CMF) and build a more robust and reliable system. Despite several fault tolerance architectures based on FPGA are available in the literature, to the best of our knowledge, none of them aims both hardening of heterogeneous processors and applying design diversity at processor level. To address this lack of solutions in the current state of the art, this dissertation proposes a novel heterogeneous fault tolerance architecture, Lock-V, which enables design diversity at processors architecture level. It deals with CMF, as well as both error detection and recovery fault tolerance techniques to mitigate errors triggered by external environment interactions, e.g., radiation. To eliminate the CMF, Lock-V explores an implementation based on different processing units: a hard-core Arm Cortex-A9 and a soft-core RISC-V-based processors, to leverage design diversity through ISA heterogeneity. To implement fault tolerance, Lock-V proposes a hybrid DCLS solution where the error detection is done by hardware, resorting to a FPGA accelerator, while error recovery is performed by software using rollback technique. After the deployment of Lock-V on a Zynq-7000 SoC, over 45000 faults were injected. The results taken from such injection shows that when an application runs on the Lock-V architecture, besides its protection against the CMF due to processors design diversity, it is also protected against 97% of the triggered errors. Nevertheless implement Lock-V came up with some tradeoffs. It used 79% of the LUT and 34% of the FF available on the Zedboard FPGA platform. Regarding the software part, implementing Lock-V leads to an 8% increase in memory footprint and also an increase in the execution overhead around 12%, mainly in the worst case scenario as tested in the absence of errors. Knowing that all the redundancy has its cost, Lock-V proved to be able to grant a system with design diversity and fault tolerance capabilities.
Quando sistemas críticos operam em ambientes hostis, estes necessitam de serviços de redundância e de tolerância a falhas para continuarem em funcionamento mesmo na presença de faltas. Embora a técnica de tolerância a falhas seja eficaz para mitigar faltas que ocorrem num único componente, ela perde eficácia, quando múltiplas faltas acontecem simultaneamente em vários componentes. Estes tipos de faltas, despoletam o mesmo erro em todos os componentes afetados, tornando-as indetectáveis. Para solucionar este problema, usualmente, recorre-se a diversidade de desenho para mitigar as Falhas de Modo Comum (FMC), construindo assim um sistema mais robusto e confiável. Várias arquiteturas de tolerância a falhas, baseadas em Field-Programmable Gate Array (FPGA), têm sido descritas na literatura, no entanto, pelas pesquisas efetuadas, nenhuma delas tem como objetivo proteger processadores heterogéneos e aplicar diversidade de desenho ao nível do processador. Para resolver a supracitada falta de soluções, esta dissertação propõe uma nova arquitetura heterogénea de tolerância a falhas, Lock-V. O Lock-V promove diversidade de desenho, ao nível da arquitetura do processador, assim como técnicas de tolerância a falhas para, respetivamente, mitigar FMC e detetar e recuperar erros despoletados por causas externas, por exemplo, radiação. Para eliminar as FMC, o Lock-V possuí duas unidades de processamento diferentes: um hard-core Arm Cortex-A9 e um soft-core baseado em RISC-V. Desta forma é aplicada diversidade de desenho, usando heterogeneidade no Instruction Set Architecture (ISA). Por outro lado, para implementar tolerância a falhas, o Lock-V propõe uma solução híbrida de Dual-Core Lockstep (DCLS), onde a deteção de erros é feita em hardware, recorrendo a um acelerador na FPGA, e a recuperação dos erros é suportado por software, usando técnicas de rollback. Após o Lock-V ser implementado na Zynq-7000 System-on-Chip (SoC), mais de 45000 faltas foram injetadas. Os resultados dessa injeção mostram que quando uma aplicação executa na arquitetura Lock-V, para além de estar protegida contra FMC, devido à diversidade do desenho ao nível dos processadores, também está protegida contra 97% dos erros ocorridos. No entanto, implementar o Lock-V acarreta alguns tradeoffs. 79% das Look-Up Tables (LUT) e 34% dos Flip-Flops (FF) disponíveis na plataforma (Zedboard), são usados. Ao nível do software, o Lock-V aumenta em 8% o consumo de memoria e, para o pior cenário testando sem a ocorrência de erros, aumenta em 12% o overhead de execução. Tendo em conta que toda a redundância tem o seu custo, o Lock-V provou ser capaz de dotar um sistema com diversidade de desenho e capacidades de tolerância a falhas.

The number of IoT devices has greatly increased over the years, so that they have invaded the electronic market. IoT describe a device-to-device communication without human interface. A large class of these devices are battery powered, and the energy consumption inside them is considered critical. Today’s embedded IoT systems interface multiple peripherals such as sensors that perform continuous monitoring of the environment around it, and actuators that are controlled by the embedded systems. Also, they interface wireless devices for data transmissions. A part of their job includes some basic pre-processing of the data before transmitting it over those wireless networks. Such pre-processing “on the edge of the network” minimizes the data to be transmitted over the wireless channels, and only transmits the desired outputs. In front of the increase demand to support pre-processing, such as computer vision and voice recognition, on small embedded systems on the edge of the network, they cannot completely satisfy those demands due to their little performance In this study we demonstrate the performance and energy efficiency of interleaved multithreaded architectures, which can be used in an embedded system on the edge of the IoT interfacing multiple sensors and peripherals, each serviced by a different hardware thread. We show the optimal pipeline organization to use in such architectures, and we finally demonstrate how these architectures can be exploited to easily improve instruction level parallelism by integrating a convolutional neural networking accelerator that can perform very fast vector arithmetic operations, and finally benchmarking this accelerator by running a custom implementation of the VGG16 convolutional neural network. The microprocessors presented are a part of a family of processing cores called Klessydra. The Klessydra microprocessors were written such that they have a pinout that are 100 percent identical with Riscy cores from PULPino SoC. The subset of the Klessydra cores presented in this thesis is called the Klessydra-T. The letter ‘T’ indicating that the cores are multithreaded, the Klessydra-T subset has two main implementations used throughout this thesis, they are Klessydra-T03 and Klessydra-T13. T03 and T13 for short. The processor cores have been tested with the Modelsim / Questasim simulators. The cores have been synthesized on the 7-series FPGAs from Xilinx with the Vivado Synthesis tool. Synthesis and Post-synthesis simulations have been made. Dynamic Power estimations were calculated by Vivado from the power report generated by Modelsim after having simulated a post-synthesis Vivado netlist. FPGA synthesis was chosen as our target implementation, as they provide high reconfigurability, which allows the user to easily customize their own accelerator and make it adapt accordingly to their specific applications. In our assessment throughout this thesis we nominated the T03 interleaved multithreaded processor as our optimal and most balanced pipeline organization. The T03 core had many advantages over other architectures, however it was only suitable to be used in control applications. T13 solves this problem by implementing superscalar hardware accelerators. A hybrid implementation of the hardware accelerator targeting thread level parallelism and slight data level parallelism was the approach yielding the highest performance and still maintaining a relatively low energy consumption for energy critical environments.