Dissertations / Theses on the topic 'RF high power amplifiers'

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology. As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.

Power amplifiers (PAs) are one of the most crucial elements in wireless standards becasue they are the most power hungry subsystems. These elements have to face an important issue, which is the power efficiency, a fact related with the output back-off (OBO). But the OBO depends on the kind of modulated signal, in proportion to the modulated signal peak-to-average power ratio (PAPR). The higuer is the data rate, the higer is the OBO, and consequently the lower is the efficiency. A low efficiency of PAs causes the waste of energy as heat. Furthermore, the trade-off between linearity and efficiency in PAs is another major issue. To cope with the undesired circumstances producing efficiency degradation, the Doherty power amplifier (DPA) is one of the useful techniques which provide high efficiency for high PAPR of modern communication signals. Nevertheless, the limited bandwidth (BW) of this kind of PAs (about 10% of fractional bandwidth) and its importance (in modern wireless systems such as LTE, WiMAX, Wi-Fi and satellite systems) have encouraged the researchers to improve this drawback in recent years. Some typical BW limiting factors effect on the performance of DPAs: i) quarter-wave length transformers, ii) phase compensation networks in/output matching circuits, iii) offset lines and device non-idealities; The quarter-wave length transformers performs as an inverter impedance in the load modulation technique of DPAs. The future objective in designing DPAs is to decrease the impact of these issues. In this context, this PhD-thesis is focused on improving fractional bandwidth of DPAs using the new methods that are related to impedance transformers instead of impedance inverters in the load modulation technique. This study is twofold. First, it is presented a novel DPA where a wideband GaN DPA in the 2.5 GHz band with an asymmetrical Wilkinson splitter. The impedance transformer of the proposed architecture is based on a matching network including a tapered line with multi-section transformer in the main stage. The BW of this DPA has ranged from 1.8 to 2.7 GHz. Plus, the obtained power efficiency (drain) is higher than 33% in the whole BW at both maximum and OBO power levels. Second, based on the benefits of the Klopfenstein taper, a promising DPA design is proposed where a Klopfenstein taper replaces the tapered line. In fact, this substitution results on reducing the reflection coefficient of the transformer. From a practical prototype realization of this novel Doherty-like PA in the 2.25 GHz band, this modification has demonstrated that the resulting DPA BW is increased in comparison to the conventional topology while keeping the efficiency figures. Moreover, this study also shows that the Klopfenstein taper based design allows an easy tuning of the group delay through the output reactance of the taper, resulting in a more straightforward adjustments than other recently published designs where the quarter-wave transformer is replaced by multi-section transmission lines (hybrid or similar). Experimental results have shown 43-54% of drain efficiency at 42 dBm output power, in the range of 1.7 to 2.75 GHz. Concretely, the results presented in this novel Doherty-like PA implies an specific load modulation technique that uses the mixed Klopfenstein tapered line together with a multi-section transformer in order to obtain high bandwidth with the usual efficiency in DPAs.
Los amplificadores de potencia (PAs) son uno de los elementos más importantes para los transmisores inalámbricos desde el punto de vista del consumo energético. Un aspecto muy importante es su eficiencia energética, un concepto relacionado con el back-off de salida (OBO), que a su vez viene condicionadpo por el PAPR de la señal modulada a amplificar. Una baja eficiencia de los PA hace que la pérdida de energía se manifieste en forma de calor. De hecho, esta cuestión conduce al incremento de los costes y tamaño, esto último por los radiadores. Además, el compromiso entre la linealidad y la eficiencia en los PA es otro problema importante. Para hacer frente a las circunstancias que producen la degradación de la eficiencia, el amplificador de potencia tipo Doherty (DPA) es una de las técnicas más útiles que proporcionan una buena eficiencia incluso para los altos PAPR comunes en señales de comunicación modernos. Sin embargo, el limitado ancho de banda (BW) de este tipo de PA (alrededor del 10% del ancho de banda fraccional) y su importancia (en los sistemas inalámbricos modernos, tales como LTE, WiMAX, Wi-Fi y sistemas de satélites) han animado a los investigadores para mejorar este inconveniente en los últimos años. Algunos aspectos típicos que limitan el BW en los DPA son: i) transformadores de longitud de cuarto de onda, ii) redes de compensación de fase y circuitos de adaptación de salida, iii) compensación de las líneas y los dispositivos no ideales. Los transformadores de cuarto de onda actuan como un inversor de impedancia en la técnica de modulación de carga de la DPA "("load modulation"). Concretamente, el objetivo futuro de diseño de DPA es disminuir el impacto de estos problemas. En este contexto, esta tesis doctoral se centra en mejorar el ancho de banda fraccional de DPA utilizando los nuevos métodos que están relacionados con el uso de transformadores de impedancias en vez de inversores en el subcircuito de modulación de carga. Este estudio tiene dos niveles. En primer lugar, se presenta una novedosa estructura del DPA de banda ancha usándose dispositivos de GaN en la banda de 2,5 GHz con un divisor Wilkinson asimétrico. El transformador de impedancias de la arquitectura propuesta se basa en una red de adaptación, incluyendo una línea cónica con múltiples secciones del transformador en la etapa principal. El BW de este DPA ha sido de 1,8 a 2,7 GHz. Además, se obtiene una eficiencia de drenador de más del 33% en todo el BW, tanto a nivel de potencia máxima como a nivel del OBO. En segundo lugar, aprovechando los beneficios de un adaptador de Klopfenstein, se propone un nuevo diseño del DPA. Con la sustitución de la lina conica por el Klopfenstein se reduce el coeficiente de reflexión de transformador de impedancias. Sobre un prototipo práctico de esta nueva estructura del Doherty, en la banda de 2,25 GHz, se ha demostrado que el BW resultante se incrementa en comparación con la topología convencional mientras se mantienen las cifras de eficiencia. Por otra parte, en este estudio se demuestra que el diseño basado en el Klopfenstein permite una afinación fácil del retardo de grupo a través de la reactancia de salida del taper, lo que resulta en un ajuste más sencillo que otros diseños publicados recientemente en el que el transformador de cuarto de onda se sustituye por multi-líneas de transmisión de la sección (híbridos o similar). Los resultados experimentales han mostrado un 43-54% de eficiencia de drenador sobre 42 dBm de potencia de salida, en el intervalo de 1,7 a 2,75 GHz. Concretamente, los resultados presentados en esta nueva estructura tipo-Doherty implican una técnica de modulación de carga que utiliza una combinación de un Klopfenstein junto con un transformador de múltiples secciones con el fin de obtener un alto ancho de banda con la eficiencia habitual en DPAs.
Els amplificadors de potència (PA) són un dels elements més importants per els sistemes ràdio ja que sone ls principals consumidors d'energía. Un aspecte molt important és l'eficiència de l'amplificador, aspecte relacionat amb el back-off de sortida (OBO) que a la seva vegada ve condicionat pel PAPR del senyal modulat. Una baixa eficiència dels PA fa que la pèrdua d'energia en manifesti en forma de calor. De fet, aquesta qüestió porta a l'increment dels costos i grandària, degut als dissipadors de calor. A més, el compromís entre la linealitat i l'eficiència en els PA es un altre problema important. Per fer front a les circumstàncies que porten a la degradació de l'eficiència, l'amplificador de potència Doherty (DPA) és una de les tècniques més útils i que proporcionen una bona eficiència per als alts PAPR comuns en senyals de comunicació moderns. No obstant això, l'ample de banda limitat (BW) d'aquest tipus de PA (al voltant del 10% de l'ample de banda fraccional) i la seva importància (en els sistemes moderns, com ara LTE, WiMAX, Wi-Fi i sistemes de satèl·lits) han animat els investigadors per millorar aquest inconvenient en els últims anys. Alguns aspectes tipicament limitadors del BW en els DPA son: i) transformadors de longitud d'quart d'ona, ii) xarxes de compensació de fase en circuits / adaptacions de sortida, iii) compensació de les línies i els dispositius no ideals. Els transformadors de quart d'ona s'utilitzen com a inversors d'impedàncies en la tècnica de modulació de càrrega del DPA ("load modulation"). Concretament, l'objectiu futur de disseny d'DPA és disminuir l'impacte d'aquests problemes. En aquest context, aquesta tesi doctoral es centra en millorar l'ample de banda fraccional dels DPA utilitzant nous mètodes que estan relacionats amb l'ús de transformadors d'impedàncies, en comptes d'inversors, en el subcircuit de modulació de càrrega. Aquest treball té dos nivells. En primer lloc, es presenta un DPA novedós que fa servir dispositus GaN DPA a la banda de 2,5 GHz amb un divisor Wilkinson asimètric. El transformador d'impedàncies de l'arquitectura proposada es basa en una xarxa d'adaptació, incloent una línia cònica amb múltiples seccions del transformador en l'etapa principal. El BW d'aquest DPA ha mostrat ser d'1,8 a a 2,7 GHz. A més, s'obté una eficiència de drenador de més del 33% en tot el BW, tant a nivell de potència màxima com de OBO. En segon lloc, sobre la base dels beneficis del adaptador de Klopfenstein, un proposa un nou disseny on un Klopfenstein substitueix la anterior línia cònica. Aquesta substitució repercuteix en la reducció del coeficient de reflexió de transformador d'impedàncies.Des d'una realització pràctica (prototipus) d'aquest nou amplificador tipus Doherty a la banda de 2,25 GHz, s'ha demostrat que el BW resultant s'incrementa en comparació amb la topologia convencional mentre es mantenen les xifres d'eficiència. D'altra banda, en aquest estudi es demostra que el disseny basat en el Klopfenstein permet una afinació fàcil del retard de grup a través de la reactància de sortida de la forma cònica, el que resulta en un ajust més senzill que altres dissenys publicats recentment en què el transformador de quart d'ona es substitueix per multi-línies de transmissió de la secció (híbrids o similar). Els resultats experimentals han mostrat un 43-54% d'eficiència de drenador en 42 dBm de potència de sortida, en l'interval de 1,7-2,75 GHz. Concretament, els resultats presentats en aquest nou amplificador tipus Doherty impliquen una tècnica de modulació de càrrega específic que utilitza una combinació del Klopfenstein juntament amb un transformador de múltiples seccions per tal d'obtenir un alt ample de banda amb la usual eficiència en DPAs.

The FREIA laboratory is a Facility for REsearch Instrumentation and Acceleratior development at Uppsala University, Sweden, constructed recently to test and develop superconducting accelerating cavities and their high power RF sources. FREIA's activity target initially the European Spallation Source (ESS) requirements for testing spoke cavities and RF power stations, typically 400 kW per cavity. Different power stations will be installed at the FREIA laboratory. The first one is based on vacuum tubes and the second on a combination of solid state modules. In this context, we investigate different related aspects, such as power generation and power combination. For the characterization of solid state amplifier modules in pulsed mode, at ESS specifications, we implement a Hot Sparameter measurement set-up, allowing in addition the measurement of different parameters such as gain and efficiency. Two new solid state amplifier modules are designed, constructed and measured at 352 MHz, using commercially available LDMOS transistors. Preliminary results show a drain efficiency of 71 % at 1300 W pulsed output power. The effects of changing quiescent current (IDq) and drain voltage are investigated, aswell as the possibilities to combine several modules together.

Abstract This thesis studies the design methods and properties of supply-modulated switch-mode radio frequency power amplifiers. Besides simulation based studies and theory review, two amplifiers were designed: a discrete MESFET class E amplifier (0.5 W at 1 GHz), and an integrated pHEMT class E-1 amplifier (2.0 W at 1.6 GHz) with an on-chip resonator. The existing design methods of the resonant output network of switching amplifiers were reviewed and some extensions on the handling of nonlinear capacitances were proposed. The effects of varying supply voltage were studied and suggestions were given to minimize Vdd / AM and Vdd / PM distortion in supply modulated amplifiers. The implementation of the bias feed was also discussed resulting in proposing a combination of a short transmission line and a small inductor, which provides both fast supply modulation and little effect on harmonic impedances. The main contributions are related to the study of the input impedance of a class E power amplifier, where the effects of supply dependent input impedance and timing skew generated by injected harmonic distortion were analyzed. The stabilization of the amplifier was also discussed. Based on the findings, a push-pull class E amplifier with extra cross-coupled feedback capacitors and second harmonic traps at the gates appears to be a very good starting point for a further study
Tiivistelmä Tämä väitöstyö käsittelee radiotaajuuksilla toimivien käyttöjännitemoduloitujen kytkintehovahvistimien ominaisuuksia ja suunnittelumenetelmiä. Suunnittelumenetelmiin liittyvän katsauksen ja simulaatioihin perustuvan tutkimusten lisäksi kaksi vahvistinta toteutettiin väitöstutkimuksen aikana: diskreettikomponentein toteutettu E-luokan vahvistin (MESFET, 0.5 W ja 1 GHz) ja integroituna piirinä toteutettu käänteinen E-luokan vahvistin (pHEMT, 2.0 W ja 1.6 GHz), jonka lähdön resonaattoripiiri sisällytettiin integroituun piiriin. Kytkinvahvistimien suunnittelumenetelmiä verrattiin ja kehitettiin edelleen siten, että suunnitteluvaiheessa voidaan ottaa huomioon esim. transistoripiirin takaisinkytkennässä olevan kapasitanssin epälineaarisuus. Työssä tutkittiin myös käyttöjännitemodulaation vaikutusta kytkinvahvistimien toimintaan, ja tutkimuksen tuloksena annettiin muutamia ehdotuksia käyttöjänniteriippuvan amplitudi- (Vdd / AM) ja vaihemodulaation (Vdd / PM) vähentämiseksi. Lähdön biasointipiirin toteutukseen suositeltiin pienen kelan ja siirtolinjan yhdistelmää. Yhdistelmän avulla pyritään maksimoimaan modulaationopeus ja minimoimaan vaikutukset harmonisiin impedansseihin. Pääkohtina väitöksessä ovat E-luokan kytkinvahvistimesta saadut tutkimus- ja mittaushavainnot käyttöjännitteen funktiona muuttuvasta transistorin tuloimpedanssista sekä suurikokoisen transistorin tuloissa tapahtuvan, säröytymisen aiheuttaman tulosignaalien ajoitusvirheen analyysi. Näiden lisäksi vahvistimen stabiilisuuteen kiinnitettiin huomiota. Saatujen havaintojen perusteella voimme todeta, että push-pull -tyyppinen E-luokan vahvistin olisi mielenkiintoinen valinta jatkotutkimuksille

Hybrid Digital/RF Envelope Predistortion Linearization for High Power Amplifiers in Wireless Communication Systems Wangmyong Woo 151 Pages Directed by Dr. J. Stevenson Kenney The objective of this research is to implement a hybrid digital/RF envelope predistortion linearization system for high-power amplifiers used in wireless communication systems. It is well known that RF PAs have AM/AM (amplitude modulation) and AM/PM (phase modulation) nonlinear characteristics. Moreover, the distortion components generated by a PA are not constant, but vary as a function of many input conditions such as amplitude, signal bandwidth, self-heating, aging, etc. Memory effects in response to past inputs cause a hysteresis in the nonlinear transfer characteristics of a PA. This hysteresis, in turn, creates uncertainty in predictive linearization techniques. To cope with these nonlinear characteristics, distortion variability, and uncertainty in linearization, an adaptive digital predistortion technique, a hybrid digital/RF envelope predistortion technique, an analog-based RF envelope predistortion technique, and a combinational digital/analog predistortion technique have been developed. A digital adaptation technique based on the error vector minimization of received PA output waveforms was developed. Also, an adaptive baseband-to-baseband test system for the characterization of RF PAs and for the validation of linearization algorithms was implemented in conjunction with the adaptation technique. To overcome disadvantages such as limited correction bandwidth and the need for a baseband input signal in digital predistortion, an adaptive, wideband RF envelope predistortion system was developed that incorporates a memoryless predistortion algorithm. This system is digitally controlled by a look-up table (LUT). Compared with conventional baseband digital approaches, this predistortion architecture has a correction bandwidth that is from 20 percent to 33 percent wider at the same clock speeds for third to fifth order IMDs and does not need a digital baseband input signal. For more accurate predistortion linearization for PAs with memory effects, an RF envelope predistortion system has been developed that uses a combination of analog-based envelope predistortion (APD) working in conjunction with digital LUT-based adaptive envelope predistortion (DPD). The resulting combination considerably decreases the computational complexity of the digital system and significantly improves linearity and efficiency at high power levels.

This research presents design techniques for a linear power amplifier with high efficiency in wireless handsets. The power amplifier operates with high efficiency at the saturated output power, maintains high linearity with enhanced efficiency at back-off power levels, and covers a broadband frequency response. The amplifier is thus able to operate in multiple modes (2G/2.5G/3G/4G). The design techniques provide contributions to current research in handset power amplifiers, especially to the converged power amplifier architecture, to reduce the number of power amplifiers within the handset while covering all standards and frequency bands around the globe. Three main areas of interest in power amplifier design are investigated: high power efficiency; high linearity; and broadband frequency response. Multiple techniques for improving the efficiency are investigated with the focus on maintaining linear operation. The research applies a new technique to the handset industry, class-J, to improve the power efficiency while avoiding the practical issues that hinder the typical techniques (class-AB and class-F). Class-J has been implemented using GaN FET in high power applications. To our knowledge, this work provides the first implementation of class-J using GaAs HBT in a handset power amplifier. The research investigates the linearity, and the nature and causes of nonlinearities. Multiple concepts for improving the linearity are presented, such as avoiding odd-degree harmonics, and linearizing the relationship between the output current and the input voltage of the amplifier at the fundamental frequency. The concept of bias depression in HBT transistors is introduced with a bias circuit that reduces the bias-offset effect to improve linearity at high output power. A design methodology is presented for broadband matching networks, including the component loss. The methodology offers a quick and accurate estimation of component values, giving more degrees of freedom to meet the design specifications. It enables a trade-off among high out-of-band attenuation, number/size of components, and power loss within the network. Although the main focus is handset power amplifiers, most of the developed techniques can be applied to a wide range of power amplifiers.
Ph. D.

This thesis discusses the design, construction and testing of a highefficiency, 100 MHz, 1 kW, Class-E solid state power amplifier. The design was performed with the aid of computer simulations using electronic design software (ADS). The amplifier was constructed around Ampleon's BLF188XR LDMOS transistor in a single ended design. The results for 100 MHz operation show a power added efficiency of 82% at 1200 W pulsed power output. For operation at 102 MHz results show a power added efficiency of 86% at 1050 W pulsed power output. Measurements of the drain- and gate voltage waveforms provide validation of Class-E operation.

The evolution of high power transistors has ultimately increased the complexity of their design, interaction and incorporation within microwave frequency power amplifiers. The requirement for high efficiency and high linearity for a wide band frequency by the consumer has put pressure on designers. Due to unexpected and unpredictable failures, device characterisation of the transistor in operational conditions is a highly valuable advantage. The proposed work will describe a non-intrusive, ultra-miniaturised, high resolution electric field probe system; with the capability of measuring relative voltage and waveforms distribution of complex active devices within their operating conditions. The design, construction and evolution of the probing system will be described displaying a resolution of better than 100μm, with a flat frequency response of up to 8GHz. Due to the miniaturised size and the flexibility in positioning, the probe has the ability to measure on-chip, at the device plane, across the device periphery. Results will show direct observation of device plane voltages in high power RFPAs, where the device can exhibit variation in the voltage distribution across the periphery. Such variation will be a function of the internal behaviour and not evident in the output characteristics of the device. This work will also describe a novel method for absolute calibration of the probing system which can be implemented with every movement of the measurement plane. Therefore presenting a successful and calibrated EFP system capable of device characterisation and diagnostics.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 91-92).
In this thesis, I addressed issues arising in the design of a high efficiency RF power amplifier for the Draper Laboratory multi-chip module (MCM) process. A design for a 2.3 GHz PCB amplifier using an enhancement-mode pHEMT device that achieves 68.9% PAE at 30 dBm output power is presented. Analysis of heat management, die connection parasitics, and transmission line structures in the context of the MCM process is performed to show that a similar design could realistically be adapted to the MCM process with possible performance enhancement.
by James Noonan.
M.Eng.

As the oil industry continues to drill deeper to reach previously untapped wells, the operating environments for electronic systems become harsher, especially due to high temperatures. It is essential to design electronic circuits and systems to be able to withstand these extreme temperatures. The proposed power amplifier (PA) has been designed for a downhole communication system operating at an ambient temperature of 230oC. GaN technology was chosen primarily due to its ability to function at a high junction temperature. The proposed PA was designed with Qorvo's T2G6003028-FL HEMT as it operates reliably at a high junction temperature (T_J) and also the package offers low junction to case thermal resistance . The proposed PA can operate reliably up to an ambient temperature of 230oC using passive cooling opposed to active cooling. At 230 C it operates in class A with a peak PAE of 25.03%, maximum output power of 1.66 W, peak gain of 24.5 dB, center frequency of 255 MHz with 1dB ripple in the passband over a 60 MHz bandwidth, 1dB output compression of approximately 32 dBm, and OIP3 of 37.9dBm. CW measurements were taken for all parameters.
Master of Science

This thesis is concerned with the design and implementation of radio frequency (RF) power amplifiers and micro-electromechanical systems---namely MEMS varactors. This is driven by the many wireless communication systems which are constantly moving towards increased integration, better signal quality, and longer battery life.
The power amplifier consumes most of the power in a receiver/transmitter system (transceiver), and its output signal is directly transmitted by the antenna without further modification. Thus, optimizing the PA for low power consumption, increased linearity, and compact integration is highly desirable.
Micro-electromechanical systems enable new levels of performance in radio-frequency integrated circuits, which are not readily available via conventional IC technologies. They are good candidates to replace lossy, low Q-factor off-chip components, which have traditionally been used to implement matching networks or output resonator tanks in class AB, class F, or class E power amplifiers. The MEMS technologies also make possible the use of new architectures, with the possibility of flexible re-configurability and tunability for multi-band and/or multi-standard applications.
The major effort of this thesis is focused on the design and fabrication of an RF frequency class AB power amplifier in the SiGe BiCMOS 5HP technology, with the capability of being tuned with external MEMS varactors. The latter necessitated the exploration of wide-tuning range MEMS variable capacitors, with prototypes designed and fabricated in the Metal-MUMPS process.
An attempt is made to integrate the power amplifier chip and the MEMS die in the same package to provide active tuning of the power amplifier matching network, in order to keep the efficiency of the PA constant for different input power levels and load conditions.
Detailed simulation and measurement results for all circuits and MEMS devices are reported and discussed.

Abstract

In this thesis, a measurement system was set to perform comprehensive measurements on RF power amplifiers. Data obtained from the measurements is then processed mathematically to obtain three dimensional graphs of the basic parameters affected or generated by nonlinearities of the amplifier i.e. gain, efficiency and distortion. Using a class AB amplifier as the DUT, two sets of signals – both swept in power level and frequency - were generated to validate the method, a two-tone signal and a WCDMA signal. The three dimensional plot gives a thorough representation of the behavior of the amplifier in any arbitrary range of spectrum and input level. Sweet spots are consequently easy to detect and analyze. The measurement setup can also yield other three dimensional plots of variations of gain, efficiency or distortion versus frequencies and input levels. Moreover, the measurement tool can be used to plot traditional two dimensional plots such as, input versus gain, frequency versus efficiency etc, making the setup a practical tool for RF amplifiers designers.

The test signals were generated by computer then sent to a vector signal generator that generates the actual signals fed to the amplifier. The output of the amplifier is fed to a vector signal analyzer then collected by computer to be handled. MATLAB® was used throughout the entire process.

The distortion considered in the case of the two-tone signals is the third order intermodulation distortion (IM3) whereas Adjacent Channel Power Ratio (ACPR) was considered in the case of WCDMA.

Measurements are important to specify and verify properties for components, modules and systems. The specifications for a certain figure of merit are usually given in a numerical value or a two dimensional plot. However, there are some devices, like power amplifiers with certain figure of merits that depends on two or more working conditions, requiring a three dimensional plot.

This thesis presents a measurement method including graphical user interface of three parameters gain, efficiency and distortion when two-tone or WCDMA signals are used as an input to the PA.

The objective of this research work is to investigate, design and measurement of a digital predistortion linearizer that is able to compensate the dynamic nonlinear distortion of a High Power Amplifier (PA). The effectiveness of the proposed baseband predistorter (PD) on the performance of a WLAN OFDM transmitter utilizing a nonlinear PA with memory effect is observed and discussed. For this purpose, a 10W Class-A/B power amplifier with a gain of 22 dB, operated over the 3.5 GHz frequency band was designed and implemented. The proposed baseband PD is independent of the operating RF frequency and can be used in multiband applications. Its operation is based on the Hammerstein system, taking into account PA memory effect compensation, and demonstrates a noticeable improvement compared to memoryless predistorters. Different types of modelling procedures and linearizers were introduced and investigated, in which accurate behavioural models of Radio Frequency (RF) PAs exhibiting linear and nonlinear memory effects were presented and considered, based on the Wiener approach employing a linear parametric estimation technique. Three new linear methods of parameter estimation were investigated, with the aim of reducing the complexity of the required filtering process in linear memory compensation. Moreover, an improved wiener model is represented to include the nonlinear memory effect in the system. The validity of the PA modelling approaches and predistortion techniques for compensation of nonlinearities of a PA were verified by several tests and measurements. The approaches presented, based on the Wiener system, have the capacity to deal with the existing trade-off between accuracy and convergence speed compared to more computationally complex behavioural modelling algorithms considering memory effects, such as those based on Volterra series and Neural Networks. In addition, nonlinear and linear crosstalks introduced by the power amplifier nonlinear behaviour and antennas mutual coupling due to the compact size of a MIMO OFDM transmitter have been investigated.

The aim of the master´s thesis is to create a high-frequency amplifier with switching power amplifier classes among classes A, B, C with output power of 10 W. The amplifier operates at frequency from 3.5 MHz to 14 MHz. Master´s thesis includes also theoretical analysis, design of lowpass filter and amplifiers and their simulation, mechanical realization and measured parameters of the amplifier.

The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions. The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies. This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals. The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology. The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated. The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals. The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion. The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB.

PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO
Este trabalho descreve o desenvolvimento completo de um Amplificador de Potência de RF para Transceptores Multibanda. Em sua etapa inicial mostra um apanhado geral da teoria de todos os parâmetros relevantes para a medida de desempenho desses dispositivos, como potência, ganho e parâmetros de não linearidades. Em seguida são expostas as teorias básicas para o entendimento dos mecanismos para extração da máxima potência de um transistor, focando nos transistores de efeito de campo FET, incluindo a caracterização para regimes de alta potência. São apresentados os modos de operação de um amplificador de potência, focando nos chamados modos clássicos, dado que esses modos são convenientes para operação em banda larga. Para a correta operação de qualquer dispositivo que apresente ganho, a análise de estabilidade é apresentada com o procedimento de estabilização de transistores. A partir de todo o apanhado teórico, é desenvolvida uma metodologia de projeto de amplificadores de potência utilizando a ferramenta de simulação computacional Advanced Design System. Então, após toda a modelagem do amplificador, a construção e medidas são realizadas e boa concordância com a simulação foi obtida.
This work describes the full development of a RF Power Amplifier for Multiband Transceivers. In its initial stage shows an overview of the theory of all relevant parameters to measure the performance of these devices, like power, gain and nonlinearity parameters. Then it exposes the basic theories for the understanding of the mechanisms for extracting the maximum power of a transistor, focusing on field effect transistors FET, including characterization for regimes of high power. It presents the modes of operation of a power amplifier, focusing on so-called classical modes, since these modes are suitable for broadband operation. For proper operation of any device that presents gain, the stability analysis is presented with the stabilization procedure of transistors. From all theoretical basis, is developed a design methodology of power amplifiers using the computational simulation tool Advanced Design System. So after all the amp modeling, construction and measurements are performed and good agreement was obtained with the simulation.

As the mobile phone is an essential accessory for everyone nowadays, predistortion for the RF power amplifiers in mobile phone systems becomes more and more popular. Especially, new predistortions for power amplifiers with both nonlinearities and memory effects interest the researchers. In our thesis, novel predistortion techniques are presented for this purpose. Firstly, we improve the digital injection predistortion in the frequency domain. Secondly, we are the first authors to propose a novel predistortion, which combines digital LUT (Look-up Table) and injection. These techniques are applied to both two-tone tests and 16 QAM (Quadrature Amplitude Modulation) signals. The test power amplifiers vary from class A, inverse class E, to cascaded amplifier systems. Our experiments have demonstrated that these new predistortion techniques can reduce the upper and lower sideband third order intermodulation products in a two-tone test by 60 dB, or suppress the spectral regrowth by 40 dB and reduce the EVM (Error Vector Magnitude) down to 0.7% rms in 16 QAM signals, disregarding whether the tested power amplifiers or cascade amplifier systems exhibit significant nonlinearities and memory effects. i

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 95-98).
Electrical stresses in the transistors of high-efficiency switching power amplifiers can lead to hot-electron-induced "breakdown" in these devices. This thesis explores issues related to breakdown in the Transcom TC2571 PHEMT, and the effects this has on the Draper Laboratory 2.3 GHz microwave power amplifier in which the transistor is used. Characterization of breakdown was performed under DC and RF drive conditions, and shows the surprising role of impact ionization at low temperatures in DC off-state breakdown, as well as the apparent prevalence of on-state breakdown under RF drive. DC characterization shows that breakdown walkout and recovery both proceed more quickly at higher temperatures, and also shows that breakdown stress might lead to the permanent creation of traps that degrade breakdown voltage. Walkout under RF drive decreases amplifier gain at lower levels of RF input drive, but appears to have no negative effect on amplifier saturated output power. The use of temperature-compensated input drive and a diode to clamp negative gate voltage swing are also explored as circuit design techniques that can mitigate device degradation due to breakdown stress.
by Gautham Venkat Arumilli.
M.Eng.

Thesis (MTech(Electrical Engineering))--Cape Peninsula University of Technology, 2006.
Electronic communication systems have become an integral part of our everyday lives. RF (Radio Frequency) power amplifiers form part of the fundamental building blocks of an electronic communication system. RF power amplifiers can also be one of the major causes of distortion in an electronic communication system. This thesis describes the linearity requirement for a RF power amplifier that is used in a transmitter section of an electronic communication system. Furthermore, five different linearisation techniques are presented and their characteristics compared. Since a power amplifier employing the Feedforward linearisation technique was designed, built and tested, this thesis focuses on the Feedforward technique. The design methods for the various Feedforward components are presented. The measured parameters of the Feedforward linearised amplifier are compared with the measured parameters of a non-linearised amplifier.

The objective of this research work is to investigate, design and measurement of a digital predistortion linearizer that is able to compensate the dynamic nonlinear distortion of a High Power Amplifier (PA). The effectiveness of the proposed baseband predistorter (PD) on the performance of a WLAN OFDM transmitter utilizing a nonlinear PA with memory effect is observed and discussed. For this purpose, a 10W Class-A/B power amplifier with a gain of 22 dB, operated over the 3.5 GHz frequency band was designed and implemented. The proposed baseband PD is independent of the operating RF frequency and can be used in multiband applications. Its operation is based on the Hammerstein system, taking into account PA memory effect compensation, and demonstrates a noticeable improvement compared to memoryless predistorters. Different types of modelling procedures and linearizers were introduced and investigated, in which accurate behavioural models of Radio Frequency (RF) PAs exhibiting linear and nonlinear memory effects were presented and considered, based on the Wiener approach employing a linear parametric estimation technique. Three new linear methods of parameter estimation were investigated, with the aim of reducing the complexity of the required filtering process in linear memory compensation. Moreover, an improved wiener model is represented to include the nonlinear memory effect in the system. The validity of the PA modelling approaches and predistortion techniques for compensation of nonlinearities of a PA were verified by several tests and measurements. The approaches presented, based on the Wiener system, have the capacity to deal with the existing trade-off between accuracy and convergence speed compared to more computationally complex behavioural modelling algorithms considering memory effects, such as those based on Volterra series and Neural Networks. In addition, nonlinear and linear crosstalks introduced by the power amplifier nonlinear behaviour and antennas mutual coupling due to the compact size of a MIMO OFDM transmitter have been investigated.

The objective of this research is to develop, characterize, and demonstrate novel parametric architectures capable of wideband operation while maintaining high gain and stability. To begin the study, phase-incoherent upconverting parametric amplifiers will be explored by first developing a set of analytical models describing their achievable gain and efficiency. These models will provide a set of design tools to optimize and evaluate prototype circuit boards. The prototype boards will then be used to demonstrate their achievable gain, bandwidth, efficiency, and stability. Further investigation of the analytical models and data collected from the prototype boards will conclude bandwidth and gain limitations and end the investigation into phase-incoherent upconverting parametric amplifiers in lieu of negative-resistance parametric amplifiers. Traditionally, there were two versions of negative-resistance parametric amplifiers available: degenerate and non-degenerate. Both modes of operation are considered single-frequency amplifiers because both the input and output frequencies occur at the source frequency. Degenerate parametric amplifiers offer more power gain than their non-degenerate counterpart and do not require additional circuitry for idler currents. As a result, a phase-coherent degenerate parametric amplifier printed circuit board prototype will be built to investigate achievable gain, bandwidth, and stability. Analytical models will be developed to describe the gain and efficiency of phase-coherent degenerate parametric amplifiers. The presence of a negative resistance suggests the possibility of instability under certain operating conditions, therefore, an in-depth stability study of phase-coherent degenerate parametric amplifiers will be performed. The observation of upconversion gain in phase-coherent degenerate parametric amplifiers will spark investigation into a previously unknown parametric architecture: phase-coherent upconverting parametric amplifiers. Using the phase-coherent degenerate parametric amplifier prototype board, stable phase-coherent upconversion with gain will be demonstrated from the source input frequency to its third harmonic. An analytical model describing the large-signal transducer gain of phase-coherent upconverting parametric amplifiers from the first to the third harmonic of the source input will be derived and validated using the prototype board and simulations.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Laskar, Joy; Committee Member: Cressler, John; Committee Member: Kohl, Paul; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanouil. Part of the SMARTech Electronic Thesis and Dissertation Collection.

This thesis focuses on class A radio frequency power amplifiers in dynamic supply modulation architectures (dynamic bias). These are promising efficiency enhancement techniques where the device is driven harder by varying its bias signals. Non linearities that arise are considered as digitally compensated through, for example, digital predistortion (DPD). Bias signals are meant as functions of the PA?s output power level (P out). Therefore, the input power level (P in) as well as the feeding signals are thought as quantities the amplifier need to give a certain P out. The selected set of bias points the device sweeps through is called bias trajectory or bias path. A tool to find a suitable bias trajectory is developed considering the requirements a class A power amplifier should satisfy: high power added efficiency, acceptable gain and output phase variations as P out changes (allowing a DPD algorithm to be effective), low harmonic distortion and not too complicated bias signals patterns. The tool consists of two softwares: ADS and Matlab. ADS simulates the device under test while Matlab allows the user to analyze the data and find a suitable bias path. Once a trajectory is identified, ADS can sweep along it and give more information on linearity and efficiency through, for instance, 2-tone harmonic balance simulations. Note that only static characteristics are evaluated and memory effects disregarded. The path searching algorithm is then applied to a HBT transistor, at a frequency of 1.9GHz and to a complete pHEMT class A PA (frequency of 6Ghz). In both cases a suitable trajectory is identified and analyzed back in ADS. The Matlab plots are qualitatively similar to each other when switching form one device to another. The HBT transistor has then been tested in the laboratory and static measurements have been performed showing good agreement with simulations. Keywords: Bias trajectory, dynamic bias, efficiency, HBT, linearity, pHEMT, power amplifier

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 micrometer] technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA's RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.
ID: 029809372; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.)--University of Central Florida, 2011.; Includes bibliographical references.
M.S.
Masters
Electrical Engineering and Computer Science
Engineering and Computer Science

In this thesis we introduce a two-way Doherty amplifier architecture with multiple feedbacks for digital predistortion based on impedance-inverting directional coupler (transcoupler). The tunable two-way Doherty amplifier with a tuned circulator-based impedance inverter is presented. Compact N-way Doherty architectures that subsume impedance inverter and offset line functionality into output matching networks are derived. Comprehensive N-way Doherty amplifier design and analysis techniques based on load-pull characterization of active devices and impedance modulation effects are developed. These techniques were then applied to the design of a two-way Doherty amplifier and a three-way Doherty amplifier which were manufactured and their performance measured and compared to the amplifier performance specifications and simulated results.

In recent years, tremendous growth of the wireless market can be defined through the following words: smartphone and high-data rate wireless communication. This situation gives new challenges to RF power amplifier design, which includes high-efficiency, multi-band operation, and robustness to antenna mismatch conditions. In addition to these issues, the industry and consumers demand a low-cost small-sized wireless device. A fully integrated single-chip CMOS transceiver is the best solution in terms of cost and level of integration with other functional blocks. Therefore, the effective approaches in a CMOS process for the abovementioned hurdles are highly desirable. In this dissertation, the new challenges are overcome by introducing adaptability to a CMOS power amplifier. Meaningful achievements are summarized as follows. First, a new CMOS switched capacitor structure for high power applications is proposed. Second, a dual-mode CMOS PA with an integrated tunable matching network is proposed to extend battery lifetime. Third, a switchless dual-band matching structure is proposed, and the effectiveness of dual-band matching is demonstrated with a fully-integrated CMOS PA. Lastly, a reconfigurable CMOS PA with an automatic antenna mismatch recovery system is presented, which can maintain its original designed performance even under various antenna mismatch conditions. Conclusively, the research in this dissertation provides various solutions for new challenges of advanced mobile terminals.

This thesis presents the design process of a class E RF power amplifier and a transmitter in a standard CMOS technology. CMOS radio frequency class-E power amplifiers (PA) for GMSK/GFSK modulations have been designed and fabricated using 0.25/0.35mum technologies. The operating frequencies are centered at 1.2GHz and 2.65GHz with 24--26dBm output power. In order to reduce the driving requirement, mode locking techniques are employed for both designs. High efficiency broadband off-chip hybrid ring baluns are used at both input and output for converting signals from single-ended to differential and vice versa. Regular bonding wires are used as inductors for the 1.2GHz PA, and on-chip bondwires are used for the 2.65GHz PA. With a 1.3V supply, the measured power added efficiency (PAE) of the 1.2GHz PA, after taking into account the losses in the baluns, is 62%. The PAE for the 2.65GHz PA is 38% when operated from a 1.7V power supply. Furthermore, a transmitter stage for 5.5GHz frequency application has been designed and simulated using a 0.18mum CMOS technology. The design and layout is completed, with a simulation frequency of 5.9GHz and an output signal of 7dBm.

Background:

The task of this thesis is to investigate the possibility of using non-linear high efficiency switching power amplifiers with spectrally efficient varying envelope modulation schemes and, if possible, further investigate such a solution on a high level.

The thesis focuses on the theory necessary to understand the technical issues related to power amplifiers and the procedures behind simulating and measuring the characteristics of different power amplifier configurations. The thesis also covers basic theory behind Delta-Sigma-modulators. The theory is needed to draw conclusions about the feasibility of using a Delta-Sigma-modulator as input to a switching amplifier.

Results:

Using a Delta-Sigma-modulated input to a switching amplifier inherently degrades the performance, mainly because of poor coding efficiency and high switching activity. However, by merely using a switching amplifier as a mixer it is shown to be possible to transmit a non-constant envelope signal, with digital logic. The resulting circuit is, however, not an amplifier and it should not be seen as the final result. As already mentioned: the result lies in the investigation of a using Delta-Sigma-modulator as input to a switching amplifier.

Conclusion:

From this investigation we believe that the widely known technique: pulse width modulation (PWM), together with a tuned switching amplifier and some linearization technique, for example pre-distortion, is a better way to go. Much effort should be put in understanding the fundamental limits and possibilities of an efficient tuned switching power amplifier.

Development of linear modulation schemes has opened the way for spectrally efficient, high speed digital communication systems for voice and data applications. A trend has been to develop ultra wide and wide bandwidth modulation formats, which has meant feedback linearisation schemes (both analogue and digital) are no longer effective. This has in turn led to a number of approaches that involve predistorting the signal prior to amplification, with a characteristic that is the inverse to that of the power amplifier (PA). This thesis presents a polynomial based predistortion for linearisation of an RF PA. The predistortion characteristic is adaptive, using the LMS algorithm to minimise the mean squared error between output of the PA, and a scaled version of the baseband signal. This system can reduce third-order intermodulation by 40 dB when running in real time.

The demands for high data rates and broadband wireless access require the development of wireless systems that can support wide and multi-band signals. To deploy these signals, new radio frequency (RF) front-ends are required which impose new challenges in terms of power consumption efficiency and sources of distortion e.g., nonlinearity. These challenges are more pronounced in power amplifiers (PAs) that degrade the overall performance of the RF transmitter. Since it is difficult to optimize the linearity and efficiency characteristics of a PA simultaneously, a trade-off is needed. At high input power, a PA exhibits high efficiency at the expense of linearity. On the other hand, at low input power, a PA is linear at the expense of the efficiency. To achieve linearity and efficiency at the same time, digital pre-distortion (DPD) is often used to compensate for the PA nonlinearity at high input power. In case of multi-channel PAs, input and output signals of different channels interact with each other due to cross-talk. Therefore, these PAs exhibit different nonlinear behavior than the single-input single-output (SISO) PAs. The DPD techniques developed for SISO PAs do not result in adequate performance when used for multi-channel PAs. Hence, an accurate behavioral modeling is essential for the development of DPD for multi-channel RF PAs. In this thesis, we propose three novel behavioral models and DPD schemes for nonlinear multiple-input multiple-output (MIMO) transmitters in presence of cross-talk. A study of the source of cross-talk in MIMO transmitters have been investigated to derive simple and powerful modeling schemes. These models are extensions of a SISO generalized memory polynomial model. A comparative study with a previously published MIMO model is also presented. The effect of coherent and partially non-coherent signal generationon DPD performance is also highlighted. It is shown experimentally that with partially non-coherent signal generation, the performance of the DPD degrades compared to coherent signal generation. In context of multi-channel RF transmitters, PA behavioral models and DPD schemes suffer from a large number of model parameters with the increase in nonlinear order and memory depth. This growth leads to high complexity model identification and implementation. We have designed a DPD scheme for MIMO PAs using a sparse estimation technique for reducing model complexity. This technique also increases the numerical stability when linear least square estimation model identification is used. A method to characterize the memory effects in a nonlinear concurrent dual-band PAs is also presented. Compared to the SISO PAs, concurrent dual-band PAs are not only affected by intermodulation distortions but also by cross-modulation distortions. The characterization of memory effects inconcurrent dual-band transmitter is performed by injecting a two-tone test signal in each input channel of the transmitter. Asymmetric energy surfaces are introduced for the intermodulation and cross-modulation products, which can be used to identify the power and frequency regions where the memory effects are dominant.

QC 20141217

Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais.
This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

In modern wireless communication systems, advanced modulation techniques are used to support more users by handling high data rates and to increase the utilization efficiency of the limited RF spectrum. These techniques are sensitive to the nonlinear distortions due to their high peak to average power ratios. Main source of nonlinear distortion in transmitter topologies are power amplifiers that determine the overall efficiency and linearity of the transmitter. To increase linearity without sacrificing efficiency, power amplifier linearization techniques may be a choice. Baseband predistortion technique is known to be one of the optimum methods due to its relatively low complexity and its convenience for adaptation. In this thesis, different memoryless baseband signal predistortion methods are investigated and analyzed by simulations. Look-Up Table(LUT) and Polynomial approaches are compared and LUT approach is found to be better in performance. Parameters, like indexing, training sequences and training duration are evaluated. An open loop testbench is built with a real amplifier and a different LUT predistortion method that is based on amplifier modeling is offered. It is evaluated by using two tone test and adjacent channel power suppression with 8PSK data. Also, some Look-Up Table parameters are re-investigated with the proposed method. The performances of the proposed method in dierent amplifier classes are observed. Along with these studies, a list of prerequisites for design of a predistortion system is determined.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 123-126).
Power amplifiers are the circuit blocks in wireless transceivers that require the largest power budget because of their relatively low efficiencies. RF designers cannot depend solely on the development better semiconductor devices in advanced deeply scaled process technologies to obtain improved power amplifier performance. The development of new and better circuits, architectures and design methodologies to maximally exploit the available semiconductor devices is very important as well. This thesis investigates a number of techniques that can be used to improve the efficiency of power amplifiers and break the power-frequency tradeoff in power amplifier design. The first technique emphasizes the use of a class E tuned output network as an efficiency enhancement tool for power amplifiers regardless of their bias conditions. A Class E tuned CMOS power amplifier (PA) operating in the 60 GHz band was designed. Design, layout, and parasitic modeling considerations to attain high-efficiency millimeter-wave PA operation are discussed. Both single-ended and differential versions of the single-stage PA were implemented in a 32 nm SOI CMOS process. Peak power added efficiency of 27% (30%), power gain of 8.8 dB (10 dB), and saturated output power > 9 dBm (12.5 dBm) were measured at 60 GHz from the single-ended (differential) PA with 0.9 V supply. The second technique investigated the efficacy of resistance compression networks in an energy recycling network operating at multi-gigahertz frequencies. The resistance compression network reduces the variation in resonant rectifier input impedance seen at the isolation port of an isolating power combiner. The system was operated at 2.14 GHz and was built around Schottky barrier diodes custom fabricated in a 0.13 [mu]m CMOS process. It is the first experimental demonstration that resistance compression networks can be used for energy recycling in multi-gigahertz applications.
by Olumuyiwa Temitope Ogunnika.
Ph.D.