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Academic literature on the topic 'REVERSE CARRY PROPAGATE ADDER'

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Published: 11 September 2023

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Journal articles on the topic "REVERSE CARRY PROPAGATE ADDER"

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Pashaeifar, Masoud, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 11 (November 2018): 2530–41. http://dx.doi.org/10.1109/tvlsi.2018.2859939.

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Arulkarthick, V. J., and Abinaya Rathinaswamy. "Delay and area efficient approximate multiplier using reverse carry propagate full adder." Microprocessors and Microsystems 74 (April 2020): 103009. http://dx.doi.org/10.1016/j.micpro.2020.103009.

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Kumre, Laxmi, Ajay Somkuwar, and Ganga Agnihotri. "Power Efficient Carry Propagate Adder." International Journal of VLSI Design & Communication Systems 4, no. 3 (June 30, 2013): 125–34. http://dx.doi.org/10.5121/vlsic.2013.4312.

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Lin, Yu Shen, and Damu Radhakrishnan. "Delay Efficient 32-Bit Carry-Skip Adder." VLSI Design 2008 (April 2, 2008): 1–8. http://dx.doi.org/10.1155/2008/218565.

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18 faster than the current fastest carry-skip adder.
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Escribá, J., and J. A. Carrasco. "Self-timed Manchester chain carry propagate adder." Electronics Letters 32, no. 8 (1996): 708. http://dx.doi.org/10.1049/el:19960512.

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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (March 25, 2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.
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Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.
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Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction in comparison of the traditional Carry Look-Ahead Adder (CLA).
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Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (May 15, 2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.
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Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

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Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.
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Dissertations / Theses on the topic "REVERSE CARRY PROPAGATE ADDER"

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CHOUDHARY, DIVYA. "NEW REVERSE CARRY PROPAGATE ADDER USING MODIFIED GDI TECHNIQUE." Thesis, 2019. http://dspace.dtu.ac.in:8080/jspui/handle/repository/16711.

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Addition is the most important function in arithmetic and logical operations. Approximate Computing can be used to reduce the number of transistors, delay and power constraints in VLSI design, which makes the use of approximate adders possible in error-tolerant applications. Existing Approximate Reverse Carry Propagate Adder designs [1] have proved to be advantageous in improving these constraints. A new design of Reverse Carry Propagate Adder has been proposed using Modified-Gate Diffusion Input (GDI) technique [7]. A 4-bit Multiplier has also been designed using this RCPFA and results verified with Xilinx Tool. Proposed circuit design simulations have been carried out in 45-nm process technology using Cadence Virtuoso. The results indicate 57% and 44% reduction in Power and Delay respectively.
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Book chapters on the topic "REVERSE CARRY PROPAGATE ADDER"

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Naresh, B., K. Aruna Manjusha, and U. Somanaidu. "Design of Low-Power Reverse Carry Propagate Adder Using FinFET." In Algorithms for Intelligent Systems, 473–87. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1669-4_42.

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Conference papers on the topic "REVERSE CARRY PROPAGATE ADDER"

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Bhavani, N. S. V. S. Ganga, and M. Vinodhini. "High Performance Accurate Multiplier using Hybrid Reverse Carry Propagate Adder." In 2022 6th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2022. http://dx.doi.org/10.1109/iceca55336.2022.10009577.

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V. S, Muralikrishna, and oselin Kavitha M. J. "A High-Speed, Area-Efficient Transfer Method Using a Reverse Carry Propagate Adder." In The International Conference on scientific innovations in Science, Technology, and Management. International Journal of Advanced Trends in Engineering and Management, 2023. http://dx.doi.org/10.59544/jjjn7780/ngcesi23p115.

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The most important component of any electronic device has historically been the arithmetic and logic unit. An efficient algorithmic function, such as addition and multiplication, which is required for an arithmetic as well as logic unit to be significant in the current improvement. For performing modular arithmetic in several cryptography and pseudorandom bit generator (PRBG) algorithms, the three-operand binary adder is the fundamental functional unit. In this paper, this study purposes a reverse carry propagate adder A carry input signal is more important than the carry output signal because, in the RCPA structure, the carry signal flows counter-clockwise from the most significant bit to the least significant bit. In the presence of delay changes, this carry propagation technique results in greater stability. Three implementations of the reverse carry propagate full-adder cell with different delay, power, energy, and accuracy levels are introduced by this study.As a result, it continues as one of the greatest options for creating huge arithmetic circuits with little increase in area and minimal power and energy usage.
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V. S, Muralikrishna, and Joselin Kavitha M. "A High-Speed, Area-Efficient Transfer Method Using a Reverse Carry Propagate Adder." In The International Conference on scientific innovations in Science, Technology, and Management. International Journal of Advanced Trends in Engineering and Management, 2023. http://dx.doi.org/10.59544/ueyi4889/ngcesi23p117.

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The most important component of any electronic device has historically been the arithmetic and logic unit. An efficient algorithmic function, such as addition and multiplication, which is required for an arithmetic as well as logic unit to be significant in the current improvement. For performing modular arithmetic in several cryptography and pseudorandom bit generator (PRBG) algorithms, the three-operand binary adder is the fundamental functional unit. In this paper, this study purposes a reverse carry propagate adder A carry input signal is more important than the carry output signal because, in the RCPA structure, the carry signal flows counter-clockwise from the most significant bit to the least significant bit. In the presence of delay changes, this carry propagation technique results in greater stability. Three implementations of the reverse carry propagate full-adder cell with different delay, power, energy, and accuracy levels are introduced by this study.As a result, it continues as one of the greatest options for creating huge arithmetic circuits with little increase in area and minimal power and energy usage.
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Garg, Bharat, and Yashoda Bisht. "A Novel High Performance Reverse Carry Propagate Adder for Energy Efficient Multimedia Applications." In 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS). IEEE, 2019. http://dx.doi.org/10.1109/ises47678.2019.00073.

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Sedhumadhavan, A., S. Sabariesh, V. Shanmathi, K. Ramya, R. Venukumar, and J. Ajayan. "Study of Performance Comparison of Static and Dynamic Approximate Reverse Carry Propagate Adder Using 22 nm CMOS Technology." In 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS). IEEE, 2020. http://dx.doi.org/10.1109/icaccs48705.2020.9074311.

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Singh, Shalini, Pavan Kumar Pothula, and Madhav Rao. "Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders." In 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2022. http://dx.doi.org/10.1109/isvlsi54635.2022.00015.

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Singh, Varun Pratap, and Manish Rai. "Reversible adder-subtractor circuit with carry and borrow propagate facility." In 2017 3rd International Conference on Advances in Computing, Communication & Automation (ICACCA) (Fall). IEEE, 2017. http://dx.doi.org/10.1109/icaccaf.2017.8344704.

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Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor." In 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2022. http://dx.doi.org/10.1109/mcsoc57363.2022.00011.

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Dipto, Md Ashik Zafar, Afran Sorwar, Elias Ahammad Sojib, and Md Mostak Tahmid Rangon. "Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms." In 2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT). IEEE, 2020. http://dx.doi.org/10.1109/icccnt49239.2020.9225667.

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Wu, Weishu, Scott Campbell, and Pochi Yeh. "Implementation of a multiwavelength optical full-adder." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.mzz.10.

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A multiwavelength half adder was recently proposed and demonstrated1. In this paper, we propose a multiwavelength full adder to avoid the repeat of the SUM and CARRY operations. Similar to the half adder, discrete wavelengths are used to represent specific bits in a binary word. Bits are ‘1’ if power at their wavelength is present, or ‘0’ if not. To simultaneously compute the SUM, which is achieved using a Mach-Zahnder interferometer XOR gate, it is necessary to determine all the carries in advance. One way to achieve this carry look-ahead is to first obtain the original carries as in the case of the half adder. A given original carry will then propagate through the next higher bit if either number is ‘ 1 ’ at that bit, and such propagation continues until both input bits are ‘0’.2 Using these original carries and the input beams from (A+B) as the two writing beam sets into a second crystal, the propagation of these carries can be achieved. In a second approach, all the carries can be generated in a single crystal by appropriately re-injecting the original carries back into the crystal. The pathlengths of the writing beams and reinjected beams are carefully arranged so that interference can be only achieved between the desired beam pairs.
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