Journal articles: 'Resistive memories (RRAMs)'

1

Kim, Kyoungdu, Woongki Hong, Changmin Lee, Won-Yong Lee, Do Won Kim, Hyeon Joong Kim, Hyuk-Jun Kwon, Hongki Kang, and Jaewon Jang. "Sol-gel-processed amorphous-phase ZrO₂ based resistive random access memory." Materials Research Express 8, no. 11 (November 1, 2021): 116301. http://dx.doi.org/10.1088/2053-1591/ac3400.

Full text

Abstract:

Abstract In this study, sol–gel-processed amorphous-phase ZrO2 was used as an active channel material to improve the resistive switching properties of resistive random access memories (RRAMs). ITO/ZrO2/Ag RRAM devices exhibit the properties of bipolar RRAMs. The effect of the post-annealing temperature on the electrical properties of the ZrO2 RRAM was investigated. Unlike the ZrO2 films annealed at 400 and 500 °C, those annealed at 300 °C were in amorphous phase. The RRAM based on the amorphous-phase ZrO2 exhibited an improved high-resistance state (HRS) to low-resistance state ratio (over 106) as well as promising retention and endurance characteristics without deterioration. Furthermore, its disordered nature, which causes efficient carrier scattering, resulted in low carrier mobility and the lowest leakage current, influencing the HRS values.

APA, Harvard, Vancouver, ISO, and other styles

2

Lin, Wu, and Chen. "Effects of Sm2O3 and V2O5 Film Stacking on Switching Behaviors of Resistive Random Access Memories." Crystals 9, no. 6 (June 19, 2019): 318. http://dx.doi.org/10.3390/cryst9060318.

Full text

Abstract:

: In this work, the resistive switching characteristics of resistive random access memories (RRAMs) containing Sm2O3 and V2O5 films were investigated. All the RRAM structures made in this work showed stable resistive switching behavior. The High-Resistance State and Low-Resistance State of Resistive memory (RHRS/RLRS) ratio of the RRAM device containing a V2O5/Sm2O3 bilayer is one order of magnitude higher than that of the devices containing a single layer of V2O5 or Sm2O3. We also found that the stacking sequence of the Sm2O3 and V2O5 films in the bilayer structure can affect the switching features of the RRAM, causing them to exhibit both bipolar resistive switching (BRS) behavior and self-compliance behavior. The current conduction mechanisms of RRAM devices with different film structures were also discussed.

APA, Harvard, Vancouver, ISO, and other styles

3

Aguilera-Pedregosa, Cristina, David Maldonado, Mireia B. González, Enrique Moreno, Francisco Jiménez-Molinos, Francesca Campabadal, and Juan B. Roldán. "Thermal Characterization of Conductive Filaments in Unipolar Resistive Memories." Micromachines 14, no. 3 (March 10, 2023): 630. http://dx.doi.org/10.3390/mi14030630.

Full text

Abstract:

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is used to fit experimental data and obtain the maximum and average temperatures of the conductive filaments (CFs) that are responsible for the switching behavior. It is found that the experimental CFs temperature corresponds to the maximum simulated temperatures obtained at the narrowest sections of the CFs. These temperature values can be used to improve compact models for circuit simulation purposes.

APA, Harvard, Vancouver, ISO, and other styles

4

Arumí, Daniel, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Víctor Montilla, David Hernández, Mireia Bargalló González, and Francesca Campabadal. "Impact of Laser Attacks on the Switching Behavior of RRAM Devices." Electronics 9, no. 1 (January 20, 2020): 200. http://dx.doi.org/10.3390/electronics9010200.

Full text

Abstract:

The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, together with the rest of related works, are expected to pave the way for the development of suitable countermeasures against external attacks.

APA, Harvard, Vancouver, ISO, and other styles

5

Ansh and Mayank Shrivastava. "Superior resistance switching in monolayer MoS₂ channel-based gated binary resistive random-access memory via gate-bias dependence and a unique forming process." Journal of Physics D: Applied Physics 55, no. 8 (November 12, 2021): 085102. http://dx.doi.org/10.1088/1361-6463/ac3281.

Full text

Abstract:

Abstract Resistance switching (RS) in 2D molybdenum disulfide (MoS2) was recently discovered. Since the discovery, many reports demonstrating MoS2 resistive random-access memory (RRAM) with synapse-like behavior have been published. These reports strongly justify applications of MoS2 RRAM in neuromorphic hardware as well as an alternative to conventional binary memories. In this work, we unveil the effect of RS, induced by current–voltage hysteresis cycles across CVD-grown monolayer MoS2-based gated RRAM, on its transistor’s electrical and reliability characteristics. A unique gate voltage dependence on the RS is identified which has a remarkable impact on the switching performance of MoS2 RRAM. RS behavior was found to be significantly dependent on the charge conduction in the channel. Moreover, we have shown a potential device-forming event when MoS2-gated RRAMs were subjected to a steady-state electrical stress. Both hysteresis and steady-state electrical stress were found to disturb the transistor action of these gated RRAMs, which can in fact be used as a signature of RS. Interestingly, current–voltage hysteresis resulted in unipolar RS, whereas steady-state electrical stress before RS measurement led to bipolar RS. Moreover, successive stress cycles of such electrical stress lead to multiple resistance states, a behavior similar to synaptic properties such as long-term potentiation and long-term depression, typically found in memristors. We find that the charge transport mechanism dominant in the MoS2 FET, in conjunction with steady-state stress-induced device forming, determine the extent of RS induced in thes MoS2-based gated RRAMs. Finally, on the basis of insights developed from the dependence on the charge transport mechanism and steady-state stress-induced forming of the MoS2 channel, we propose a certain steady-state electrical stress condition which can be used as a ‘forming’ process, employed prior to the use of MoS2-based binary RRAMs for improved switching performance.

APA, Harvard, Vancouver, ISO, and other styles

6

Shu, Pan, Xiaofei Cao, Yongqiang Du, Jiankui Zhou, Jianjun Zhou, Shengang Xu, Yingliang Liu, and Shaokui Cao. "Resistive switching performance of fibrous crosspoint memories based on an organic–inorganic halide perovskite." Journal of Materials Chemistry C 8, no. 37 (2020): 12865–75. http://dx.doi.org/10.1039/d0tc02579h.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Alimkhanuly, Batyrbek, Sanghoek Kim, Lok-won Kim, and Seunghyun Lee. "Electromagnetic Analysis of Vertical Resistive Memory with a Sub-nm Thick Electrode." Nanomaterials 10, no. 9 (August 20, 2020): 1634. http://dx.doi.org/10.3390/nano10091634.

Full text

Abstract:

Resistive random access memories (RRAMs) are a type of resistive memory with two metal electrodes and a semi-insulating switching material in-between. As the persistent technology node downscaling continues in transistor technologies, RRAM designers also face similar device scaling challenges in simple cross-point arrays. For this reason, a cost-effective 3D vertical RRAM (VRRAM) structure which requires a single pivotal lithography step is attracting significant attention from both the scientific community and the industry. Integrating an extremely thin plane electrode to such a structure is a difficult but necessary step to enable high memory density. In addition, experimentally verifying and modeling such devices is an important step to designing RRAM arrays with a high noise margin, low resistive-capacitive (RC) delays, and stable switching characteristics. In this work, we conducted an electromagnetic analysis on a 3D vertical RRAM with atomically thin graphene electrodes and compared it with the conventional metal electrode. Based on the experimental device measurement results, we derived a theoretical basis and models for each VRRAM design that can be further utilized in the estimation of graphene-based 3D memory at the circuit and architecture levels. We concluded that a 71% increase in electromagnetic field strength was observed in a 0.3 nm thick graphene electrode when compared to a 5 nm thick metal electrode. Such an increase in the field led to much lower energy consumption and fluctuation range during RRAM switching. Due to unique graphene properties resulting in improved programming behavior, the graphene-based VRRAM can be a strong candidate for stacked storage devices in new memory computing platforms.

APA, Harvard, Vancouver, ISO, and other styles

8

Vasileiadis, Nikolaos, Vasileios Ntinas, Georgios Ch Sirakoulis, and Panagiotis Dimitrakis. "In-Memory-Computing Realization with a Photodiode/Memristor Based Vision Sensor." Materials 14, no. 18 (September 10, 2021): 5223. http://dx.doi.org/10.3390/ma14185223.

Full text

Abstract:

State-of-the-art IoT technologies request novel design solutions in edge computing, resulting in even more portable and energy-efficient hardware for in-the-field processing tasks. Vision sensors, processors, and hardware accelerators are among the most demanding IoT applications. Resistance switching (RS) two-terminal devices are suitable for resistive RAMs (RRAM), a promising technology to realize storage class memories. Furthermore, due to their memristive nature, RRAMs are appropriate candidates for in-memory computing architectures. Recently, we demonstrated a CMOS compatible silicon nitride (SiNx) MIS RS device with memristive properties. In this paper, a report on a new photodiode-based vision sensor architecture with in-memory computing capability, relying on memristive device, is disclosed. In this context, the resistance switching dynamics of our memristive device were measured and a data-fitted behavioral model was extracted. SPICE simulations were made highlighting the in-memory computing capabilities of the proposed photodiode-one memristor pixel vision sensor. Finally, an integration and manufacturing perspective was discussed.

APA, Harvard, Vancouver, ISO, and other styles

9

Poddar, Swapnadeep, Yuting Zhang, Zhesi Chen, Zichao Ma, and Zhiyong Fan. "(Digital Presentation) Resistive Switching and Brain-Inspired Computing in Perovskite Nanowires and Quantum Wires." ECS Meeting Abstracts MA2022-02, no. 36 (October 9, 2022): 1336. http://dx.doi.org/10.1149/ma2022-02361336mtgabs.

Full text

Abstract:

In the past decade, halide perovskites (HPs) have shot to fame in the genre of optoelectronics and photovoltaics owing to their large absorption co-effcient, high color purity, tunable bandgap and long charge diffusion lengths. Besides these traits, HPs also possess innumerable charge transport pathways, inherent hysteresis, high charge-carrier and ionic mobilities which render them as ideal candidates for resistive random access switching memories (RRAMs). However owing to material and electrical instability associated with HP thin-film devices, the figures-of-merits (FOMs) namely retention, endurance and switching speed were not up to the state of-the-art standard until recently. In order to revolutionize HP Re-RAMs we devised a unique device structure where we replaced the thin-film architecture with vertically aligned high density HP nanowires and quantum wires embedded in a porous alumina membrane (PAM) sandwiched between metallic silver and aluminum contacts. The excellent passivation provided by the PAM imparted the requisite electrical and material stability to the environmentally delicate HPs by drastically reducing the surface diffusion pathways and thereby thwarting the moisture induced attacks. Extrapolated retention time as high as 28.3 years and measured device endurance of a million cycles were obtained. Utilizing the single crystalline HP nanowires and quantum wires and their associated high ionic and electronic mobilities, switching speed as fast as 100 ps was also obtained. These FOMs represent record values for HP RRAMs ever reported. Furthermore a 14 nm lateral size HP quantum wire RRAM cell was fabricated and a cross-bar device architecture with a unique sneaky path mitigation scheme were developed, which successfully exhibited the scalability potential of our devices. We further coupled the optoelectronic and switching behaviors and were able to obtain optical programmability among the low resistance states. Besides data storage, the HP nanowires and quantum wires were employed in developing neuromorphic devices enabled with low power and high precision computing capabilities. Specifically, we obtained robust multi-level states in two types of brain-inspired devices capable of performing analog processing tasks by using silver as the top electrode and precisely controlling the current injection in the monocrytalline switching medium and by using indium doped tin oxide as the top electrode and inducing a novel valence change mechanism in the HP nanowires triggering the gradual conductance change. All in all, our nanowire and quantum wire devices propel HP RRAMs to the state-of-the-art standard in multifarious applications concerning future data storage and neuromorphic computing.

APA, Harvard, Vancouver, ISO, and other styles

10

Minguet Lopez, J., T. Hirtzlin, M. Dampfhoffer, L. Grenouillet, L. Reganaz, G. Navarro, C. Carabasse, et al. "OxRAM + OTS optimization for binarized neural network hardware implementation." Semiconductor Science and Technology 37, no. 1 (December 8, 2021): 014001. http://dx.doi.org/10.1088/1361-6641/ac31e2.

Full text

Abstract:

Abstract Low-power memristive devices embedded on graphics or central processing units logic core are a very promising non-von-Neumann approach to improve significantly the speed and power consumption of deep learning accelerators, enhancing their deployment on embedded systems. Among various non-ideal emerging neuromorphic memory devices, synaptic weight hardware implementation using resistive random-access memories (RRAMs) within 1T1R architectures promises high performance on low precision binarized neural networks (BNN). Taking advantage of the RRAM capabilities and allowing to substantially improve the density thanks to the ovonic threshold selector (OTS) selector, this work proposes to replace the standard 1T1R architecture with a denser 1S1R crossbar system, where an HfO2-based resistive oxide memory (OxRAM) is co-integrated with a Ge-Se-Sb-N-based OTS. In this context, an extensive experimental study is performed to optimize the 1S1R stack and programming conditions for extended read window margin and endurance characteristics. Focusing on the standard machine learning MNIST image recognition task, we perform offline training simulations in order to define the constraints on the devices during the training process. A very promising bit error rate of ∼10−3 is demonstrated together with 1S1R 104 error-free programming endurance characteristics, fulfilling the requirements for the application of interest. Based on this simulation and experimental study, BNN figures of merit (system footprint, number of weight updates, accuracy, inference speed, electrical consumption per image classification and tolerance to errors) are optimized by engineering the number of learnable parameters of the system. Altogether, an inherent BNN resilience to 1S1R parasitic bit errors is demonstrated.

APA, Harvard, Vancouver, ISO, and other styles

11

Ali, Sarfraz, Muhammad Abaid Ullah, Ali Raza, Muhammad Waqas Iqbal, Muhammad Farooq Khan, Maria Rasheed, Muhammad Ismail, and Sungjun Kim. "Recent Advances in Cerium Oxide-Based Memristors for Neuromorphic Computing." Nanomaterials 13, no. 17 (August 28, 2023): 2443. http://dx.doi.org/10.3390/nano13172443.

Full text

Abstract:

This review article attempts to provide a comprehensive review of the recent progress in cerium oxide (CeO2)-based resistive random-access memories (RRAMs). CeO2 is considered the most promising candidate because of its multiple oxidation states (Ce3+ and Ce4+), remarkable resistive-switching (RS) uniformity in DC mode, gradual resistance transition, cycling endurance, long data-retention period, and utilization of the RS mechanism as a dielectric layer, thereby exhibiting potential for neuromorphic computing. In this context, a detailed study of the filamentary mechanisms and their types is required. Accordingly, extensive studies on unipolar, bipolar, and threshold memristive behaviors are reviewed in this work. Furthermore, electrode-based (both symmetric and asymmetric) engineering is focused for the memristor’s structures such as single-layer, bilayer (as an oxygen barrier layer), and doped switching-layer-based memristors have been proved to be unique CeO2-based synaptic devices. Hence, neuromorphic applications comprising spike-based learning processes, potentiation and depression characteristics, potentiation motion and synaptic weight decay process, short-term plasticity, and long-term plasticity are intensively studied. More recently, because learning based on Pavlov’s dog experiment has been adopted as an advanced synoptic study, it is one of the primary topics of this review. Finally, CeO2-based memristors are considered promising compared to previously reported memristors for advanced synaptic study in the future, particularly by utilizing high-dielectric-constant oxide memristors.

APA, Harvard, Vancouver, ISO, and other styles

12

Arashloo, Banafsheh Alizadeh. "Cupper doping effect on the electrical characteristics of TiO2 based Memristor." Brilliant Engineering 2, no. 1 (June 10, 2020): 19–24. http://dx.doi.org/10.36937/ben.2021.001.004.

Full text

Abstract:

Nanostructures as a starting point to solve the scaling problems of the CMOS technologies, have been concerned the attention of numerous researchers. By strong demanding for nonvolatile memory technology, resistive memories based on metal oxide has been common due to several advantages, such as low-power consumption, good scalability and fast switching speed. Even though high-temperature fabrication process has a large area limitation by their material characteristics. Metal oxide thin films are respectable candidate to fabricate at nano scale solid state electronic device. Metal/Metal-Oxide/Metal structure is employed to several devices such as Non-volatile able memories, RRAMs, resistance switching based devices and memristor. The foundation of the primary TiO2 based memristor served a number of consequences for understanding the conduction mechanisms during the formation of hysteresis loop. Also, the current-voltage characteristics (hysteretic loop) which is formed by mobile anions or oxygen vacancies motion in the set and reset process, is clarified the resistive switching behavior by swapping the resistance of TiO2 thin film. Here, the effect of Cu doping into TiO2 based memristor by focused on the hysteresis loop characteristics is considered. Similarities of hysteresis loop form in Cu doped devices are explored. Hysteresis loop is symmetric for structures having pure TiO2; however, asymmetric character appears after Cu doping. After the formation process hysteresis loop of the Cu doped devices shown higher conductance path on (I-V) characteristic than the initial forming process loop in positive cycle loop as the un-doped TiO2. Also, in spite of un-doped TiO2, this (I-V) hysteresis loop character shown lower path conductance than primary forming process in the negative cycle loop. Surface roughness of 30nm thick TiO2 is increased from 0.3nm to 0.77nm as Cu doping increased from %10 to %30. Unfortunately, XRD results cleared that there is no exchange in crystallinity but optical band gap decreased as Cu doping increased.

APA, Harvard, Vancouver, ISO, and other styles

13

WANG, SHENG-YU, and TSEUNG-YUEN TSENG. "INTERFACE ENGINEERING IN RESISTIVE SWITCHING MEMORIES." Journal of Advanced Dielectrics 01, no. 02 (April 2011): 141–62. http://dx.doi.org/10.1142/s2010135x11000306.

Full text

Abstract:

Electric-induced resistive switching effects have attracted wide attention for future nonvolatile memory applications known as resistive random access memory (RRAM). RRAM is one of the promising candidates because of its excellent properties including simple device structure, high operation speed, low power consumption and high density integration. The RRAM devices primarily utilize different resistance values to store the digital data and can keep the resistance state without any power. Recent advances in the understanding of the resistive switching mechanism are described by a thermal or electrochemical redox reaction near the interface between the oxide and the active metal electrode. This paper reviews the ongoing research and development activities on the interface engineering of the RRAM devices. The possible switching mechanisms for the bistable resistive switching are described. The effects of formation, composition and thickness of the interface layer on the resistive switching characteristics and consequently the memory performance are also discussed.

APA, Harvard, Vancouver, ISO, and other styles

14

Qian, Kai, Viet Cuong Nguyen, Tupei Chen, and Pooi See Lee. "Novel concepts in functional resistive switching memories." Journal of Materials Chemistry C 4, no. 41 (2016): 9637–45. http://dx.doi.org/10.1039/c6tc03447k.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Chen, Tong, Kangmin Leng, Zhongyuan Ma, Xiaofan Jiang, Kunji Chen, Wei Li, Jun Xu, and Ling Xu. "Tracing the Si Dangling Bond Nanopathway Evolution ina-SiNx:H Resistive Switching Memory by the Transient Current." Nanomaterials 13, no. 1 (December 24, 2022): 85. http://dx.doi.org/10.3390/nano13010085.

Full text

Abstract:

With the big data and artificial intelligence era coming, SiNx-based resistive random-access memories (RRAM) with controllable conductive nanopathways have a significant application in neuromorphic computing, which is similar to the tunable weight of biological synapses. However, an effective way to detect the components of conductive tunable nanopathways in a-SiNx:H RRAM has been a challenge with the thickness down-scaling to nanoscale during resistive switching. For the first time, we report the evolution of a Si dangling bond nanopathway in a-SiNx:H resistive switching memory can be traced by the transient current at different resistance states. The number of Si dangling bonds in the conducting nanopathway for all resistive switching states can be estimated through the transient current based on the tunneling front model. Our discovery of transient current induced by the Si dangling bonds in the a-SiNx:H resistive switching device provides a new way to gain insight into the resistive switching mechanism of the a-SiNx:H RRAM in nanoscale.

APA, Harvard, Vancouver, ISO, and other styles

16

Wan, Zhenni, Robert B. Darling, and M. P. Anantram. "Vanadium Oxide Based RRAM Device." MRS Advances 2, no. 52 (2017): 3019–24. http://dx.doi.org/10.1557/adv.2017.442.

Full text

Abstract:

ABSTRACTForming-free bipolar resistive switching characteristics in a Vanadium oxide based sandwich structure is observed for the first time. The bottom conducting layer is the common ground electrode for all devices. The top conducting layer acts as an active element with an additional Cr/Al/Cr electrode patterned on its top for making contact. Different from the typical metal/transition metal oxide/metal sandwich structure based resistive memories, our device exhibits a low resistance state (LRS) in its virgin state, and can be switched to a high resistance state (HRS) when a positive bias of +2.5V is applied to the top electrode. Following this, the device can be reset to a LRS when a negative bias of approximately 2.5V is applied. A significant decrease of switching voltages is observed when the diameter of the top contact decreases, indicating an electric field enhanced switching mechanism. Simulation using TCAD confirms that electric field beneath the top metal contact increases due to fringing. The results suggest future applications in low power integrated non-volatile memories.

APA, Harvard, Vancouver, ISO, and other styles

17

Dash, C. S., and S. R. S. Prabaharan. "Science and Technological Understanding of Nano-ionic Resistive Memories (RRAM)." Nanoscience & Nanotechnology-Asia 9, no. 4 (November 25, 2019): 444–61. http://dx.doi.org/10.2174/2210681208666180621095241.

Full text

Abstract:

Ion transport in the solid state has been regarded as imperative with regards to high energy density electrochemical storage devices (for instance, batteries) for efficient electric mobility. Of late, there is another niche application involving ion transport in solid state which manifested itself as nonvolatile memory namely memristor. Such memories are classified under the emerging category of novel solid state Resistive Random Access Memories (RRAM). In 2008, HP labs unveiled the first practical memristor device employing TiO2 and non-stoichiometric titania as bilayer stack structure and on both sides of two titania layers platinum (pt) are used as blocking electrode for ions. It is understood that switching fundamentals are correlated to the filamentary conduction in metal oxide memristors owing to the formation and rupture of the filament-like nano-dendrites, one of the key mechanisms widely accepted in the arena of memristor analysis. This paper critically reviews the fundamental materials being employed in novel memristor memories. It is believed that solid electrolytes (fast ion conductors) are the fundamental building blocks of these memories. We have chosen a few archetypes, solid electrolytes are considered and their impact on the state-of-art research in this domain is discussed in detail. An indepth analysis of the fundamentals of resistive switching mechanism involved in various classes of memristive devices viz., Electrochemical Metallization Memories (ECM) and Valence Change Memories (VCM) is elucidated. A few important applications of memristors such as neuristor and artificial synapse in neuromorphic computing are reviewed as well.

APA, Harvard, Vancouver, ISO, and other styles

18

Molas, Gabriel, Gilbert Sassine, Cecile Nail, Diego Alfaro Robayo, Jean-François Nodin, Carlo Cagli, Jean Coignus, Philippe Blaise, and Etienne Nowak. "(Invited) Resistive Memories (RRAM) Variability: Challenges and Solutions." ECS Transactions 86, no. 3 (July 20, 2018): 35–47. http://dx.doi.org/10.1149/08603.0035ecst.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Lee, Yunseok, Jiung Jang, Beomki Jeon, Kisong Lee, Daewon Chung, and Sungjun Kim. "Resistive Switching Characteristics of Alloyed AlSiOx Insulator for Neuromorphic Devices." Materials 15, no. 21 (October 26, 2022): 7520. http://dx.doi.org/10.3390/ma15217520.

Full text

Abstract:

Charge-based memories, such as NAND flash and dynamic random-access memory (DRAM), have reached scaling limits and various next-generation memories are being studied to overcome their issues. Resistive random-access memory (RRAM) has advantages in structural scalability and long retention characteristics, and thus has been studied as a next-generation memory application and neuromorphic system area. In this paper, AlSiOx, which was used as an alloyed insulator, was used to secure stable switching. We demonstrate synaptic characteristics, as well as the basic resistive switching characteristics with multi-level cells (MLC) by applying the DC sweep and pulses. Conduction mechanism analysis for resistive switching characteristics was conducted to understand the resistive switching properties of the device. MLC, retention, and endurance are evaluated and potentiation/depression curves are mimicked for a neuromorphic device.

APA, Harvard, Vancouver, ISO, and other styles

20

Koohzadi, Pooria, Mohammad Taghi Ahmadi, Javad Karamdel, and Truong Khang Nguyen. "Graphene band engineering for resistive random-access memory application." International Journal of Modern Physics B 34, no. 18 (July 10, 2020): 2050171. http://dx.doi.org/10.1142/s0217979220501714.

Full text

Abstract:

Emerging memory technologies promise new memories to store more data at less cost. On the other hand, the scaling of silicon-based chips approached its physical limits. Nonvolatile memory technologies, such as resistive random-access memory (RRAM), are trying to solve this problem. The fundamental study in RRAM devices still needs to be moved further. In this regard, conduction mechanism of RRAM is focused in this study. The RRAM conductance varies considerably depending on the material used in the dielectric layer and selection of electrodes. To formulate the conductance mechanism, new materials with notable conductivity such as graphene oxide (GO) sheets has been employed by researchers. In the GO-based RRAM, pristine of GO due to the presence of sp3-hybridized oxygen functional groups(hydroxyl) leads to electrically insulating layers in the device. However, by applying the voltage, the conductive path can be formed with the redox of GO layer in to graphene. This phenomenon is known as RRAM set process which can be explained due to the conversion of sp3 to sp2 oxygen functionalities, which make the RRAM to move in to the ON state. Also, in this paper, variation of the ON state resistance by the voltage in the nondegenerate mode is described and the reset process by degeneracy variation is reported.

APA, Harvard, Vancouver, ISO, and other styles

21

Pérez, Eduardo, Florian Teply, and Christian Wenger. "Electrical study of radiation hard designed HfO2-based 1T-1R RRAM devices." MRS Advances 2, no. 4 (December 12, 2016): 223–28. http://dx.doi.org/10.1557/adv.2016.616.

Full text

Abstract:

ABSTRACTIn this work the electrical performance of a radiation hard designed 1T-1R resistive random access memory (RRAM) device is investigated in DC (voltage sweep) and AC (pulsed voltage) modes. This new device is based on the combination of an Enclosed Layout Transistor (ELT) used as selector device and a TiN/ HfO2/ Ti/TiN RRAM stack used as resistive device. The high cell to cell variability in the DC mode makes it difficult to define an electrical gap between the High Resistive State (HRS) and the Low Resistive State (LRS). The strong reduction of the variability by the use of Incremental Step Pulse with Verify Algorithm (ISPVA) makes the later a mandatory programming approach. The Quantum Point Contact (QPC) model defines an energy barrier located in the rupture point of the filament in HRS. The compensation between the width and height variations of this barrier during cycling could explain the stability of HRS and LRS. The good performance of the proposed device using the ISPVA programming approach makes it a good candidate for Rad-Hard Non Volatile Memories integration.

APA, Harvard, Vancouver, ISO, and other styles

22

Wang, Li-Wen, Chih-Wei Huang, Ke-Jing Lee, Sheng-Yuan Chu, and Yeong-Her Wang. "Multi-Level Resistive Al/Ga2O3/ITO Switching Devices with Interlayers of Graphene Oxide for Neuromorphic Computing." Nanomaterials 13, no. 12 (June 13, 2023): 1851. http://dx.doi.org/10.3390/nano13121851.

Full text

Abstract:

Recently, resistive random access memory (RRAM) has been an outstanding candidate among various emerging nonvolatile memories for high-density storage and in-memory computing applications. However, traditional RRAM, which accommodates two states depending on applied voltage, cannot meet the high density requirement in the era of big data. Many research groups have demonstrated that RRAM possesses the potential for multi-level cells, which would overcome demands related to mass storage. Among numerous semiconductor materials, gallium oxide (a fourth-generation semiconductor material) is applied in the fields of optoelectronics, high-power resistive switching devices, and so on, due to its excellent transparent material properties and wide bandgap. In this study, we successfully demonstrate that Al/graphene oxide (GO)/Ga2O3/ITO RRAM has the potential to achieve two-bit storage. Compared to its single-layer counterpart, the bilayer structure has excellent electrical properties and stable reliability. The endurance characteristics could be enhanced above 100 switching cycles with an ON/OFF ratio of over 103. Moreover, the filament models are also described in this thesis to clarify the transport mechanisms.

APA, Harvard, Vancouver, ISO, and other styles

23

Yalon, E., I. Karpov, V. Karpov, I. Riess, D. Kalaev, and D. Ritter. "Detection of the insulating gap and conductive filament growth direction in resistive memories." Nanoscale 7, no. 37 (2015): 15434–41. http://dx.doi.org/10.1039/c5nr03314d.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Napolean, A., N. M. Sivamangai, S. Rajesh, R. Naveenkumar, N. Sharon, N. Nithya, and S. Kamalnath. "Effects of Ambient and Annealing Temperature in HfO₂ Based RRAM Device Modeling and Circuit-Level Implementation." ECS Journal of Solid State Science and Technology 11, no. 2 (February 1, 2022): 023012. http://dx.doi.org/10.1149/2162-8777/ac557b.

Full text

Abstract:

This article focuses on the relevance of the effect of ambient temperature and annealing in the context of compact modeling of metal oxide resistive random access memory (RRAM) devices. The ambient temperature affects the conduction characteristic of resistive switching memories, so it becomes an essential factor to include when adjusting the experimental data. Reported the fabricated results and memory switching parameters with the defined set (Vset) and reset (Vreset) transition voltages for the fabricated annealed HfO2-based RRAM. Additionally, to illustrate the importance of this characteristic in the form of the I-V curve, the Stanford model (SFM) for RRAM devices is enhanced by incorporating the annealing temperature as an additional parameter in the script of the Verilog-A model. Stanford and modified Stanford model (MSFM) are analyzed at the device level using cadence circuit simulator and implemented in the nonvolatile memory circuit (3 *3 memory arrays). Results confirmed that the experimental switching voltages, Vset, Vreset are 1.7 V, −0.8 V. These values are well suited along the simulated MSFM switching voltages of, Vset, Vreset (1.8 V, −0.7 V). The mean error percentage of the MSF is 18.42%.

APA, Harvard, Vancouver, ISO, and other styles

25

Yang, Seyeong, Jongmin Park, Youngboo Cho, Yunseok Lee, and Sungjun Kim. "Enhanced Resistive Switching and Synaptic Characteristics of ALD Deposited AlN-Based RRAM by Positive Soft Breakdown Process." International Journal of Molecular Sciences 23, no. 21 (October 31, 2022): 13249. http://dx.doi.org/10.3390/ijms232113249.

Full text

Abstract:

Nitride film played an essential role as an excellent diffusion barrier in the semiconductor field for several decades. In addition, interest in next-generation memories induced researchers’ attention to nitride film as a new storage medium. A Pt/AlN/TaN device was investigated for resistive random-access memory (RRAM) application in this work. Resistive switching properties were examined in the AlN thin film formed by atomic layer deposition (ALD). The unique switching feature conducted under the positive voltage was investigated, while the typical bipolar switching was conducted under the application of negative voltage. Good retention and DC, and pulse endurances were achieved in both conditions and compared to the memory performances. Finally, the electronic behaviors based on the unique switching feature were analyzed through X-ray photoelectron spectroscopy (XPS) and the current–voltage (I–V) linear fitting model.

APA, Harvard, Vancouver, ISO, and other styles

26

Zhang, Donglin, Bo Peng, Yulin Zhao, Zhongze Han, Qiao Hu, Xuanzhi Liu, Yongkang Han, et al. "Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes." Micromachines 12, no. 8 (July 30, 2021): 913. http://dx.doi.org/10.3390/mi12080913.

Full text

Abstract:

Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces many issues, which can significantly degrade RRAM performance. Therefore, it is necessary to optimize the sensing schemes to improve the application range of RRAM. In this paper, the issues faced by RRAM in advanced technology nodes are summarized. Then, the advantages and weaknesses in the novel design and optimization methodologies of sensing schemes are introduced in detail from three aspects, the reference schemes, sensing amplifier schemes, and bit line (BL)-enhancing schemes, according to the development of technology in especially recent years, which can be the reference for designing the sensing schemes. Moreover, the waveforms and results of each method are illustrated to make the design easy to understand. With the development of technology, the sensing schemes of RRAM become higher speed and resolution, low power consumption, and are applied at advanced technology nodes and low working voltage. Now, the most advanced nodes the RRAM applied is 14 nm node, the lowest working voltage can reach 0.32 V, and the shortest access time can be only a few nanoseconds.

APA, Harvard, Vancouver, ISO, and other styles

27

Ruiz-Castro, Juan E., Christian Acal, Ana M. Aguilera, and Juan B. Roldán. "A Complex Model via Phase-Type Distributions to Study Random Telegraph Noise in Resistive Memories." Mathematics 9, no. 4 (February 16, 2021): 390. http://dx.doi.org/10.3390/math9040390.

Full text

Abstract:

A new stochastic process was developed by considering the internal performance of macro-states in which the sojourn time in each one is phase-type distributed depending on time. The stationary distribution was calculated through matrix-algorithmic methods and multiple interesting measures were worked out. The number of visits distribution to a determine macro-state were analyzed from the respective differential equations and the Laplace transform. The mean number of visits to a macro-state between any two times was given. The results were implemented computationally and were successfully applied to study random telegraph noise (RTN) in resistive memories. RTN is an important concern in resistive random access memory (RRAM) operation. On one hand, it could limit some of the technological applications of these devices; on the other hand, RTN can be used for the physical characterization. Therefore, an in-depth statistical analysis to model the behavior of these devices is of essential importance.

APA, Harvard, Vancouver, ISO, and other styles

28

Lahbacha, Khitem, Fakhreddine Zayer, Hamdi Belgacem, Wael Dghais, and Antonio Maffucci. "Performance Enhancement of Large Crossbar Resistive Memories With Complementary and 1D1R-1R1D RRAM Structures." IEEE Open Journal of Nanotechnology 2 (2021): 111–19. http://dx.doi.org/10.1109/ojnano.2021.3124846.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

La Torraca, Paolo, Francesco Maria Puglisi, Andrea Padovani, and Luca Larcher. "Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory." Materials 12, no. 21 (October 23, 2019): 3461. http://dx.doi.org/10.3390/ma12213461.

Full text

Abstract:

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material’s microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device’s performance and variability to be evaluated, the analog resistance switching to be optimized, and the device’s reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

APA, Harvard, Vancouver, ISO, and other styles

30

Khan, Mohammad Nasim Imtiaz, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. "Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 28, 2021): 38. http://dx.doi.org/10.3390/jlpea11040038.

Full text

Abstract:

Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache.

APA, Harvard, Vancouver, ISO, and other styles

31

Huang, Yanzi, Lingyu Wan, Jiang Jiang, Liuyan Li, and Junyi Zhai. "Self-Powered Resistance-Switching Properties of Pr0.7Ca0.3MnO3 Film Driven by Triboelectric Nanogenerator." Nanomaterials 12, no. 13 (June 27, 2022): 2199. http://dx.doi.org/10.3390/nano12132199.

Full text

Abstract:

As one of the promising non-volatile memories (NVMs), resistive random access memory (RRAM) has attracted extensive attention. Conventional RRAM is deeply dependent on external power to induce resistance-switching, which restricts its applications. In this work, we have developed a self-powered RRAM that consists of a Pr0.7Ca0.3MnO3 (PCMO) film and a triboelectric nanogenerator (TENG). With a traditional power supply, the resistance switch ratio achieves the highest switching ratio reported so far, 9 × 107. By converting the mechanical energy harvested by a TENG into electrical energy to power the PCMO film, we demonstrate self-powered resistance-switching induced by mechanical movement. The prepared PCMO shows excellent performance of resistance switching driven by the TENG, and the resistance switch ratio is up to 2 × 105, which is higher than the ones ever reported. In addition, it can monitor real-time mechanical changes and has a good response to the electrical signals of different waveforms. This self-powered resistance switching can be induced by random movements based on the TENG. It has potential applications in the fields of self-powered sensors and human-machine interaction.

APA, Harvard, Vancouver, ISO, and other styles

32

Otsus, Markus, Joonas Merisalu, Aivar Tarre, Anna-Liisa Peikolainen, Jekaterina Kozlova, Kaupo Kukli, and Aile Tamm. "Bipolar Resistive Switching in Hafnium Oxide-Based Nanostructures with and without Nickel Nanoparticles." Electronics 11, no. 18 (September 19, 2022): 2963. http://dx.doi.org/10.3390/electronics11182963.

Full text

Abstract:

As research into additives and intentionally introduced impurities in dielectric thin film for enhancing the resistive switching based random access memories (RRAM) continues to gain momentum, the aim of the study was to evaluate the effects of chemically presynthesised Ni nanoparticles (NPs) embedded in a dielectric layer to the overall structure and resistive switching properties. HfO2-based thin films embedded with Ni NPs were produced by atomic layer deposition (ALD) from tetrakis(ethylmethylamino)hafnium (TEMAH) and the O2 plasma ALD process onto a TiN/Si substrate. The Ni NPs were separately synthesised through a continuous flow chemistry process and dispersed on the dielectric layer between the two stages of preparing the HfO2 layer. The nanodevices’ morphology and composition were analysed with physical characterisation methods and were found to be uniformly dispersed across the sample, within an amorphous HfO2 layer deposited around them. When comparing the resistive switching properties of otherwise identical samples with and without Ni NPs, the ILRS/IHRS ratio rose from around a 4 to 9 at 0.2 V reading voltage, the switching voltage dropped from ~2 V to ~1.5 V, and a distinct increase in the endurance characteristics could be seen with the addition of the nanoparticles.

APA, Harvard, Vancouver, ISO, and other styles

33

Pérez, Eduardo, Óscar González Ossorio, Salvador Dueñas, Helena Castán, Héctor García, and Christian Wenger. "Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays." Electronics 9, no. 5 (May 23, 2020): 864. http://dx.doi.org/10.3390/electronics9050864.

Full text

Abstract:

A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width.

APA, Harvard, Vancouver, ISO, and other styles

34

Cario, Laurent, Cristian Vaju, Benoit Corraze, Vincent Guiot, and Etienne Janod. "Electric-Field-Induced Resistive Switching in a Family of Mott Insulators: Towards a New Class of RRAM Memories." Advanced Materials 22, no. 45 (October 18, 2010): 5193–97. http://dx.doi.org/10.1002/adma.201002521.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 24, 2021): 36. http://dx.doi.org/10.3390/jlpea11040036.

Full text

Abstract:

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

APA, Harvard, Vancouver, ISO, and other styles

36

Quiroz, Heiddy P., Jorge A. Calderón, and A. Dussan. "Magnetic switching control in Co/TiO2 bilayer and TiO2:Co thin films for Magnetic-Resistive Random Access Memories (M-RRAM)." Journal of Alloys and Compounds 840 (November 2020): 155674. http://dx.doi.org/10.1016/j.jallcom.2020.155674.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Mounica, J., and G. V. Ganesh. "Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1183. http://dx.doi.org/10.11591/ijece.v6i3.9448.

Full text

Abstract:

Now-a-days, Energy consumption is the major key factor in Memories. By switching the circuit in off mode and with an lower voltages, leads to decrease in an power dissipation of the circuit. Compared to DRAM SRAM’S are mostly used because of their data retaining capability. The major advantage of using SRAM’s rather than DRAM’S is that, they are providing fast power-on/off speeds. Hence SRAM’s are more preferred over DRAM’s for better instant-on operation. Generally SRAM’s are classified in to two types namely volatile and non-volatile SRAM’s. A non-volatile SRAM enables chip to achieve performance factors and also provides an restore operation which will be enabled by an restore signal to restore the data and also power-up operation is performed. This paper describes about novel NVSRAM circuit which produces better “instant-on operation” compared to previous techniques used in SRAM’s. In addition to normal 6T SRAM core, we are using RRAM circuitry (Resistive RAM) to provide better instant-on operation. By comparing the performance factors with 8T2R and 9T2R, 8T1R design performs the best in the Nano meter scale. Thus this paper provides better performances in power, energy, propagation delay and area factors as compared with other designs.

APA, Harvard, Vancouver, ISO, and other styles

38

Mounica, J., and G. V. Ganesh. "Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1183. http://dx.doi.org/10.11591/ijece.v6i3.pp1183-1189.

Full text

Abstract:

Now-a-days, Energy consumption is the major key factor in Memories. By switching the circuit in off mode and with an lower voltages, leads to decrease in an power dissipation of the circuit. Compared to DRAM SRAM’S are mostly used because of their data retaining capability. The major advantage of using SRAM’s rather than DRAM’S is that, they are providing fast power-on/off speeds. Hence SRAM’s are more preferred over DRAM’s for better instant-on operation. Generally SRAM’s are classified in to two types namely volatile and non-volatile SRAM’s. A non-volatile SRAM enables chip to achieve performance factors and also provides an restore operation which will be enabled by an restore signal to restore the data and also power-up operation is performed. This paper describes about novel NVSRAM circuit which produces better “instant-on operation” compared to previous techniques used in SRAM’s. In addition to normal 6T SRAM core, we are using RRAM circuitry (Resistive RAM) to provide better instant-on operation. By comparing the performance factors with 8T2R and 9T2R, 8T1R design performs the best in the Nano meter scale. Thus this paper provides better performances in power, energy, propagation delay and area factors as compared with other designs.

APA, Harvard, Vancouver, ISO, and other styles

39

Li, Rongbin, Yan Sun, Qianyu Zhao, Xin Hao, Haowei Liang, Shengang Xu, Yingliang Liu, Xiaoman Bi, and Shaokui Cao. "NIR-Triggered Logic Gate in MXene-Modified Perovskite Resistive Random Access Memory." Journal of Materials Chemistry C, 2024. http://dx.doi.org/10.1039/d3tc03847e.

Full text

Abstract:

The resistive-switching-based logic gates are the promising electronic components for future digital logic operation in the integrated circuit based on resistive random access memories (RRAMs). Especially, the logic gates being...

APA, Harvard, Vancouver, ISO, and other styles

40

Ielmini, Daniele, Federico Nardi, Carlo Cagli, and Andrea L. Lacaita. "Size-dependent Temperature Instability in NiO–based Resistive Switching Memory." MRS Proceedings 1250 (2010). http://dx.doi.org/10.1557/proc-1250-g05-03.

Full text

Abstract:

AbstractResistive switching memory (RRAM) is attracting a strong interest as novel nonvolatile memories for high-density storage. Anyway this technology has to overcome two main issues before its use in real applications which are the high current needed for program operations and data retention stability. These two problems are here investigated from experimental and theoretical points of view to clarify the possibilities of NiO RRAMs to become a real competitive alternative to mainstream Flash technology.

APA, Harvard, Vancouver, ISO, and other styles

41

"Comprehensive Examination on Resistive Random Access Memory." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 4663–67. http://dx.doi.org/10.35940/ijrte.d8398.118419.

Full text

Abstract:

With the latest advances in materials science, resistive random access memory (RRAM) devices are attracting non-volatile, low power consumption, non-destructive read, and high density memory. Related performance parameters for RRAM devices include operating voltage, operating speed, resistivity, durability, retention time, device yield, and multi-level storage. Numerous resistive mechanisms, such as conductive filaments, space charge limited conduction, trap charging and discharging, Schottky emission, and pool-Frenkel emission, have been proposed to explain the resistance switches of RRAM devices. Therefore, in this work, different oxide-based random access memories (RRAMs) were provided for comprehensive investigation of neuromorphiccalculations. With the development of RRAM, the physical mechanism of conduction, the basic history of neuromorphic calculations begins. Finally, suggestions for future research, as well as waiting for the challenges of RRAM equipment, are given.

APA, Harvard, Vancouver, ISO, and other styles

42

Li, Yang, Shahar Kvatinsky, and Lior Kornblum. "Harnessing Conductive Oxide Interfaces for Resistive Random-Access Memories." Frontiers in Physics 9 (October 27, 2021). http://dx.doi.org/10.3389/fphy.2021.772238.

Full text

Abstract:

Two-dimensional electron gases (2DEGs) can be formed at some oxide interfaces, providing a fertile ground for creating extraordinary physical properties. These properties can be exploited in various novel electronic devices such as transistors, gas sensors, and spintronic devices. Recently several works have demonstrated the application of 2DEGs for resistive random-access memories (RRAMs). We briefly review the basics of oxide 2DEGs, emphasizing scalability and maturity and describing a recent trend of progression from epitaxial oxide interfaces (such as LaAlO3/SrTiO3) to simple and highly scalable amorphous-polycrystalline systems (e.g., Al2O3/TiO2). We critically describe and compare recent RRAM devices based on these systems and highlight the possible advantages and potential of 2DEGs systems for RRAM applications. We consider the immediate challenges to revolve around scaling from one device to large arrays, where further progress with series resistance reduction and fabrication techniques needs to be made. We conclude by laying out some of the opportunities presented by 2DEGs based RRAM, including increased tunability and design flexibility, which could, in turn, provide advantages for multi-level capabilities.

APA, Harvard, Vancouver, ISO, and other styles

43

Shen, Yang, He Tian, Yanming Liu, Fan Wu, Zhaoyi Yan, Thomas Hirtz, Xuefeng Wang, and Tian-Ling Ren. "Modeling of Gate Tunable Synaptic Device for Neuromorphic Applications." Frontiers in Physics 9 (December 24, 2021). http://dx.doi.org/10.3389/fphy.2021.777691.

Full text

Abstract:

The emerging memories are great candidates to establish neuromorphic computing challenging non-Von Neumann architecture. Emerging non-volatile resistive random-access memory (RRAM) attracted abundant attention recently for its low power consumption and high storage density. Up to now, research regarding the tunability of the On/Off ratio and the switching window of RRAM devices remains scarce. In this work, the underlying mechanisms related to gate tunable RRAMs are investigated. The principle of such a device consists of controlling the filament evolution in the resistive layer using graphene and an electric field. A physics-based stochastic simulation was employed to reveal the mechanisms that link the filament size and the growth speed to the back-gate bias. The simulations demonstrate the influence of the negative gate voltage on the device current which in turn leads to better characteristics for neuromorphic computing applications. Moreover, a high accuracy (94.7%) neural network for handwritten character digit classification has been realized using the 1-transistor 1-memristor (1T1R) crossbar cell structure and our stochastic simulation method, which demonstrate the optimization of gate tunable synaptic device.

APA, Harvard, Vancouver, ISO, and other styles

44

Yon, Victor, Amirali Amirsoleimani, Fabien Alibart, Roger G. Melko, Dominique Drouin, and Yann Beilliard. "Exploiting Non-idealities of Resistive Switching Memories for Efficient Machine Learning." Frontiers in Electronics 3 (March 25, 2022). http://dx.doi.org/10.3389/felec.2022.825077.

Full text

Abstract:

Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep learning and spiking neural networks. However, resistive switch technology is immature and suffers from numerous imperfections, which are often considered limitations on implementations of artificial neural networks. Nevertheless, a reasonable amount of variability can be harnessed to implement efficient probabilistic or approximate computing. This approach turns out to improve robustness, decrease overfitting and reduce energy consumption for specific applications, such as Bayesian and spiking neural networks. Thus, certain non-idealities could become opportunities if we adapt machine learning methods to the intrinsic characteristics of resistive switching memories. In this short review, we introduce some key considerations for circuit design and the most common non-idealities. We illustrate the possible benefits of stochasticity and compression with examples of well-established software methods. We then present an overview of recent neural network implementations that exploit the imperfections of resistive switching memory, and discuss the potential and limitations of these approaches.

APA, Harvard, Vancouver, ISO, and other styles

45

Vaccaro, Francesco, Stefano Brivio, Simona Perotto, Aurelio Giancarlo Mauri, and Sabina Spiga. "Physics-based compact modelling of the analog dynamics of HfOx resistive memories." Neuromorphic Computing and Engineering, May 25, 2022. http://dx.doi.org/10.1088/2634-4386/ac7327.

Full text

Abstract:

Abstract Resistive random access memories (RRAMs) constitute a class of memristive devices particularly appealing for bio-inspired computing schemes. In particular, the possibility of achieving analog control of the electrical conductivity of RRAM devices can be exploited to mimic the behaviour of biological synapses in neuromorphic systems. With a view to neuromorphic computing applications, it turns out to be crucial to guarantee some features, among which a detailed device characterization, a mathematical modelling comprehensive of all the key features of the device both in quasi-static and dynamic conditions, a description of the variability due to the inherently stochasticity of the processes involved in the switching transitions. In this paper, starting from experimental data, we provide a modelling and simulation framework to reproduce the operative analog behaviour of HfOx-based RRAM devices under train of programming pulses both in the analog and binary operation mode. To this aim, we have calibrated the model by using a single set of parameters for the quasi-static current-voltage characteristics as well as switching kinetics and device dynamics. The physics-based compact model here settled captures the difference between the SET and the RESET processes in the I-V characteristics, as well as the device memory window both for strong and weak programming conditions. Moreover, the model reproduces the correct slopes of the highly non-linear kinetics curves over several orders of magnitudes in time, and the dynamic device response including the inherent device variability.

APA, Harvard, Vancouver, ISO, and other styles

46

Rocha, Paulo F., Henrique L. Gomes, Asal Kiazadeh, Qian Chen, Dago M. de Leeuw, and Stefan C. J. Meskers. "Switching speed in Resistive Random Access Memories (RRAMS) based on plastic semiconductor." MRS Proceedings 1337 (2011). http://dx.doi.org/10.1557/opl.2011.859.

Full text

Abstract:

ABSTRACTThis work addresses non-volatile memories based on metal-oxide polymer diodes. We make a thorough investigation into the static and dynamic behavior. Current-voltage characteristics with varying voltage ramp speed demonstrate that the internal capacitive double-layer structure inhibits the switching at high ramp rates (typical 1000 V/s). This behavior is explained in terms of an equivalent circuit.It is also reported that there is not a particular threshold voltage to induce switching. Voltages below a particular threshold can still induce switching when applied for a long period of time. The time to switch is longer the lower is the applied voltage and follows an exponential behavior. This suggests that for a switching event to occur a certain amount of charge is required.

APA, Harvard, Vancouver, ISO, and other styles

47

Hyun, Gihwan, Batyrbek Alimkhanuly, Donguk Seo, Minwoo Lee, Junseong Bae, Seunghyun Lee, Shubham Patil, et al. "CMOS‐Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin." Small, April 12, 2024. http://dx.doi.org/10.1002/smll.202310943.

Full text

Abstract:

AbstractThe development of data‐intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory‐centric paradigm. Within this context, ternary content‐addressable memory (TCAM) can become an essential platform for high‐speed in‐memory matching applications of large data vectors. Compared to traditional static random‐access memory (SRAM) designs, TCAM technology using non‐volatile resistive memories (RRAMs) in two‐transistor‐two‐resistor (2T2R) configurations presents a cost‐efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory‐based TCAMs for large‐scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive‐bridge memories (CBRAMs) integrated with existing complementary metal‐oxide‐semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity‐enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM‐based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

APA, Harvard, Vancouver, ISO, and other styles

48

Choi, Hyun-Seok, Jihye Lee, Boram Kim, Jaehong Lee, Byung-Gook Park, Yoon Kim, and Suck Won Hong. "Highly-packed Self-assembled Graphene Oxide Film-Integrated Resistive Random-Access Memory on a Silicon Substrate for Neuromorphic Application." Nanotechnology, July 12, 2022. http://dx.doi.org/10.1088/1361-6528/ac805d.

Full text

Abstract:

Abstract Resistive random-access memories (RRAMs) based on metal-oxide thin films have been studied extensively for application as synaptic devices in neuromorphic systems. The use of graphene oxide (GO) as a switching layer offers an exciting alternative to other materials such as metal-oxides. For a GO-based RRAM device to be used as a synapse device, the gradual conductance modulation is generally required to imitate adaptive synaptic weight change. However, there have been few studies demonstrating synaptic behavior with gradual memory modulation from the perspective of realizing application in neuromorphic scenarios. We present a newly developed RRAM device fabricated by implementing close-packed GO layers on a highly doped Si wafer to yield a gradual modulation of the memory as a function of the number of input pulses. By using flow-enabled self-assembly, highly uniform GO thin films can be formed on flat Si wafers in a rapid and simple process. The switching mechanism was explored through proposed scenarios reconstructing the density change of the sp2 cluster in the GO layer, resulting in a gradual conductance modulation. Finally, through a pattern-recognition simulation with a modified national institute of standards and technology database, the feasibility of using close-packed GO layers as synapse devices was successfully demonstrated.

APA, Harvard, Vancouver, ISO, and other styles

49

Xie, Maosong, Yueyang Jia, Chen Nie, Zuheng Liu, Alvin Tang, Shiquan Fan, Xiaoyao Liang, Li Jiang, Zhezhi He, and Rui Yang. "Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory." Nature Communications 14, no. 1 (September 23, 2023). http://dx.doi.org/10.1038/s41467-023-41736-2.

Full text

Abstract:

AbstractEmerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

APA, Harvard, Vancouver, ISO, and other styles

50

Xi, Zhao-Ying, Li-Li Yang, Lin-Cong Shu, Mao-Lin Zhang, Shan Li, Li Shi, Zeng Liu, Yu-Feng Guo, and Wei-Hua Tang. "The growth and expansive applications of amorphous Ga₂O₃: a review." Chinese Physics B, April 24, 2023. http://dx.doi.org/10.1088/1674-1056/accf81.

Full text

Abstract:

Abstract As a promising ultra-wide bandgap semiconductor material, gallium oxide (Ga2O3) is attracting an extensive attention of researchers due to its feasible growth process, appropriate bandgap of 4.4-5.3 eV allowing for deep-ultraviolet (deep-UV) detection, good physical and chemical stability, high breakdown field strength and electron mobility, etc. Different from the strict processes for controllable crystalline Ga2O3 (usually refer to stable monoclinic β-Ga2O3), amorphous Ga2O3 (a-Ga2O3) film can be prepared uniformly at low temperature on a large-area deposition substrate, suggesting great advantages such as low manufacturing cost and excellent flexibility, dispensing with high-temperature and high vacuum techniques. Thus, a-Ga2O3 extremely facilitates important applications in various applied fields. Therefore, in this concise review, we summarized several major deposition methods for a-Ga2O3 films, of which the characteristics were discussed. Additionally, potential methods to optimize the film properties were proposed by right of the inspiration from some recent studies. Subsequently, the applications of a-Ga2O3 thin films, e.g., in photodetectors, resistive random access memories (RRAMs) and gas sensors, were represented with a fruitful discussion of their structures and operating mechanisms.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Resistive memories (RRAMs)'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles