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Journal articles on the topic 'Reliability of metallic interconnects'

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Author: Grafiati

Published: 10 December 2022

Last updated: 29 January 2023

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1

Zhao, Wen-Sheng, Kai Fu, Da-Wei Wang, Meng Li, Gaofeng Wang, and Wen-Yan Yin. "Mini-Review: Modeling and Performance Analysis of Nanocarbon Interconnects." Applied Sciences 9, no. 11 (May 28, 2019): 2174. http://dx.doi.org/10.3390/app9112174.

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As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic interconnects face several serious challenges in aspects of performance and reliability. To address these issues, nanocarbon materials, including carbon nanotube (CNT) and graphene, have been proposed as promising candidates for interconnect applications. Considering the rapid development of nanocarbon interconnects, this paper is dedicated to providing a mini-review on our previous work and on related research in this field.

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2

Kuruvilla, Nisha, J. P. Raina, Arun Greig John, and A. Athulya. "Performance and Reliability Analysis of Bundled SWCNT as IC Interconnects." Advanced Materials Research 129-131 (August 2010): 920–25. http://dx.doi.org/10.4028/www.scientific.net/amr.129-131.920.

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This work has investigated the performance of Single-walled carbon nanotube bundle as futuristic interconnect material under process constraints and compared its suitability as IC interconnect material as per ITRS predictions. It also analyzes variance of each parasitic effect along with the variations in process parameters. This paper pinpoints the variables causing bottlenecks in realizing optimum performance and improving reliability. It also evaluates the effect of diameter variations of CNTs in an SWCNT bundle and metallic tube ratio on the performance and reliability for 22nm technological node. The results demonstrate that the relative variations in the resistance are critically effected by the variations in metallic tube ratios rather than diameter variations. The diameter variation introduces its critical effect only at global level.

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3

Katkar, Rajesh, Michael Huynh, and Laura Mirkarimi. "Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 002404–23. http://dx.doi.org/10.4071/2011dpc-tha33.

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Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

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4

Gelatos, A. V., A. Jain, R. Marsh, and C. J. Mogab. "Chemical Vapor Deposition of Copper for Advanced On-Chip Interconnects." MRS Bulletin 19, no. 8 (August 1994): 49–54. http://dx.doi.org/10.1557/s0883769400047734.

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Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density, and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length will be at 0.18 μm, while microprocessors will pack more than 15 million transistors over an area ~700 mm. To conserve area, interconnects will continue to be stacked at an increasing number of levels (six by the year 2000, versus four in today's leading microprocessors), and the minimum spacing and width within an interconnect layer will shrink to 0.3 μm. In addition, it is expected that future interconnects will need to sustain increasingly higher current densities without electromigration failures.Aluminum alloys are the conductors of choice in present-day interconnects, and much effort is focused on means to extend the usefulness of aluminum through improvements in reliability, either by new alloy formulations or by the development of complicated multimetal stacks. A more radical approach, which is gaining increased attention, is the replacement of aluminum altogether by copper. The bulk resistivity of copper is significantly lower than that of aluminum (1.7 μΩ cm for Cu versus 3.0 μΩ cm for Al-Cu), which is expected to translate to interconnects of higher performance because of reduction in signal propagation delay. In addition, the significantly higher melting temperature of copper (~1100°C versus ~600°C for Al-Cu alloys) and its higher atomic weight are expected to translate to improved resistance to electromigration.

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5

Sasagawa, K., N. Yamaji, and S. Fukushi. "Threshold Current Density of Electromigration Damage in Angled Polycrystalline Line." Key Engineering Materials 353-358 (September 2007): 2958–61. http://dx.doi.org/10.4028/www.scientific.net/kem.353-358.2958.

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As silicon ICs continue to scale down, several reliability issues have emerged. Electromigration- the transportation of metallic atoms by the electron wind- has been recognized as one of the key damage mechanisms in metallic interconnects. It is known that there is a threshold current density of electromigration damage in via-connected lines. The evaluation of the threshold current density is a matter of the great interest from the viewpoint of IC reliability. In this study, Al polycrystalline lines with two-dimensional shape, i.e. angled lines are experimentally treated for the evaluation. Comparing the experimental result with that of straight-shaped line, the effect of line-shape on the threshold current density of electromigration damage is discussed.

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6

Chen, Giin-Shan, Ching-En Lee, Yi-Lung Cheng, Jau-Shiung Fang, Chien-Nan Hsiao, Wei-Chun Chen, Yiu-Hsiang Chang, Yen-Chang Pan, Wei Lee, and Ting-Hsun Su. "Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer." Journal of The Electrochemical Society 169, no. 8 (August 1, 2022): 082519. http://dx.doi.org/10.1149/1945-7111/ac89b8.

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The downsizing of integrated circuits for the upcoming technology nodes has brought attention to sub-2 nm thin organic/inorganic materials as an alternative to metallic barrier/capping layers for nanoscaled Cu interconnects. While self-assembled monolayers (SAMs) serving as the barrier materials for copper metalized films are well studied, electromigration (EM) of Cu interconnects encapsulated by SAMs is an untouched research topic. In this study, we report an all-wet encapsulating process involving SAM seeding/encapsulating and electroless narrow-gap filling to fabricate nanoscaled copper interconnects that are completely encapsulated by a 1 nm-thin amino-based SAM, subsequently annealed to some extents prior to EM testing. Both annealing and SAM encapsulation retard EM of the Cu interconnects tested at current densities on orders of 108–109 A cm−2. Particularly, SAM encapsulation quintuples the lifetime of, for example, as-fabricated Cu interconnects from 470 to 2,890 s. Electromigration failure mechanisms are elucidated from analyses of activation energies and current-density scale factors obtained from the accelerated EM testing. The importance of SAM qualities (e.g., ordering and layered structure) as a prerequisite for the reliability enhancement cannot be overestimated, and the results of the SAM quality evaluation are presented. The mechanism of reliability enhancement is also thoroughly discussed.

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7

Xu, Zhijie, Wei Xu, Elizabeth Stephens, and Brian Koeppel. "Mechanical reliability and life prediction of coated metallic interconnects within solid oxide fuel cells." Renewable Energy 113 (December 2017): 1472–79. http://dx.doi.org/10.1016/j.renene.2017.06.103.

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8

Saito, T., H. Ashihara, K. Ishikawa, M. Miyauchi, Y. Yamada, and H. Nakano. "A Reliability Study of Barrier-Metal-Clad Copper Interconnects With Self-Aligned Metallic Caps." IEEE Transactions on Electron Devices 51, no. 12 (December 2004): 2129–35. http://dx.doi.org/10.1109/ted.2004.838512.

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9

Amoah, Papa K., Christopher E. Sunday, Chukwudi Okoro, Jungjoon Ahn, Lin You, Dmitry Veksler, Joseph Kopanski, and Yaw Obeng. "(Invited) Towards the Physical Reliability of 3D-Integrated Systems: Broadband Dielectric Spectroscopic (BDS) Studies of Material Evolution and Reliability in Integrated Systems." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 859. http://dx.doi.org/10.1149/ma2022-0217859mtgabs.

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In this talk, we present an overview of our current research focus in developing non-destructive metrology for monitoring reliability issues in 3D-integrated electronic systems. Working closely with the semiconductor industry, we have been looking at various performance limiting phenomena in 3D-interconnects, the associated dielectrics, and advanced packaging for integrated circuits. The talk will identify some common reliability concerns, and identify some metrology gaps, for 3-D integrated systems. We will introduce a suite of microwave-based Broadband Dielectric Spectroscopic (BDS) techniques and show how these non-destructive metrologies can serve as early warning monitors for reliability issues. These techniques are based on the application of high frequency microwaves, to probe impedance changes due to material and structural changes in integrated circuits under various external stress. For example, we will also discuss the combination of BDS with scanning probe infrastructure to create the Scanning Microwave Microscopy (SMM) technique, which has been used to detect buried artifacts and characterize metallic contacts. We further illustrate the capabilities of the BDS-based techniques with case studies of three potential reliability issues in 3D IC. We conclude with a forward look at the future metrology and standards needs 3-D interconnects and the associated advanced packaging.

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10

Hau-Riege, Stefan P., and Carl V. Thompson. "The Effects of the Mechanical Properties of the Confinement Material on Electromigration in Metallic Interconnects." Journal of Materials Research 15, no. 8 (August 2000): 1797–802. http://dx.doi.org/10.1557/jmr.2000.0259.

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New low-dielectric-constant interlevel dielectrics are being investigated as alternatives to SiO2 for future integrated circuits. In general, these materials have very different mechanical properties from SiO2. In the standard model, electromigration-induced stress evolution caused by changes in the number of available lattice sites in interconnects is described by an effective elastic modulus, B. Finite element calculations were carried out to obtain B as a function of differences in the modulus, E, of interlevel dielectrics, for several stress-free homogeneous dilational strain configurations, for several line aspect ratios, and for different metallization schemes. In contradiction to earlier models, we found that for Cu-based metallization schemes with liners, a decrease in E by nearly two orders of magnitude has a relatively small effect on B, changing it by less than a factor of 2. However, B, and therefore the reliability of Cu interconnects, can be strongly dependent on the modulus and thickness of the liner material.

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11

Fu, C., D. L. McDowell, and I. C. Ume. "A Finite Element Procedure of a Cyclic Thermoviscoplasticity Model for Solder and Copper Interconnects." Journal of Electronic Packaging 120, no. 1 (March 1, 1998): 24–34. http://dx.doi.org/10.1115/1.2792281.

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A finite element procedure using a semi-implicit time-integration scheme has been developed for a cyclic thermoviscoplastic constitutive model for Pb-Sn solder and OFHC copper, two common metallic constituents in electronic packaging applications. The scheme has been implemented in the commercial finite element (FE) code ABAQUS (1995) via the user-defined material subroutine, UMAT. Several single-element simulations are conducted to compare with previous test results, which include monotonic tensile tests, creep tests, and a two-step ratchetting test for 62Sn36Pb2Ag solder; a nonproportional axial-torsional test and a thermomechanical fatigue (TMF) test for OFHC copper. At the constitutive level, we also provide an adaptive time stepping algorithm, which can be used to improve the overall computation efficiency and accuracy especially in large-scale FE analyses. We also compare the computational efforts of fully backward Euler and the proposed methods. The implementation of the FE procedure provides a guideline to apply user-defined material constitutive relations in FE analyses and to perform more sophisticated thermomechanical simulations. Such work can facilitate enhanced understanding thermomechanical reliability issue of solder and copper interconnects in electronic packaging applications.

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12

Tang, Jian She, Brian J. Brown, Steven Verhaverbeke, Han Wen Chen, Jim Papanu, Raymond Hung, Cathy Cai, and Dennis Yost. "Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow." Solid State Phenomena 103-104 (April 2005): 353–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.353.

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As device features scale down to 90nm and Cu/low-k films are employed for back end interconnects, post etch and ash residue cleaning becomes increasingly challenging due to the higher aspect ratio of the features, tighter CD control requirements, sensitivity of the low-k films, and the requirement for high wet etch selectivity between CuxO and Cu. Traditional solvent based cleaning in wet benches has additional issues such as wafer cross-contamination and high disposal cost [1, 2]. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. The results of physical characterization, process integration electrical data, and process integration reliability data such as electromigration (EM) and stress migration data are presented. The main conclusions can be summarized as follows: (1) The single wafer cleaning process developed on the Oasis™ system can clean post etch residues and simultaneously clean the wafer front side and backside metallic contaminants; (2) In terms CuxO and Cu wet etch selectivity, CD loss control, the Oasis™ aqueous single wafer clean process is superior to the bench solvent cleaning process; (3)The Oasis aqueous cleaning process shows no undercut below etchstop due to the very low Cu etch amount in one cleaning pass, therefore the electromigration and stress migration performance of the aqueous Oasis processed wafers is clearly better than that of the solvent bench processed wafers.

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13

Ogurtani, Tarik Omer, and Oncu Akyildiz. "Morphological Evolution of Intragranular Void under the Thermal-Stress Gradient Generated by the Steady State Heat Flow in Encapsulated Metallic Films: Special Reference to Flip Chip Solder Joints." Solid State Phenomena 139 (April 2008): 151–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.139.151.

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The morphological evolution of intragranular voids induced by the surface drift-diffusion under the action of capillary forces, electromigration (EM) forces, and thermal stress gradients (TSG) associated with steady state heat flow is investigated in passivated metallic thin films via computer simulation using the front-tracking method. As far as the device reliability is concerned, the most critical configuration for interconnect failure occurs even when thermal stresses are low if the normalized ratio of interconnect width to void radius is less than certain range of values (which indicates the onset of heat flux crowding). This regime manifests itself by the formation of two symmetrically disposed finger shape extrusions (pitchfork shape slits) on the upper and lower shoulders of the void surface on the windward side. The void growth (associated with supersaturated vacancy condensation) on the other hand inhibits anode displacement but enhances cathode and shoulder slit velocities drastically, which causes lateral spreading.

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14

Whitt, Reece, and David Huitink. "THERMAL VALIDATIONS OF ADDITIVE MANUFACTURED NON-METALLIC HEAT SPREADING DEVICE FOR HOT SPOT MITIGATION IN POWER MODULES." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000398–403. http://dx.doi.org/10.4071/2380-4505-2019.1.000398.

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Abstract As energy demands and power electronics density scale concurrently, reliability of such devices is being challenged. Inadequate thermal management can cause system-wide failures due to thermal run-away, thermal expansion induced stresses, interconnect fractures and many more. Conventional techniques used to cool devices consist of heavy, metallic systems such as cold plates and large heat sinks, which can significantly reduce the overall system power density. Moreover, the manufacturing of such components is expensive and often requires custom-made cold plates for improved integration with the electronic system. Although used as a standard practice, these metallic thermal management systems have the potential to intensify electro-magnetic interference (EMI) when coupling with high frequency switching power electronics, and the material density increases the weight of the system, which is detrimental in mobile applications. Lastly, cold plates and heat sinks can create non-uniform cooling profiles in the electronics due to the insufficient management of hot-spots. To combat these drawbacks, a new heat spreader design has been proposed which reduces weight and EMI effects while eliminating hot-spots through localized fluid impingement. This current study describes the methodology and construction of the experimental test setup to characterize the performance of the heat spreading device compared to an off-the-shelf cold plate. Through infrared imagining, the viability of two heated test sections are evaluated in their ability to replicate power module temperature profiles during operation.

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15

Nair, K. M., M. F. McCombs, K. E. Souders, and S. E. Gordon. "New Mixed Metal Transition Via-Fill Conductors for Cost Effective DuPont GreenTape™ 951 & 9K7 LTCC Circuits." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000254–60. http://dx.doi.org/10.4071/isom-2010-tp3-paper3.

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LTCC (Low Temperature Co-fired Ceramic) technology provides an option for circuit designers that combines the benefits of HTCC and thick film technologies and is the technology of choice for many complex automotive, consumer, and military applications. For demanding and high reliability applications, LTCC circuits containing gold conductors for all ground planes, signal traces, and via fills are common. With the rise in gold cost from $400/TO in 2005 to a recent peak of over $1,200/TO in 2009, OEMs and circuit designers are forced to seek lower cost alternatives to all gold LTCC structures. The use of all silver conductors raises questions of reliability, especially for the external silver layers, and wire-bonding to silver is not possible. The traditional method employed to address cost and reliability has been the use of mixed metallurgies, rather than using gold throughout the LTCC module. Silver based conductors for signal and ground are used internally, with gold conductors for wire bonding, brazing, or soldering on the external surfaces. Today there are two primary options to achieve this type of structure: 1) Ni/Au plating the top silver surface; or 2) Use of precious metal based transition via fill compositions that interconnect the silver to the gold conductors. Traditional LTCC transition via fills compositions have consisted of Pd/Ag or Pd/Pt/Ag mixtures. However, such systems may be disposed to certain phenomena at the surface interface(s) between dissimilar metals. For example, the Kirkendall Effect has been found in various alloy systems and can impact the bonding between different materials. In particular, it has been studied and is used to describe voids that are produced in the boundary region at a bonding interface especially during high temperature processes such as metallic powder sintering. This paper introduces two new mixed metal via-fill conductors that are compatible with the DuPont GreenTape™ 951 and 9K7 LTCC systems. Reliability and refire stability are described in detail.

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16

Placha, Katarzyna, Richard S. Tuley, Milena Salvo, Valentina Casalegno, and Kevin Simpson. "Solid-Liquid Interdiffusion (SLID) Bonding of p-Type Skutterudite Thermoelectric Material Using Al-Ni Interlayers." Materials 11, no. 12 (December 6, 2018): 2483. http://dx.doi.org/10.3390/ma11122483.

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Over the past few years, significant progress towards implementation of environmentally sustainable and cost-effective thermoelectric power generation has been made. However, the reliability and high-temperature stability challenges of incorporating thermoelectric materials into modules still represent a key bottleneck. Here, we demonstrate an implementation of the Solid-Liquid Interdiffusion technique used for bonding Mmy(Fe,Co)4Sb12 p-type thermoelectric material to metallic interconnect using a novel aluminium–nickel multi-layered system. It was found that the diffusion reaction-controlled process leads to the formation of two distinct intermetallic compounds (IMCs), Al3Ni and Al3Ni2, with a theoretical melting point higher than the initial bonding temperature. Different manufacturing parameters have also been investigated and their influence on electrical, mechanical and microstructural features of bonded components are reported here. The resulting electrical contact resistances and apparent shear strengths for components with residual aluminium were measured to be (2.8 ± 0.4) × 10−5 Ω∙cm2 and 5.1 ± 0.5 MPa and with aluminium completely transformed into Al3Ni and Al3Ni2 IMCs were (4.8 ± 0.3) × 10−5 Ω∙cm2 and 4.5 ± 0.5 MPa respectively. The behaviour and microstructural changes in the joining material have been evaluated through isothermal annealing at hot-leg working temperature to investigate the stability and evolution of the contact.

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17

Sung, Po-Hsien, and Tei-Chen Chen. "Material Properties of Zr–Cu–Ni–Al Thin Films as Diffusion Barrier Layer." Crystals 10, no. 6 (June 24, 2020): 540. http://dx.doi.org/10.3390/cryst10060540.

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Due to the rapid increase in current density encountered in new chips, the phenomena of thermomigration and electromigration in the solder bump become a serious reliability issue. Currently, Ni or TiN, as a barrier layer, is widely academically studied and industrially accepted to inhibit rapid copper diffusion in interconnect structures. Unfortunately, these barrier layers are polycrystalline and provide inadequate protection because grain boundaries may presumably serve as fast diffusion paths for copper and could react to form Cu–Sn intermetallic compounds (IMCs). Amorphous metallic films, however, have the potential to be the most effective barrier layer for Cu metallization due to the absence of grain boundaries and immiscibility with copper. In this article, the diffusion properties, the strength of the interface between polycrystalline and amorphous ZrCuNiAl thin film, and the effects of quenching rate on the internal microstructures of amorphous metal films were individually investigated by molecular dynamics (MD) simulation. Moreover, experimental data of the diffusion process for three different cases, i.e., without barrier layer, with an Ni barrier layer, and with a Zr53Cu30Ni9Al8 thin film metallic glass (TFMG) barrier layer, were individually depicted. The simulation results show that, for ZrCuNiAl alloy, more than 99% of the amorphous phase at a quenching rate between 0.25 K/ps and 25 K/ps can be obtained, indicating that this alloy has superior glass-forming ability. The simulation of diffusion behavior indicated that a higher amorphous ratio resulted in better barrier performance. Moreover, a very small and uniformly distributed strain appears in the ZrCuNiAl layer in the simulation of the interfacial tension test; however, almost all the voids are initiated and propagated in the Cu layer. These phenomena indicate that the strength of the ZrCuNiAl/Cu interface and ZrCuNiAl layer is greater than polycrystalline Cu. Experimental results show that the Zr53Cu30Ni9Al8 TFMG layer exhibits a superior barrier effect. Almost no IMCs appear in this TFMG barrier layer even after aging at 125 °C for 500 h.

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18

Naeemi, A., and J. D. Meindl. "Monolayer metallic nanotube interconnects: promising candidates for short local interconnects." IEEE Electron Device Letters 26, no. 8 (August 2005): 544–46. http://dx.doi.org/10.1109/led.2005.852744.

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19

Li, Baozhen, Timothy D. Sullivan, Tom C. Lee, and Dinesh Badami. "Reliability challenges for copper interconnects." Microelectronics Reliability 44, no. 3 (March 2004): 365–80. http://dx.doi.org/10.1016/j.microrel.2003.11.004.

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20

Fergus, Jeffrey W. "Metallic interconnects for solid oxide fuel cells." Materials Science and Engineering: A 397, no. 1-2 (April 2005): 271–83. http://dx.doi.org/10.1016/j.msea.2005.02.047.

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21

Gaetano Chiariello, Andrea, Giovanni Miano, Antonio Maffucci, Fabio Villone, and Walter Zamboni. "Electromagnetic models for metallic carbon nanotube interconnects." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 26, no. 3 (June 19, 2007): 571–85. http://dx.doi.org/10.1108/03321640710751064.

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22

Hu, Yaoqiao, Patrick Conlin, Yeonghun Lee, Dongwook Kim, and Kyeongjae Cho. "van der Waals 2D metallic materials for low-resistivity interconnects." Journal of Materials Chemistry C 10, no. 14 (2022): 5627–35. http://dx.doi.org/10.1039/d1tc05872j.

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2D metallic materials offer a solution to the problem of poor scalability of elemental metals within ever-downscaling device interconnects. With the absence of surface scattering, they could be used for interconnects in future integrated circuits.

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23

Baklanov, Mikhail R., Christoph Adelmann, Larry Zhao, and Stefan De Gendt. "Advanced Interconnects: Materials, Processing, and Reliability." ECS Journal of Solid State Science and Technology 4, no. 1 (December 17, 2014): Y1—Y4. http://dx.doi.org/10.1149/2.0271501jss.

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24

Changsup Ryu, Kee-Won Kwon, A. L. S. Loke, Haebum Lee, T. Nogami, V. M. Dubin, R. A. Kavari, G. W. Ray, and S. S. Wong. "Microstructure and reliability of copper interconnects." IEEE Transactions on Electron Devices 46, no. 6 (June 1999): 1113–20. http://dx.doi.org/10.1109/16.766872.

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25

Dudek, Rainer, Peter Sommer, Andreas Fix, Joerg Trodler, Sven Rzepka, and Bernd Michel. "Reliability investigations for high temperature interconnects." Soldering & Surface Mount Technology 26, no. 1 (January 28, 2014): 27–36. http://dx.doi.org/10.1108/ssmt-10-2013-0030.

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Purpose – Because of the need for electronics use at temperatures beyond 150°C, high temperature resistant interconnection technologies like transient liquid phase (TLP) soldering and silver sintering are being developed which are not only replacements of high-lead solders, but also open new opportunities in terms of temperature resistance and reliability. The paper aims to address the thermo-mechanical reliability issues that have to be considered if the new interconnection technologies will be applied. Design/methodology/approach – A TLP soldering technique is briefly introduced and new challenges concerning the thermo-mechanical reliability of power devices are worked out by numerical analysis (finite element simulation). They arise as the material properties of the interconnect materials differ substantially from those known for soft solders. The effective material responses of the new materials are determined by localized unit cell models that capture the inhomogeneous structure of the materials. Findings – It is shown that both the TLP solder layer and the Ag-sinter layer have much less ductility and show less creep than conventional soft solders. The potential failure modes of an assembly made by TLP soldering or Ag sintering change. In particular, the characteristic low cycle fatigue solder failures become unlikely and are replaced either by metallization fatigue, brittle failure of intermetallic compound, components, or interfaces. Originality/value – A variety of new failure risks, which have been analyzed theoretically, can be avoided only if they are known to the potential user of the new techniques. It is shown that an optimal reliability will be strongly dependent on the actual assembly design.

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26

Tőkei, Zsolt, Kristof Croes, and Gerald P. Beyer. "Reliability of copper low-k interconnects." Microelectronic Engineering 87, no. 3 (March 2010): 348–54. http://dx.doi.org/10.1016/j.mee.2009.06.025.

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27

McPherson, J. W., H. A. Le, and C. D. Graas. "Reliability challenges for deep submicron interconnects." Microelectronics Reliability 37, no. 10-11 (October 1997): 1469–77. http://dx.doi.org/10.1016/s0026-2714(97)00089-9.

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28

Kopera, Paul M. "Reliability of passive fiber-optic interconnects." Fiber and Integrated Optics 9, no. 1 (March 1990): 53–59. http://dx.doi.org/10.1080/01468039008202894.

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29

Tang, Liang. "Commentary: Metallic nanodevices for chip-scale optical interconnects." Journal of Nanophotonics 3, no. 1 (March 1, 2009): 030302. http://dx.doi.org/10.1117/1.3111849.

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30

Harris, D. B., and M. G. Pecht. "A Reliability Study of Fuzz Button Interconnects." Circuit World 21, no. 2 (February 1995): 12–18. http://dx.doi.org/10.1108/eb046298.

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31

Gambino, Jeff, Tom C. Lee, Fen Chen, and Timothy D. Sullivan. "Reliability of Copper Interconnects: Stress-Induced Voids." ECS Transactions 18, no. 1 (December 18, 2019): 205–11. http://dx.doi.org/10.1149/1.3096451.

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Hassan, Muhammad Aqib, and Othman Bin Mamat. "Mitigation of Chromium Poisoning of Ferritic Interconnect from Annealed Spinel of CuFe2O4." Processes 8, no. 9 (September 8, 2020): 1113. http://dx.doi.org/10.3390/pr8091113.

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Low-temperature solid oxide fuel cells permit the possibility of metallic interconnects over conventional ceramic interconnects. Among various metallic interconnects, the ferritic interconnects are the most promising. However, chromium poisoning in them adversely affects their performance. To resolve this issue, various coatings and pretreatment methods have been studied. Herein, this article encloses the coating of CuFe2O4 spinel over two prominent ferritic interconnects (Crofer 22 APU and SUS 430). The CuFe2O4 spinel layer coating has been developed by the dip-coating of both samples in CuFe2O4 slurry, followed by heat treatment at 800 °C in a reducing environment (5% hydrogen and 95% nitrogen). Additionally, both samples were annealed to further enhance their spinel coating structure. The morphological and crystallinity analysis confirmed that the spinel coating formed multiple layers of protection while annealing further reduced the thickness and improved the densities. Moreover, the area-specific resistance (ASR) and weight gain rate (WGR) of both samples before and after annealing was calculated using mathematical modeling, which matches with the experimental data. It has been noted that CuFe2O4 spinel coating improved the ASR and WGR of both samples which were further improved after annealing. This research reveals that the CuFe2O4 spinel is the promising protective layer for ferritic interconnects and annealing is the better processing technique for achieving the preferred properties.

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Hwang, Byungil, Yurim Han, and Paolo Matteini. "BENDING FATIGUE BEHAVIOR OF AG NANOWIRE/CU THIN-FILM HYBRID INTERCONNECTS FOR WEARABLE ELECTRONICS." Facta Universitatis, Series: Mechanical Engineering 20, no. 3 (November 30, 2022): 553. http://dx.doi.org/10.22190/fume220730040h.

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Enhancing the mechanical reliability of metal interconnects is important for achieving highly reliable flexible/wearable electronic devices. In this study, Ag nanowire and Cu thin-film hybrid interconnects were explored as a novel concept to enhance mechanical reliability under bending fatigue. Bending fatigue tests were conducted on the Cu thin films and Cu/Ag nanowire/polyimide (CAP) interconnects. The increase in resistance was larger for the Cu thin films than for the CAP. The single-component Cu electrodes showed multiple crack initiation and propagation due to bending strain, which degraded the electrical conductivity. In CAP, however, no long-range cracks were observed, even after 300,000 cycles of bending, although a wavy structure was observed, probably due to the delamination of the Ag nanowires under repeated bending. Our study confirms that flexible Ag nanowire and metal thin-film hybrids can enhance the mechanical reliability of metal thin-film interconnects under bending fatigue.

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Brylewski, Tomasz, and Kazimierz Przybylski. "Perovskite and Spinel Functional Coatings for SOFC Metallic Interconnects." Materials Science Forum 595-598 (September 2008): 813–22. http://dx.doi.org/10.4028/www.scientific.net/msf.595-598.813.

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The oxidation kinetics, electrical properties, microstructure and chromium vaporization effects of the oxide products formed on Fe-25 wt.-%Cr steel uncoated and coated with films of (La,Sr)CrO3, (La,Sr)CoO3, (La,Sr)(Co,Fe)O3, Mn1.5Cr1.5O4 and MnCo2O4 in air and the Ar-H2-H2O gas mixture at 1023−1173 K for up to 840 h with regard to their application as SOFC metallic interconnect were investigated. To improve poor electrical conductivity of chromia scales and to suppress chromium vaporization from this scale grown on uncoated steel during oxidation, the perovskite and spinel thick films composed of paste prepared via co-precipitation-calcination and ultrasonic spray pyrolysis methods were applied. Perovskite and spinel coatings decreased the volatilization rate of chromia species in comparison with the value of this parameter corresponding to oxide scales built mainly of chromia formed on uncoated steel. Microstructure investigations by the SEM-EDS method and electrical resistance measurements revealed the significant influence of the formation of multilayer reaction products at the steel/coating interface on the electrical properties of the composite materials used for the construction of the SOFC metallic interconnect.

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Zeng, Z. "Corrosion of metallic interconnects for SOFC in fuel gases." Solid State Ionics 167, no. 1-2 (February 12, 2004): 9–16. http://dx.doi.org/10.1016/j.ssi.2003.11.026.

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Armstrong, Tad J. "Oxidation Kinetics of Metallic Interconnects for Intermediate Temperature SOFC." ECS Proceedings Volumes 2005-07, no. 1 (January 2005): 1795–805. http://dx.doi.org/10.1149/200507.1795pv.

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Holcomb, Gordon R., Malgorzata Ziomek-Moroz, Stephen D. Cramer, Bernard S. Covino, and Sophie J. Bullard. "Dual-Environment Effects on the Oxidation of Metallic Interconnects." Journal of Materials Engineering and Performance 15, no. 4 (August 1, 2006): 404–9. http://dx.doi.org/10.1361/105994906x117198.

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38

Maffucci, A., G. Miano, and F. Villone. "A transmission line model for metallic carbon nanotube interconnects." International Journal of Circuit Theory and Applications 36, no. 1 (January 2008): 31–51. http://dx.doi.org/10.1002/cta.396.

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39

Kacker, Karan, and Suresh K. Sitaraman. "Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 59–65. http://dx.doi.org/10.4071/1551-4897-6.1.59.

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Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

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Coakley, Kevin J., Pavel Kabos, Stephane Moreau, and Yaw Obeng. "(Invited) Empirical Modeling of Broadband Insertion Losses in TSV-Interconnects." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 860. http://dx.doi.org/10.1149/ma2022-0217860mtgabs.

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The reliability of through silicon via (TSV)-interconnects depends on various factors including construction materials, fabrication location on wafers, thermal history, operating conditions and integration schemes. The magnitude of the frequency-dependent $S_{21}$ microwave scattering parameter quantifies insertion losses in TSV-interconnects. We attribute these losses (which affect device reliability) to reorientation of electrically active defects, cracks, voids, dielectric constant variation, and water molecules affected by heat. We model these insertion losses with an equivalent circuit model. We estimate model parameters with a stochastic optimization implementation of the Levenberg-Marquadt method. For TSV-interconnects from two different providers, we quantify how estimated model parameters vary spatially (on a wafer), and how estimated parameters vary with thermal cycles for TSV-interconnects fabricated at particular wafer locations.

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Hsu, Yung-Yu, Cole Papakyrikos, Daniel Liu, Xianyan Wang, Milan Raj, Baosheng Zhang, and Roozbeh Ghaffari. "Design for reliability of multi-layer stretchable interconnects." Journal of Micromechanics and Microengineering 24, no. 9 (August 11, 2014): 095014. http://dx.doi.org/10.1088/0960-1317/24/9/095014.

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Nguyen, Luu T. "Foreword Wafer-Level Packaging: Interconnects for Enhanced Reliability." IEEE Transactions on Advanced Packaging 32, no. 2 (May 2009): 360–61. http://dx.doi.org/10.1109/tadvp.2009.2022602.

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43

Huang, M. L. "(Invited) Electromigration Reliability of Lead-Free Solder Interconnects." ECS Transactions 60, no. 1 (February 27, 2014): 811–16. http://dx.doi.org/10.1149/06001.0811ecst.

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44

Igarashi, Yasushi, Tomomi Yamanobe, and Toshio Ito. "High-Reliability Copper Interconnects through Dry Etching Process." Japanese Journal of Applied Physics 34, Part 1, No. 2B (February 28, 1995): 1012–15. http://dx.doi.org/10.1143/jjap.34.1012.

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45

Robert Kao, C., Albert T. Wu, King-Ning Tu, and Yi-Shao Lai. "Reliability of micro-interconnects in 3D IC packages." Microelectronics Reliability 53, no. 1 (January 2013): 1. http://dx.doi.org/10.1016/j.microrel.2012.11.005.

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46

Sato, Motonobu, Takashi Hyakushima, Akio Kawabata, Tatsuhiro Nozue, Shintaro Sato, Mizuhisa Nihei, and Yuji Awano. "High-Current Reliability of Carbon Nanotube Via Interconnects." Japanese Journal of Applied Physics 49, no. 10 (October 20, 2010): 105102. http://dx.doi.org/10.1143/jjap.49.105102.

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47

Keller, Robert. "(Invited) Assessing Reliability of Materials for Electronic Interconnects." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 861. http://dx.doi.org/10.1149/ma2022-0217861mtgabs.

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Reliability of materials refers to how well an engineered material performs its intended function over a targeted design lifetime. Quantitatively, reliability is defined as (1 − probability of failure). Because a material’s physical properties are determined by its atomic makeup, reliable material function fundamentally depends on the stability of atomic structure as that material sees continued exposure to operational conditions. From the interconnect perspective, the primary functions include routing signal and power within and between devices or other subcomponents. Any disruptions to the atomic arrangement of materials used as interconnects therefore change the ability of those interconnects to perform those functions. An important aspect of designing these structures for high reliability therefore involves measuring and understanding how operational stressors can lead to the formation and evolution of defects in atomic structure over time. This type of knowledge can then at a minimum be used to predict when those effects unacceptably compromise interconnect functionality. Better yet, it can be used to improve material processing to slow or even eliminate damage. While interconnect technology has undergone significant changes and improvements over the years due to new materials, material systems, dimensions, and architectures, the fundamental factors that remain a chronic concern for reliability of interconnects used in BEOL and packaging are a combination of temperature, electric current, and mechanical strain. Our work addresses methods to test, detect, and ultimately control material defects, reliability, and failure. In this contribution, I will summarize some of our work to measure damage due to thermal fatigue and electromigration in several materials, including aluminum, copper, carbon nanotubes, and 2D molybdenum disulfide. I will also summarize some of our recent developments in material characterization, which we believe can play an important role in assessing material reliability for the semiconductor industry.

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48

Xu, Pingye, and Michael C. Hamilton. "Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 002082–94. http://dx.doi.org/10.4071/2015dpc-tha32.

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With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

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Kacker, Karan, Thomas Sokol, Wansuk Yun, Madhavan Swaminathan, and Suresh K. Sitaraman. "A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance." Journal of Electronic Packaging 129, no. 4 (April 9, 2007): 460–68. http://dx.doi.org/10.1115/1.2804096.

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Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

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D, Nirmal. "DESIGN AND EFFICIENCY ANALYSIS OF NANOCARBON INTERCONNECT STRUCTURES." Journal of Electronics and Informatics 01, no. 01 (September 6, 2019): 12–23. http://dx.doi.org/10.36548/jei.2019.1.002.

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With significant reduction in the size of ICs, there has been a massive increase in the operating speed. Due to this condition, the area available for interconnects within the transistor and between transistors in an IC is greatly reduced. Carbon wires pose high resistance and power dissipation in constrained space. It is necessary to opt efficient means to overcome this issue. The drawbacks of traditional metallic interconnects are overcome by nanocarbon interconnects. Considering factors such as shrinking dimensions, interconnect delay and power dissipation, we have considered four nanocarbon interconnect structures for analysis in this paper. The design and efficiency are analysed for Graphene Nanoribbon (GNR), Carbon Nanotube, Cu-Nanocarbon and All Carbon 3-D interconnects.

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