Dissertations / Theses on the topic 'Reliability of metallic interconnects'
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Gurrum, Siva P. "Thermal Modeling and Characterization of Nanoscale Metallic Interconnects." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10435.
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Temperature rise due to Joule heating of on-chip interconnects can severely affect performance and reliability of next generation microprocessors. Thermal predictions become difficult due to large number of features, and the impact of electron size effects on electrical and thermal transport. It is thus necessary to develop efficient numerical approaches, and accurate metal and dielectric thermal characterization techniques. In this research, analytical, numerical, and experimental techniques were developed to enable accurate and efficient predictions of interconnect temperature rise.
A finite element based compact thermal model was developed to obtain temperature rise with fewer elements and acceptable accuracy. Temperature drop across the interconnect cross-section was ignored. The compact model performed better than standard finite element model in two and three-dimensional case studies, and the predictions for a real world structure agreed closely with experimentally measured temperature rise.
A numerical solution was developed for electron transport based on the Boltzmann Transport Equation (BTE). This deterministic technique, based on the path integral solution of BTE within the relaxation time approximation, free electron model, and linear response, was applied to a constriction in a finite size thin metallic film. A correlation for effective conductance was obtained for different constriction sizes.
The Atomic Force Microscope (AFM) based Scanning Joule Expansion Microscopy (SJEM) was used to develop a new technique to measure thermal conductivity of thin metallic films in the size effect regime. This technique does not require suspended metal structures, and thus preserves the original electron interface scattering characteristics. The thermal conductivities of 43 nm and 131 nm gold films were extracted to be 82 W/mK and 162 W/mK respectively. These measurements were close to Wiedemann-Franz Law predictions and are significantly smaller than the bulk value of 318 W/mK due to electron size effects. The technique can potentially be applied to interconnects in the sub-100 nm regime.
A semi-analytical solution for the 3-omega method was derived to account for thermal conduction within the metallic heater. It is shown that significant errors can result when the previous solution is applied for anisotropic thermal conductivity measurements.
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Choi, Zung-Sun. "Reliability of copper interconnects in integrated circuits." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/39553.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.
As dimensions shrink and current densities increase, the reliability of metal interconnects becomes a serious concern. In copper interconnects, the dominant diffusion path is along the interface between the copper and the top passivation layer (usually Si3N4). One of the predominant failure mechanisms in Cu has been open-circuit failure due to electromigration-induced void nucleation and growth near the cathode ends of interconnect segments. However, results from accelerated electromigration tests show that the simple failure analyses based on simple void nucleation and growth can not explain the wide range of times-to-failure that are observed, suggesting that other types of failure mechanisms are present. In this thesis, by devising and performing unique experiments through the development of an electromigration simulation tool, unexpected complex failure mechanisms have been identified that have significant effects on the reliability of copper interconnects. A simulation tool was developed by implementing the one-dimensional non-linear differential equation model first described by Korhonen et al. By applying an implicit method (Backward Euler method), the calculation time was significantly reduced, and stability increased, compared to previous tools based on explicit methods (Forward Euler method).
(cont.) The tool was crosschecked with experimental results by comparing void growth rates in simulations and experiments. Using this tool, one can simulate stress and atomic concentration states over the entire length of an interconnect segment or throughout a multi-segment interconnect tree, to identify analyze possible failure locations and mechanisms. Experiments were carried out on dotted-i structures, where two 25jim-lomg segments were connected by a via in the middle. Electrical currents were applied to the two segments independently, and lifetime effects of adjacent segments were determined. Using the simulation tool and calculations, it was shown that adjacent segments have a significant effect on a segment's stress state, even if the adjacent segment has no electrical current. This explains experimental observations. This also suggests that for reliability analyses to be accurate, the states of all adjacent segments must be considered, including the ones without electrical current. In a second set of experiments, the importance of pre-existing voids was investigated. Using in-situ scanning electron microscopy, voids away from the cathode were observed. These voids grew and drifted toward the cathode and the shape of the voids were found to be closely related to the texture and stress state of individual grains in the interconnect.
(cont.) The drift velocity of voids was shown to be directly proportional to surface diffusivity. Electromigration tests on unpassivated samples were performed under vacuum to obtain the surface diffusivity of copper and its dependence on texture orientations. Simulation results show that pre-existing voids cause void growth away from the cathode. Subsequent failure mechanisms differ depending on the location of the pre-existing void and the critical void volume for de-pinning from grain boundaries. If pre-existing voids are present, void-growth-limited failure is expected in interconnects at low current densities, due to growth of pre-existing void, and the lifetimes are expected to scale inversely with j. However, at higher current densities (typical for accelerated testing), failure can occur through nucleation of new voids at the cathode (so that lifetimes scale inversely with j2), or through a mixture of nucleation of new voids and growth of pre-existing voids. These effects must be taken into account to accurately project the reliability of interconnects under service conditions, based on experiments carried out under accelerated conditions.
by Zung-Sun Choi.
Ph.D.
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Garcia-Vargas, Maria José. "Oxidation behaviour of potential materials for metallic SOFC interconnects." Lille 1, 2006. https://pepite-depot.univ-lille.fr/RESTREINT/Th_Num/2006/50376_2006_208.pdf.
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Les interconnecteurs de SOFC à haute température ont deux rôles principaux: la connexion électrique entre les cellules et l'approvisionnement des gaz dans le stack. Ce travail porte sur l'étude d'interconnecteurs métalliques pour SOFC fonctionnant à une température d'environ 800°e. Deux matériaux austénitiques et trois ferritiques, ayant un pourcentage de Cr compris entre 17% et 27%, ont été sélectionnés pour étudier le comportement en oxydation dans différentes atmosphères. Une étude par diffraction des rayons-X (ORX) du comportement d'oxydation de ces matériaux à 800°C a été réalisée pendant les premières 100 h sous air sec et humide. Des essais d'oxydation à moyen terme (1000 h) ont été de plus réalisés. Chaque échantillon a été caractérisé microscopiquement après les essais d'oxydation à temps court et à moyen terme. Pour éviter le problème de la migration du chrome, montré par les études précédentes sur ce type de matériaux, deux couches protectrices de type spinelle ont été développées. Ensuite, quelques échantillons ont été recouverts avec ces couches de protection en utilisant la projection au plasma atmosphérique (APS). Des essais d'oxydation à moyen terme ont été réalisés, sans montrer de migration du chrome à travers la couche de protection. Finalement trois interconnecteurs, avec ou sans une couche de protection, ont été essayés sur la cathode d'une cellule. Les interconnecteurs et les cellules ont été analysées par MEB, après chaque test.
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Gall, Martin. "Investigation of electromigration reliability in Al(Cu) interconnects /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Bashir, Muhammad Muqarrab. "Modeling reliability in copper/low-k interconnects and variability in cmos." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41092.
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The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown.
A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.
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Garcia-Vargas, Maria J. [Verfasser]. "Oxidation behaviour of potential materials for metallic SOFC interconnects / Maria J Garcia-Vargas." Aachen : Shaker, 2007. http://d-nb.info/1170527221/34.
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Zheng, Yunqi. "Effect of surface finishes and intermetallics on the reliability of SnAgCu interconnects." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/2427.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Lee, Kitae 1966. "The influence of texture on the reliability of aluminum and copper interconnects /." Thesis, McGill University, 2000. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=37759.
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Texture in films develops during deposition processes and annealing of patterned wafers. Recent studies show that texture influences the performance and reliability of both aluminum and copper interconnects. To improve the current understanding of this matter, the influence of texture on reliability was studied.The influence of texture on electromigration and stress-induced failures in aluminum interconnects was studied since these are the most often responsible for failures observed in aluminum interconnects. Results obtained showed that a strong {111} texture in aluminum interconnects improves their median time-to-failure. The grain boundary character distribution and percentage of coincidence site lattice (CSL) boundaries, was quantified using orientation imaging microscopy. It was found that the median time-to-failure of specimens increased as the number of low angle and CSL boundaries increased. These boundaries are known to have low diffusivity. It was also demonstrated that while the investigated specimens had grains of comparable size, the grains of similar orientations were clustered in the specimens having the stronger {111} texture. This phenomenon contributed to the longer median time-to-failure of the interconnects by reducing the frequency of high angle grain boundaries. The experimental data obtained shows that the residual stress in films decreases as the intensity of the {111} texture increases. A model based on Monte-Carlo simulation of texture formation during the deposition of aluminum film was proposed to suggest the optimum conditions for a growth of a strong {111} texture component. A low deposition rate and a high mobility of atoms on the surface, which corresponds to a high substrate temperature, can strengthen {111} texture.
Copper has been recently used as an interconnecting material because of its good electromigration resistance and low electrical resistivity. One of the major problems of copper as an interconnecting material is that it easily oxidizes at relatively low temperatures. The formation of oxide degrades the electrical and mechanical properties of copper interconnects. The influence of substrate texture on the oxidation kinetics was studied to suggest methods to reduce copper oxidation. Copper single crystals having (100), (110), (123), (314), (111) and (311) orientations were oxidized at 200ºC in air. Only the Cu2O phase was formed during oxidation. The oxidation of the (100) single crystal substrate was much faster than that of the others. This is attributed to a large number of fine oxide grains on the (100) crystal in the initial stages of oxidation. It is recommended that the {100} texture in copper interconnects should be avoided in order to reduce oxidation rate. A quantitative model was proposed to predict the oxidation kinetics of copper from the texture of the specimens. Reasonable agreement was obtained comparing the model predictions and the experimental results obtained from the test of oxidation of polycrystalline copper specimens. However, further improvement of the model can be done if more data from single crystal experiments are obtained.
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Srikar, V. T. (Vengallatore Thattai) 1972. "Electromigration behavior and reliability of bamboo Al(Cu) interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/85249.
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Sarvari, Reza. "Impact of size effects and anomalous skin effect on metallic wires as GSI interconnects." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/31636.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Meindl, James D.; Committee Member: Davis, Jeffrey A.; Committee Member: Gaylord, Thomas K.; Committee Member: Hess, Dennis W.; Committee Member: Peterson, Andrew F. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Cho, Taiheui. "Anisotropy of low dielectric constant materials and reliability of Cu/low-k interconnects /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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Lo, George Chih-Yu. "Electroplated Compliant High-Density Interconnects For Next-Generation Microelectronic Packaging." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4778.
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Dramatic advances are taking place in the microelectronic industry. The feature size continues to scale down and it is expected that the minimum feature size on the integrated circuit is expected to reach 9 nm by 2016, and there will be more than 8 billion transistors on a 310 cm² chip, according to various available roadmaps. Subsequently, this reduction in feature size would require the first-level input-output interconnects to decrease in pitch size to meet the increased number of transistors on the chip. Also, to minimize the on-chip interconnect delay, development of low-K dielectric/copper will become increasingly common in future devices. However, due to the low fracture strength of low-K dielectric, it is essential that the first-level interconnects exert minimal force on the die pads and therefore, do not crack or delaminate the low-K dielectric material. It is also preferable to have a wafer-level packaging approach to facilitate test-and-burn in and to produce known-good dies. Based on these growing demands from the microelectronics industry, there is a compelling need to develop innovative interconnect technologies.
This thesis aims to develop one such innovative interconnect — G-Helix interconnect. G-Helix is a scalable lithography-based wafer-level electroplated compliant interconnect that has the potential to meet the fine-pitch first-level chip-to-substrate interconnect requirements. The three-mask fabrication of G-Helix is based on lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be easily integrated into large-area wafer-level fine-pitch batch processing. In this work, the fabrication, assembly, experimental reliability testing, and numerical physics-based modeling of the G-Helix interconnects will be presented.
The fabrication of the interconnects will be demonstrated at 100μm pitch on a 20 x 20 mm die in a class 10/1000 cleanroom facility. The wafers with compliant interconnects will be singulated into individual dies and assembled on substrates using Pb/Sn eutectic solder. The assembly will then be subjected to air-to-air thermal cycling between 0℃and 100℃ and the reliability of the compliant interconnect will be assessed. In addition to the thermo-mechanical reliability testing, some of the dies with free-standing interconnects will also be used for measuring the compliance of the interconnects by compressing with a nanoindenter. In parallel to the experimental research, a numerical analysis study will also be carried out. The numerical model will use direction-, temperature, time-dependent, and time independent material constitutive properties as appropriate. The thermo-mechanical fatigue life of the compliant interconnect assembly will be determined and compared with the experimental data. Recommendations will be developed for further enhancement of reliability and reduction in pitch size.
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Cho, Jaeshin. "Effect of microstructure of aluminum alloys on the electromigration-limited reliability of VLSI interconnects." Thesis, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/13636.
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Joo, Young-Chang. "Electromigration failure and reliability of single-crystal and polycyrstalline aluminum interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11446.
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Rodriguez, Omar. "Thermo-Mechanical Reliability of Micro-Interconnects in Three-Dimensional Integrated Circuits: Modeling and Simulation." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/737.
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Three-dimensional integrated circuits (3D ICs) have been designed with the purpose of achieving higher communication speed by reducing the interconnect length between integrated circuits, and integrating heterogeneous functions into one single package, among other advantages. As a growing, new technology, researchers are still studying the different parameters that impact the overall lifetime of such packages in order to ensure the customer receives reliable end products. This study focused on the effect of four design parameters on the lifetime of the interconnects and, in particular, solder balls and through-silicon vias (TSVs). These parameters included TSV pitch, TSV diameter, underfill stiffness and underfill thickness. A three-dimensional finite element model of a 3D IC package was built in ANSYS to analyze the effect of these parameters under thermo-mechanical cyclic loading. The stresses and damage in the interconnects of the IC were evaluated using Coffin-Manson and the energy partitioning fatigue damage models. A three-level Taguchi design of experiment method was utilized to evaluate the effect of each parameter. Minitab software was used to assess the main effects of the selected design parameters. Locations of maximum stresses and possible damage initiation were discussed, and recommendations were made to the manufacturer for package optimization.
Due to the very small scale of the interconnects, conducting mechanical tests and measuring strains in small microscopic scale material is very complicated and challenging; therefore, it is very difficult to validate finite element and analytical analysis of stress and strain in microelectronic devices. At the next step of this work, a new device and method were proposed to facilitate testing and strain measurements of material at microscopic scale.
This new micro-electromechanical system (MEMS) consisted of two piezoelectric members that were constrained by a rigid frame and that sandwiched the test material. These two piezoelectric members act as load cell and strain measurement sensors. As the voltage is applied to the first member, it induces a force to the specimen and deforms it, which in turn deforms the second piezoelectric member. The second piezoelectric member induces an output voltage that is proportional to its deformation. Therefore, the strain and stresses in the test material can be determined by knowing the mechanical characteristics of the piezoelectric members. Advantages of the proposed system include ease of use, particularly at microscopic scale, adaptability to measure the strain of different materials, and flexibility to measure the modulus of elasticity for an unknown material. An analytical analysis of the device and method was presented, and the finite element simulation of the device was accomplished. The results were compared and discussed. An inelastic specimen was also analyzed and sensitivity of the device to detecting nonlinear behavior was evaluated. A characteristic curve was developed for the specific geometry and piezoelectric material.
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Gupta, Piyush. "Effect of intermetallic compounds on thermomechanical reliability of lead-free solder interconnects for flip-chips." Thesis, Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08202004-125146/unrestricted/gupta%5Fpiyush%5F200412%5Fmaster.pdf.
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Thesis (M.S.)--Materials Science and Engineering, Georgia Institute of Technology, 2005.Suresh, Committee Member ; C.P. Wong, Committee Member ; Rao R. Tummala, Committee Chair. Includes bibliographical references.
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Khan, Sharif [Verfasser]. "Improving the reliability of high density interconnects in hybrid assemblies of active microimplants / Sharif Khan." München : Verlag Dr. Hut, 2018. http://d-nb.info/1168534550/34.
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Zhu, Wenbo. "Soldering interconnects through self-propagating reaction process." Thesis, Loughborough University, 2016. https://dspace.lboro.ac.uk/2134/23259.
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This thesis presents a research into the solder interconnects made through the reactive bonding process based on the self-propagating reaction. A numerical study of soldering conditions in the heat affected zone (HAZ) during bonding was initially carried out in order to understand the self-propagating reactive bonding and the related influencing factors. This was subsequently followed by an extensive experimental work to evaluate the feasibility and reliability of the reactive bonding process to enable the optimisation of processing parameters, which had provided a detailed understanding in terms of interfacial characteristics and bonding strengths. In addition, by focusing on the microstructure of the bonds resulted from the self-propagating reactions, the interfacial reactions and microstructural evolution of the bonded structures and effects of high-temperature aging were studied in details and discussed accordingly. To study the soldering conditions, a 3D time-dependent model is established to describe the temperature and stress field induced during self-propagating reactions. The transient temperature and stress distribution at the critical locations are identified. This thus allows the prediction of the melting status of solder alloys and the stress concentration points (weak points) in the bond under certain soldering conditions, e.g. ambient temperature, pressure, dimension and type of solder materials. Experimentally, the characterisation of interconnects bonded using various materials under different technical conditions is carried out. This ultimately assists the understanding of the feasibility, reliability and failure modes of reactive bonding technique, as well as the criteria and optimisation to form robust joints. The formation of phases such as intermetallic compounds (IMCs) and mechanism of interfacial reactions during reactive bonding and subsequent aging are elaborated. The composition, dimension, distribution of phases have been examined through cross-sectional observations. The underlying temperature and stress profile determining the diffusion, crystallization and growth of phases are defined by numerical predictions. XXI Through the comparative analysis of the experimental and numerical results, the unique phases developed in the self-propagating joints are attributed to the solid-liquid-convective diffusion, directional solidification and non-equilibrium crystallization. The recrystallization and growth of phases during aging are revealed to be resulted from the solid-state diffusion and equilibration induced by the high-temperature heating. In conclusion, the interfacial reactions and microstructural evolution of interconnect developed through self-propagating reactive bonding are studied and correlated with the related influencing factors that has been obtained from these predictions and experiments. The results and findings enable the extensive uses of self-propagating reactive bonding technology for new design and assembly capable of various applications in electronic packaging. It also greatly contributes to the fundamentals of the crystallization and soldering mechanism of materials under the non-equilibrium conditions.
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Xu, Di. "Nanotwin formation by electrodeposition and its influence on the physical properties and reliability of copper interconnects." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=1997610601&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Longworth, Hai Pham. "Microstructural modification of thin films and its relation to the electromigration-limited reliability of VLSI interconnects." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/13114.
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Otieno, Wilkistar. "A Framework for Determining the Reliability of Nanoscale Metallic Oxide Semiconductor (MOS) Devices." Scholar Commons, 2010. http://scholarcommons.usf.edu/etd/3499.
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An increase in worldwide investments during the past several decades has pro-pelled scienti c breakthroughs in nanoscience and technology research to new and exciting levels. To ensure that these discoveries lead to commercially viable prod-ucts, it is important to address some of the fundamental engineering and scientific challenges related to nanodevices. Due to the centrality of reliability to product integrity, nanoreliability requires critical analysis and understanding to ensure long-term sustainability of nanodevices and systems. In this study, we construct a relia-bility framework for nanoscale dielectric lms used in Metallic Oxide Semiconductor (MOS) devices. The successful fabrication and incorporation of metallic oxides in MOS devices was a major milestone in the electronics industry. However, with the progressive scaling of transistors, the dielectric dimension has progressively decreased to about 2nm. This reduction has had severe reliability implications and challenges including: short channeling e ects and leakage currents due to quantum-mechanical tunneling which leads to increased power dissipation and eventually temperature re-lated gate degradation.
We develop a framework to characterize and model reliability of recently devel-oped gate dielectrics of Si-MOS devices. We accomplish this through the following research steps: (i) the identi cation of the failure mechanisms of Si-based high-k gates (stress, material, environmental), (ii) developing a 3-D failure simulation as a way to acquire simulated failure data, (iii) the identi cation of the dielectric failure prob-ability structure using both kernel estimation and nonparametric Bayesian schemes so as to establish the life pro le of high-k gate dielectric. The goal is to eventually develop the appropriate failure extrapolation model to relate the reliability at the test conditions to the reliability at normal use conditions.
This study provides modeling and analytical clarity regarding the inherent failure characteristics and hence the reliability of metal/high-k gate stacks of Si-based sub-strates. In addition, this research will assist manufacturers to optimally characterize, predict and manage the reliability of metal high-k gate substrates. The proposed reliability framework could be extended to other thin lm devices and eventually to other nanomaterials and devices.
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Ginga, Nicholas J. "On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52225.
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The cohesive fracture of thin films is a concern for the reliability of many devices in microelectronics, MEMS, photovoltaics, and other applications. In microelectronic packaging the cohesive fracture toughness has become a concern with new low-k dielectric materials currently being used. To obtain the low-k values needed to meet electrical performance goals, the mechanical strength of the material has decreased. This has resulted in cohesive cracks occurring in the Back End of Line (BEoL) dielectric layers of the microelectronic packages. These cracks lead to electronic failures and occur after thermal loading (due to CTE mismatch of materials) and mechanical loading. To prevent these cohesive cracks, it is necessary to measure the cohesive fracture resistance of these thin films to implement during the design and analysis process. Many of the current tests to measure the cohesive fracture resistance of thin films are based on methods developed for larger scale specimens. These methods can be difficult to apply to thin films due to their size and require mechanical fixturing, physical contact near the crack tip, and complicated stress fields. Therefore, a fixtureless cohesive fracture resistance measurement technique has been developed that utilizes photolithography fabrication processes. This technique uses a superlayer thin film with a high intrinsic stress deposited on top of the desired test material to drive cohesive fracture through the thickness of test material. In addition to developing a technique to measure the fracture resistance of dielectric thin films, the use of carbon nanotube (CNT) forests as off-chip interconnects is investigated as a potential method to mitigate the fracture of these materials. The compressive and tensile modulus of CNT forests is characterized, and it is seen that the modulus is several orders of magnitude less than that of a single straight CNT. The low-modulus CNT forest will help mechanically decouple the chip from the board and reduce stress occurring in the dielectric layers as compared to the current technology of solder ball interconnects and therefore improve reliability. The mechanical performance of these CNT interconnects is investigated by creating a finite-element model of a flip chip electronic package utilizing CNT interconnects and comparing the chip stresses to a traditional solder ball interconnect scenario. Additionally, flip chips are fabricated with CNT forest interconnects, assembled to an FR4 substrate, and subjected to accelerated thermomechanical testing to experimentally investigate their performance.
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Hinshaw, Robert Bruce Lall Pradeep. "Reliability of lead-free and advanced interconnects in fine pitch and high I/O electronics subjected to harsh thermo-mechanical environments." Auburn, Ala, 2009. http://hdl.handle.net/10415/1907.
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Agrawal, Akash. "Board level energy comparison and interconnect reliability modeling under drop impact." Diss., Online access via UMI:, 2009.
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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.Includes bibliographical references.
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Mølmen, Live. "Materials Reliability in PEM Fuel Cells." Licentiate thesis, Jönköping University, JTH, Material och tillverkning, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-52424.
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As part of the global work towards reducing CO2 emissions, all vehicles needs to be electrified, or fueled by green fuels. Batteries have already revolutionised the car market, but fuel cells are believed to be a key energy conversion system to be able to electrify also heavy duty vehicles. The type of fuel cell commercially available for vehicles today is the polymer electrolyte membrane fuel cell (PEMFC), but for it to be able to take a larger market share, the cost must be reduced while sufficient lifetime is ensured. The PEMFC is a system containing several components, made of different materials including the polymer membrane, noble metal catalyst particles, and metallic bipolar plate. The combination of different materials exposed to elevated temperature, high humidity and low pH make the PEMFC components susceptible to corrosion and degradation. The noble metal catalyst is one of the major contributors to the high cost. In this work, the latest research on new catalyst materials for PEMFCs are overviewed. Furthermore, electrodeposition as a simple synthesis route to test different Pt-alloys for the cathode catalyst in the fuel cell is explored by synthesis of PtNi and PtNiMo. The gas diffusion layer of the PEMFC is used as substrate to reduce the number of steps to form the membrane electrode assembly. In addition to cheaper and more durable materials, understanding of how the materials degrade, and how the degradation affects the other components is crucial to ensure a long lifetime. Finding reliable test methods to validate the lifetime of the final system is necessary to make fuel cell a trusted technology for vehicles, with predictable performance. In this work, commercial flow plates are studied, to see the effect of different load cycles and relative humidities on the corrosion of the plate. Defects originating from production is observed, and the effect of these defects on the corrosion is further analysed. Suggestions are given on how the design and production of bipolar plates should be made to reduce the risk of corrosion in the PEMFC.Som en del av det globala arbetet med at reducera utsläppen av koldioxid måste alla fordon elektrifieras eller tankas med förnybart bränsle. Batterier har redan revolutionerat bilmarknaden, men bränsleceller är en viktig pusselbit för att också elektrifiera tunga fordon. Den typen av bränsleceller för fordon som finns tillgänglig på den kommersiella marknaden i dag är polymerelektrolytbränslecellen (PEMFC). För att PEMFC skall ta en större marknadsandel måste kostnaderna minskas och livslängden förlängas. PEMFC består av ett antal komponenter gjorda av olika material, bland annat polymer membran, ädelmetallkatalysator, och metalliska bipolära plattor. Kombinationen av olika material i tillägg till den höga temperaturen, hög fuktighet och låg pH gör att materialen i bränslecellen är utsatta för korrosion. Ädelmetallkatalysatorn är en av de kostdrivande komponenterna i bränslecellen. I denna studien presenteras en översikt över framstegen inom katalysatormaterial för PEM bränsleceller de senaste två åren. Sedan studeras elektroplätering som en enkel produktionsmetod för nanopartiklar av platina legeringar. Möjligheten att simultant plätera fler metaller, och att använda gasdiffutions-skiktet från bränslecellen som substrat för att reducera antal produktionsteg och därmed reducera kostnader, undersöks. Det möjliggör också snabb testning av olika legeringar för att identifiera den optimala sammansättningen med hög prestanda, lång livslängd och lite platina. I tillägg till att ta fram billigare och tåliga material är det viktigt att förstå hur materialen degraderar och hur degraderingen av ett material påverkar de andra komponenterna. Med den kunskapen kan man utveckla accelererade testmetoder för att bedöma livslängden av hela bränslecellen. Validerade testmetoder är viktigt för att styrka förtroendet till nya teknologier. I denna studien fokuseras det också på korrosion av bipolära plattor, och hur olika lastcykler och fuktnivåer som kan bli applicerad vid accelererad testning påverkar korrosionen. Också effekten av defekter från tillverkningen i den skyddande beläggningen analyseras med hänsyn till korrosion, för att ge mer insikt i hur bipolära plattor kan designas och produceras för att minska korrosionen.
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Lin, Ta-Hsuan. "Assembly process development, reliability and numerical assessment of copper column flexible flip chip technology." Diss., Online access via UMI:, 2008.
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Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.Includes bibliographical references.
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Zhang, Rongwei. "Novel conductive adhesives for electronic packaging applications: a way towards economical, highly conductive, low temperature and flexible interconnects." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39548.
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Isotropically conductive adhesives (ICAs) are promising as a lead-free interconnect material; However, ICAs have a higher resistivity compared to tin/lead solder. The higher resistivity of ICAs results from the large contact resistance between conductive fillers. Several novel approaches to engineer the interface between electrically conductive fillers were studied to develop highly conductive ICAs. Shown in this dissertation are three methodologies to reduce contact resistance: low temperature sintering, fast sintering and in-situ reduction. Furthermore, two approaches, surface modification and in-situ protection, were developed to prevent oxidation and corrosion of silver-coated copper flakes to produce low cost ICAs. The findings and insights in this dissertation significantly contribute to (1) understanding of filler-filler, filler-polymer and structure-property relationships of ICAs; (2) the structural design and formulation of high performance ICAs; and (3) the wider use of ICAs in emerging applications such as printed electronics and solar cells.
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Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.
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Hu, Xiao. "Multiscale Simulation of Metallic Copper and Copper Oxide Atomic Layer Deposition from Cu Beta-diketonates." Universitätsverlag der Technischen Universität Chemnitz, 2016. https://monarch.qucosa.de/id/qucosa%3A21539.
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Copper (Cu) interconnects have been widely used to replace aluminum in ultra-large-scale integration due to low resistivity and superior resistance to electromigration. Current processes for the fabrication of interconnects require thin Cu seed layers before the subsequent Cu filling by electrochemical deposition (ECD). It is crucial that these seed layers are coated conformally and smoothly in vias and trenches, ensuring that the ECD Cu films are free of voids. With the continuous scaling down of device dimensions, atomic layer deposition (ALD) has been considered as the most promising technology for making the Cu seed layers, because of its excellent conformality and precise thickness control. This dissertation is dedicated to the multiscale simulation of Cu ALD using the Cu beta-diketonate precursors (nBu3P)2Cu(acac) and Cu(acac)2. Different co-reactants (H, H2, H2O, O3 and wet O2) were investigated with respect to their application for the ALD of metallic Cu and Cu oxides. While Cu beta-diketonates have been widely applied in ALD, the mechanistic details of the surface reactions are still largely unknown. Ab initio calculations were performed to obtain the input data for reactive molecular dynamics (RMD) simulations and thermodynamic modeling, which were realized at the molecular-scale and macroscale, respectively.Kupferleitbahnen werden in höchstintegrierten Schaltkreisen aufgrund des niedrigen spezifischen Widerstands und der sehr guten Beständigkeit gegen Elektromigration verwenden. Aktuelle Verfahren zur Leitbahnherstellung erfordern dünne Cu Keimschichten vor der anschließenden Cu Füllung durch die elektrochemische Abscheidung (ECD). Dabei ist es entscheidend, dass diese Keimschichten konform und glatt in den Vias und Gräben abgeschieden werden können, so dass die ECD Cu-Filme frei von Hohlräumen sind. Mit der weiteren Skalierung wird die Atomlagenabscheidung (ALD) mit ihrer hohen Konformalität und der ausgezeichneten Dickensteuerung als die vielversprechendste Technik zur Herstellung der Cu Keimschichten betrachtet. Die vorliegende Dissertation ist der Multiskalensimulation der ALD von metallischem Kupfer und Kupferoxiden aus Cu-beta-Diketonat Präkursoren (nBu3P)2Cu(acac) und Cu(acac)2 gewidmet. Verschiedene Koreaktanden H, H2, H2O, O3 und feuchtes O2 werden hinsichtlich ihrer Anwendung für die ALD von metallischem Kupfer oder Kupferoxid untersucht. Die Mechanismen der Oberflächenreaktionen dieser Präkursoren sind noch weitgehend unbekannt, obwohl die Cu Beta-Diketonate in der ALD bereits breite Verwendung finden. Ab-initio-Rechnungen wurden durchgeführt, um die Eingangsdaten für die reaktive Molekulardynamiksimulation und die thermodynamische Modellierung zu erhalten, die sowohl auf molekularer wie auch auf makroskopischer Ebene durchgeführt wurden.
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Bana, Franck Lionel. "Dégradation par électromigration dans les interconnexions en cuivre : étude des facteurs d'amélioration des durées de vie et analyse des défaillances précoces." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENI081/document.
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Les circuits intégrés sont partie prenante de tous les secteurs industriels et de la vie couranteactuels. Leurs dimensions sont sans cesse réduites afin d’accroître leurs performances. Cetteminiaturisation s’accompagne notamment d’une densification et d’une complexification du réseaud’interconnexions. Les interconnexions, lignes métalliques chargées de transporter le signalélectrique dans les circuits apparaissent ainsi plus sensibles à la dégradation par électromigration.Ceci, compte tenu des fortes densités de courant qu’elles transportent. Il se trouve donc dans lesnoeuds technologiques avancés, de plus en plus difficile de garantir le niveau de fiabilité requis pourles interconnexions.La réduction de la durée de vie des interconnexions est liée à la fois à la difficulté croissanteà réaliser les étapes de procédés pour les géométries souhaitées et à l’augmentation de la dispersiondes temps à la défaillance. Dans un premier temps, nous avons poussé la compréhension desmécanismes en jeu lors de la dégradation par électromigration. Nous avons ainsi mis en évidence lerôle joué par la microstructure et la composition chimique des lignes de cuivre dans l’augmentationde leur durée de vie. Dans un second volet, l’accent a été porté sur l’amélioration de l’analysestatistique des durées de vie avec un focus sur les défaillances précoces et les distributionsbimodales qu’elles engendrent. De même, la structure multi liens que nous avons mise au pointpermet de répondre à la question fondamentale de l’augmentation de l’échantillonnage de test ;améliorant ainsi la précision aux faibles taux de défaillance pour des projections robustes des duréesde vieIntegrated circuits are part of our nowadays life as they are presents everywhere; as well as in daily life or industry. They are continuously downscaled to increase their performances. As a result, this downscaling lead to complex interconnects grid architectures. Interconnects which are metal lines carrying electric signal in the circuit are thus more and more sensitive to electromigration failure. This I because of increasingly higher current densities they carry. Obviously, in advanced technology nodes, it is more and more difficult to ensure the reliability level required for interconnects. Interconnects lifetime reduction is linked to increasing difficulty to perform all process steps with these very small features and also to increasing failure times dispersion. In the first part of the work presented here, we deepened the understanding of mechanisms involved during electromigration degradation. We have thus shown the fundamental role played by the microstructure and the chemical composition of the line in increasing its lifetime. The second part of the work dealt with the improvement of statistical analysis of failure times. We thus focused on early failures and the bimodal failure times distributions they generate. As far as that goes, the multilink structure we have designed answers the fundamental question of increase test sampling. This lead then to improved precision at very low failure rates for robust lifetime's extrapolation to use conditions
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Choudhury, Abhishek. "Chip-last embedded low temperature interconnections with chip-first dimensions." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37104.
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Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection.
This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.
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Schulz, Stefan E. "AMC 2015 – Advanced Metallization Conference." Universitätsverlag der Technischen Universität Chemnitz, 2016. https://monarch.qucosa.de/id/qucosa%3A20503.
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Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry.
Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of:
- Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials)
- Highly-scaled local and global interconnects
- Beyond Cu interconnect
- Novel metallization schemes and advanced dielectrics
- Interconnect and device reliability
- Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM)
- 3D and packaging (monolithic 3D, TSV, EMI)
- Novel and emerging interconnects
Executive Committee:
Sang Hoon Ahn (Samsung Electronics Co., Ltd.)
Paul R. Besser (Lam Research)
Robert S. Blewer (Blewer Scientific Consultants, LLC)
Daniel Edelstein (IBM)
John Ekerdt (The University of Texas at Austin)
Greg Herdt (Micron)
Chris Hobbs (Sematech)
Francesca Iacopi (Griffith University)
Chia-Hong Jan (Intel Corporation)
Rajiv Joshi (IBM)
Heinrich Koerner (Infineon Technologies)
Mehul Naik (Applied Materials Inc.)
Fabrice Nemouchi (CEA LETI MINATEC)
Takayuki Ohba (Tokyo Institute of Technology)
Noel Russell (TEL Technology Center, America)
Stefan E. Schulz (Chemnitz University of Technology)
Yosi Shacham-Diamand (Tel-Aviv University)
Roey Shaviv (Applied Materials Inc.)
Zsolt Tokei (IMEC)
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Al, Choueyri Yousef, and Mojtaba Fayazi. "Digital models of manufacturing : with emphasis on titanium welding for early product development." Thesis, Blekinge Tekniska Högskola, Institutionen för maskinteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18317.
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This thesis work is part of the BTH research lab, focusing on developing the early product development, by analyzing how to integrate the manufacturing process with the early design process. A known problem in the manufacturing industry is the knowledge gap between the designers and the manufacturing process. Where in the early stages of the product development a knowledge regarding the manufacture process is needed. This is in many cases ignored by the designers because it is commonly thought that the responsibility of selecting the manufacturing processes for a product falls upon the manufacturers, despite the fact that the manufacturing processes in reality is highly dependent upon the design choses such as materials, size, shape, finishing and tolerances of the product. To mitigate this problem a variations of product ‘team’ approaches have been used where the idea is to involve a multitude of people with the necessary experience to produce a ‘production friendly product’. Those approaches have a few drawbacks mainly the problem of finding people with the relevant experiences or that the expertise only covers the manufacturing processes already used in the organization, losing the opportunity to benefit from any alternative manufacturing process. This thesis focuses on how the welding manufacturing technic, analysis can be integrated into the design process with the help of a digital model? To improve the communications between the manufacturers and designers, two excel files were developed. The first excel file aimed at the manufacturers where they can present the specific machines used in the workshop. Focusing on specific machine and workshops instead of on the general welding method will give the designers a better understanding of the feasibility of producing their design in a specific workshop instead of focusing on a specific manufacturing method. The second excel file is aimed at calculating and comparing the weld methods where the cost and requirements are derived for general welding methods and compared with the machine specifications gathered from the manufacturers using the first excel file. To assess the excel files, a parametrized CAD model of the rear engine turbine structure was developed, and three different cases were used to evaluate the developed excel files. The values used are presented in Appendix A: Table 11–15, and were gathered from public sources. Values were also approximated using regression analysis.Avhandlingen är en del av BTH research lab och fokuserar på det tidiga produktutvecklingsstadiet. Närmare kontrolleras hur produkttillverkningsprocessen kan integreras in i det tidiga produktutvecklingsstadiet. Ett känt problem för detta område är skillnaden på kunskapen som designer och tillverkaren besitter under det tidiga produktutvecklingsstadiet, då kunskapen om tillverkningsprocessen inte existerar. Vanligtvis tar inte produktutvecklare hänsyn till detta, eftersom ansvaret för valet av tillverkningsprocessen bedöms falla på tillverkaren. Trots att tillverkningsprocessen beror på många aspekter som bestäms under designprocessen som till exempel materialval, geometrin, efterbehandlingar och toleranser på produkten. För att minimera problemet involverar industrin en stor variation av människor med kompetens och erfarenhet, som sedan kan tillverka en produkt rätt anpassad för tillverkningsprocessen. Dock har denna lösning några nackdelar, då det kan vara svårt att hitta människor med rätt erfarenhet, men då man fokuserar på ett tillverkningssätt så kan företaget gå miste om fördelarna med alternativa tillverkningsprocesser. Denna avhandling fokuserar på hur analysen av svetstillverkningstekniken kan integreras in i designprocessen med hjälp av en digital modell. För att förbättra kommunikationen mellan tillverkare och designer har 2 Excel filer utvecklats. Den första Excel filen är riktat mot tillverkarna där dem kan nämna maskinerna som finns tillgängliga i deras verkstad. Den andra Excel filen är till för att kunna göra en kostnadskalkyl och jämföra dem olika tillverkningsmetoderna med hjälp av maskinspecifikationerna som fanns presenterade i den första Excel filen. För att utvärdera Excel filerna, har en parametrisk CAD modell skapats och 3 fall har använts för att testa de utvecklade CAD modellera. Värdena som använts i detta examensarbete finns i Appendix A: Table 11–15 och är hämtade från allmänt tillgängliga källor. Värden uppskattades också med hjälp av regressionsanalyser.
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Verriere, Virginie. "Analyse électrique de diélectriques SiOCH poreux pour évaluer la fiabilité des interconnexions avancées." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00593515.
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Avec la miniaturisation des circuits intégrés, le délai de transmission dû aux interconnexions a fortement augmenté. Pour limiter cet effet parasite, le SiO2 intégré en tant qu'isolant entre les lignes métalliques a été remplacé par des matériaux diélectriques à plus faible permittivité diélectrique dits Low-κ. La principale approche pour élaborer ces matériaux est de diminuer la densité en incorporant de la porosité dans des matériaux à base de SiOCH. L'introduction de ces matériaux peu denses a cependant diminué la fiabilité : sous tension, le diélectrique SiOCH poreux est traversé par des courants de fuite et peut claquer, générant des défaillances dans le circuit. La problématique pour l'industriel est de comprendre les mécanismes de dégradation du diélectrique Low-κ afin de déterminer sa durée de vie aux conditions de température et de tension de fonctionnement. Dans ce contexte, les travaux de cette thèse ont consisté à étudier les mécanismes de conduction liés aux courant de fuite afin d'extraire des paramètres quantitatifs représentatifs de l'intégrité électrique du matériau. Nous avons utilisé ces paramètres afin de suivre le vieillissement du matériau soumis à une contrainte électrique. Nous avons également introduit la spectroscopie d'impédance à basse fréquence comme moyen de caractérisation du diélectrique Low-κ. Cet outil nous a permis de caractériser le diélectrique intermétallique de façon non agressive et d'identifier des phénomènes de transport de charges et de diffusion métallique à très basses tensions qui offrent des perspectives pour l'étude de la fiabilité diélectrique des interconnexions.
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Taibi, Mohamed. "Intégration 3D haute densité : comportement et fiabilité électrique d'interconnexions métalliques réalisées par collage direct." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00721981.
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Depuis plus de 50 ans, l'industrie de la microélectronique ne cesse d'évoluer afin de répondre à la demande d'augmentation des performances ainsi que des fonctionnalités des composants, tout en diminuant les tailles et les prix des produits. Cela est obtenu à ce jour principalement par la réduction des dimensions des composants électroniques. Cependant les dimensions actuelles des transistors atteignent une limitation physique et de nombreux effets parasites émergent. Il devient évident que dans un avenir très proche cet axe de développement ne sera plus envisageable. L'intégration tridimensionnelle apparaît alors comme une solution très prometteuse face à cette problématique de miniaturisation. Cette architecture permet la réalisation de composants plus performants tout en augmentant les fonctionnalités de ces derniers. Son concept consiste à empiler différents circuits de natures éventuellement différentes puis de les interconnecter électriquement à l'aide de connexions verticales. Le collage direct métallique permet en ce sens d'assembler mécaniquement et électriquement deux circuits l'un sur l'autre. Le but de ce travail de thèse est d'étudier le comportement électrique du procédé de collage direct métallique avant de l'intégrer dans un composant actif. On retrouve dans la première partie de ces travaux, la description du jeu de masque ainsi que les intégrations technologiques utilisées, pour réaliser les démonstrateurs 3D permettant les différentes caractérisations électriques de ces interconnexions métalliques. L'évolution de la résistance spécifique de l'interface de collage a été investiguée en fonction de la température de recuit. Puis, la fiabilité électrique de ces interconnexions a été étudiée en analysant leurs comportements face aux risques de dégradation induits par électromigration ou sous contrainte thermique. Des études physico-chimiques ont permis d'analyser les défaillances et de proposer des mécanismes. Pour finir, dans une dernière partie, les étapes technologiques nécessaires à une intégration 3D haute densité type puce à plaque ont été développées et caractérisées.
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Chery, Emmanuel. "Fiabilité des diélectriques low-k SiOCH poreux dans les interconnexions CMOS avancées." Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-01063862.
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Avec la miniaturisation continue des circuits intégrés et le remplacement de l'oxyde de silicium par des diélectriques low-k poreux à base de SiOCH, la fiabilité des circuits microélectroniques a été fortement compromise. Il est aujourd'hui extrêmement important de mieux appréhender les mécanismes de dégradation au sein de ces matériaux afin de réaliser une estimation précise de leur durée de vie. Dans ce contexte, ces travaux de thèse ont consisté à étudier les mécanismes de dégradation au sein du diélectrique afin de proposer un modèle de durée de vie plus pertinent. Par une étude statistique du temps à la défaillance sous différents types de stress électrique, un mécanisme de génération des défauts par impact est mis en évidence. En l'associant au mécanisme de conduction au sein du diélectrique, il a été possible de développer un modèle de durée de vie cohérent pour les interconnexions permettant une estimation de la durée de vie plus fiable que les modèles de la littérature. L'impact du piégeage de charges dans le diélectrique a ensuite été analysé grâce à ce modèle.
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Karlsson, Hampus, and Anton Karlsson. "Konceptutveckling av en caterpillar med inriktning på kvalitet : En utvecklingsprocess." Thesis, Blekinge Tekniska Högskola, Institutionen för maskinteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14996.
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When transporting a sea cable, what is commonly called a caterpillar is used, but the most common said is a cable tensioner. These machines can be found in a flurry of different variants, where there are a multitude of competitors, which applies demands to having an extremely distinctive machine. Therefore from a market analysis it have been identified that a lack of quality regarding the machines are a factor. A poor quality shortage that usually occurs in hard weather conditions, but this is something that should not happen as it may lead to machine breakdown. Semcon AB in Karlskrona constructs and then collaborates with Ronneby Svets & Smide, who manufacture cable carousels, armrests and other equipment for the cable industry but not the cable tensioner that are ordered separately by external companies. This is the background to why the project is created because Semcon sees a need to eliminate this bottleneck and also expand their product portfolio for customer recovery. The aim it therefore, together with Semcon, develop a new concept for a completely new cable tensioner with given preferences, rough drawing and selection of qualitative features for the machine in order to be competitive with its future overall solution for the cable industry. To find a solution to the described problem, a product development process has been followed to establish structure. The process include a planning, concept development, design and detailed development phase. From the first phase, a wide understanding of how the complex machine works and where its deficiencies may be. Even hidden customer needs in form of interviews with cable manufacturers in Karlskrona and with industries that handle sea cable were conducted to get a broader spectrum. The needs are transformed into specifications to generate concepts based on the rankings of the measurably formulated specifications. Followed up by an evaluation where the best concepts were taken to the design phase and detailed development. All design calculations have been made, either by hand or with computer-based programs. The work has resulted in an innovative concept of a whole cable tensioner with all key components, rough drawing, together with a new thinking solution regarding the contact face between the cable and the machine, developed through experiments and theory studies. As this project is very broad, the overall project has been divided into two master thesis works and all electronics are handles by an electrical/automation company. Therefore, for a broader understanding and information about functionality, reference is made to the second project “Konceptutveckling kring funktionerna hos en kabeldragare” authored by Anton Hansson. It is extremely important to mention that the outcome of this project is intended to be a concept for a new innovative cable tensioner. This means that with future work on the concept, which includes continued depth of calculation and further contact with suppliers, can provide an opportunity to manufacture the generated concept. Another development area Semcon must proceed with is to review the safety routines of the machine. The authors of this report believe that a highly competitive solution has been presented, and that work contributes to a strong foundation for the development of transporting sea cable technology in the future with the help of this innovative concept.
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Le, Druillennec Marie. "Etude des mécanismes d'endommagement de films minces métalliques déposés sur substrats souples pour l'électronique flexible." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAI108/document.
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Depuis une vingtaine d'années, des composants électroniques flexibles sont développés. Ces composants étant amenés à se tordre, à s'étirer et à se fléchir au cours de leur utilisation, le développement de composants ayant une bonne fiabilité mécanique est primordial. Ce travail s'est concentré sur les films métalliques d'argent déposés par impression jet d'encre ou sérigraphie sur des substrats de polyimide, servant à l’interconnexion électrique entre composants actifs. Deux mécanismes d’endommagement sont observables dans ces systèmes : la fissuration et le flambement par délaminage.Premièrement, pour caractériser expérimentalement ces deux phénomènes, des tests de traction sont réalisés sous microscope optique, afin de suivre l'évolution des fissures au cours de la déformation et sous interféromètre optique, afin de suivre les cloques de délaminage. Une analyse d'images est réalisée afin d'obtenir l'évolution de l'espacement entre fissures au cours de la déformation. L'existence de deux régimes de fissuration est observée : la fissuration longue et droite pour les films épais et la fissuration courte et en forme de zigzag pour les films minces. Le suivi des profils de cloques permet d'obtenir l'évolution de leur forme au cours de la déformation.Ensuite, afin d'éclairer les observations expérimentales, les phénomènes à l'étude sont modélisés par élément finis. Ainsi l'origine des deux régimes de fissuration est expliquée par un effet géométrique de l'épaisseur du film. Un modèle élastoplastique bidimensionnel de relaxation de contraintes dans le film permet d'obtenir un encadrement de l'espacement entre fissures au cours de la déformation. À partir du suivi des cloques, un modèle tridimensionnel permet de réaliser une identification des paramètres de la zone cohésive à l'interface film/substrat, où une énergie d'adhésion de 2 J.m-2, une contrainte critique de 20 MPa et un paramètre de mixité modale de 0,4 sont déterminés. Ces valeurs sont en accord avec la littératureOver the past 20 years, new improvements in materials and processes led to the development of printed flexible electronics. Flexible electronics devices subjected to bending, twisting, or stretching during their lifetime, the development of device with high reliability is therefore of great importance for the efficiency of electrical connection. This work investigates the mechanical reliability of inkjet or screen-printed Ag thin films on polyimide substrates dedicated to the electrical interconnection of active components. Expected mechanical failure modes are film cracking and buckling delamination.First of all, in order to characterized the two mechanisms, tensile tests are performed under an optical microscope to follow cracks and under an optical interferometer to follow buckles. In order to obtain crack spacing evolution during deformation, an image processing is realized. Two types of cracks are observed: long and straight cracking for thick films and small and zigzag shape cracking for thin films. The evolution of buckles shape with imposed tensile deformation is characterized.In a second time, in order to understand experimental observations, mechanical failure modes are analysed with finite elements models. The origin of the two types of cracking are explained by a geometrical effect of film thickness. A elastoplastic shear lag bidimensional model gives upper and lower bonds of crack spacing during deformation. A three-dimensional model allows identification of cohesive zone model parameters at film/substrate interface, from experimental buckle shape. An adhesion energy of 2 J.m-2 , a critical strength of 20 MPa and a mode mixity parameter of 0.4 are determined. These values are in good agreement with literature
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Sellier, Alain. "Modélisations probabilistes du comportement de matériaux et de structures en génie civil." Cachan, Ecole normale supérieure, 1995. http://www.theses.fr/1995DENS0012.
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Des méthodes de calcul basées sur la théorie des probabilités sont développées. Elles permettent d'étudier la sécurité de structures métalliques à assemblages semi-rigides et la sécurité de structures en béton arme. Ces méthodes sont également intéressantes pour la modélisation de matériaux hétérogènes. Elles permettent alors de développer une loi de comportement du béton intégrant des phénomènes aussi divers que la localisation des déformations, les effets d'échelle ou les mécanismes physico-chimiques de la réaction alcali-granulats
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"Series Resistance Increase in Field Degraded PV Modules in Different Climatic Conditions." Master's thesis, 2018. http://hdl.handle.net/2286/R.I.51795.
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abstract: Global photovoltaic (PV) module installation in 2018 is estimated to exceed 100 GW, and crystalline Si (c-Si) solar cell-based modules have a share more than 90% of the global PV market. To reduce the social cost of PV electricity, further developments in reliability of solar panels are expected. These will lead to realize longer module lifetime and reduced levelized cost of energy. As many as 86 failure modes are observed in PV modules [1] and series resistance increase is one of the major durability issues of all. Series resistance constitutes emitter sheet resistance, metal-semiconductor contact resistance, and resistance across the metal-solder ribbon. Solder bond degradation at the cell interconnect is one of the primary causes for increase in series resistance, which is also considered to be an invisible defect [1]. Combination of intermetallic compounds (IMC) formation during soldering and their growth due to solid state diffusion over its lifetime result in formation of weak interfaces between the solar cell and the interconnect. Thermal cycling under regular operating conditions induce thermo-mechanical fatigue over these weak interfaces resulting in contact reduction or loss. Contact reduction or loss leads to increase in series resistance which further manifests into power and fill factor loss. The degree of intermixing of metallic interfaces and contact loss depends on climatic conditions as temperature and humidity (moisture ingression into the PV module laminate) play a vital role in reaction kinetics of these layers. Modules from Arizona and Florida served as a good sample set to analyze the effects of hot and humid climatic conditions respectively. The results obtained in the current thesis quantifies the thickness of IMC formation from SEM-EDS profiles, where similar modules obtained from different climatic conditions were compared. The results indicate the thickness of the IMC and detachment degree to be growing with age and operating temperatures of the module. This can be seen in CuxSny IMC which is thicker in the case of Arizona module. The results obtained from FL
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aged modules also show that humidity accelerates the formation of IMC as they showed thicker AgxSny layer and weak interconnect-contact interfaces as compared to Arizona modules. It is also shown that climatic conditions have different effects on rate at which CuxSny and AgxSny intermetallic compounds are formed.Dissertation/Thesis
Masters Thesis Materials Science and Engineering 2018
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"Electromigration in Gold Interconnects." Doctoral diss., 2013. http://hdl.handle.net/2286/R.I.20914.
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abstract: Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.Dissertation/Thesis
Ph.D. Materials Science and Engineering 2013
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Wei, F., S. P. Hau-Riege, C. L. Gan, Carl V. Thompson, J. J. Clement, H. L. Tay, B. Yu, M. K. Radhakrishnan, Kin Leong Pey, and Wee Kiong Choi. "Length Effects on the Reliability of Dual-Damascene Cu Interconnects." 2002. http://hdl.handle.net/1721.1/3977.
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The effects of interconnect length on the reliability of dual-damascene Cu metallization have been investigated. As in Al-based interconnects, the lifetimes of Cu lines increase with decreasing length. However, unlike Al-based interconnects, no critical length exists, below which all Cu lines are âimmortal’. Furthermore, we found multi-modal failure statistics for long lines, suggesting multiple failure mechanisms. Some long Cu interconnect segments have very large lifetimes, whereas in Al segments, lifetimes decrease continuously with increasing line length. It is postulated that the large lifetimes observed in long Cu lines result from liner rupture at the bottom of the vias, which allows continuous flow of Cu between the two bond pads. As a consequence, the average lifetimes of short lines and long lines can be higher than those of lines with intermediate lengths.Singapore-MIT Alliance (SMA)
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Baek, Won-chong. "Reliability study on the via of dual damascene Cu interconnects." Thesis, 2006. http://hdl.handle.net/2152/2656.
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Lin, Fong-Jie, and 林豐傑. "Electromigration Behavior and Electrical Reliability of Copper Interconnects in Integrated Circuits." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/01525676773955483304.
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碩士國立中興大學
材料科學與工程學系所
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Electromigration tests of dual-damascene Cu interconnect structures with or without an NH3/He plasma treatment between Cu and SiCN etch stop layer have been performed in this study at 400゜C under a current density of 8 MA/cm2 to investigate the influence of interface structures to electrical reliability. From the electrical resistance-to-time traces, it was observed that the electrical resistance of the interconnects with the plasma treatment increased slowly. From the cumulative failure probabilities of 1.1 R0, 1.3 R0, 1.5 R0 (R0: initial resistance), and wire opening, it was found that the interconnects with the plasma treatment exhibited a higher median time to failure, and the electrical reliability of the interconnects was effectively enhanced by the plasma treatment. An oxide layer existed at the Cu/SiCN interface without the plasma treatment, whereas it was removed by the plasma treatment, and Cu-N or Cu-Si bonds formed, consequently enhancing the adhesion of interface. From the observations of EM-induced voiding behaviors in the interconnects, it was found that voids nucleated at the Cu/SiCN interface without the plasma treatment and then grew gradually with testing intervals. In comparison, voids nucleated inside the Cu wires, rather than at the interface, after the plasma treatment, indicating that the NH3/He plasma treatment strengthened the adhesion of the interface and then inhibited the electromigration behavior which occurred at the interface.
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Thompson, Carl V. "Processing, Structure, Properties, and Reliability of Metals for Microsystems." 2002. http://hdl.handle.net/1721.1/3984.
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Research on the processing, structure, properties and reliability of metal films and metallic microdevice elements is reviewed. Recent research has demonstrated that inelastic deformation mechanisms of metallic films and microelements are a function of temperature, encapsulation, and dimension. Reduced dimension can lead to strengthening or softening, depending on the temperature and strain rate. These results will help in the analysis and prediction of the stress state of films and microelements as a function of their thermal history. Experimental characterization and modeling of stress evolution during film formation has also been undertaken. New microelectromechanical devices have been developed for in situ measurements of stress during processing, and experiments relating stress and structure evolution are underway for electrodeposition and reactive film formation as well as vapor deposition. Experiments relating current-induced stress evolution (electromigration) to the reliability of Cu based interconnects are also being carried out.Singapore-MIT Alliance (SMA)
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Pyun, Jung Woo 1970. "Scaling and process effect on electromigration reliability for Cu/low k interconnects." Thesis, 2007. http://hdl.handle.net/2152/3146.
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The microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.text
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Lu, Kuan Hsun. "Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs)." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2096.
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This dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived.
In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc.
Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem.
In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays.text
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Zhang, Lijuan 1979. "Effects of scaling and grain structure on electromigration reliability of Cu interconnects." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2136.
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Electromigration (EM) remains a major reliability concern for on-chip Cu interconnects due to the continuing scaling and the introduction of new materials and processes. In Cu interconnects, the atomic diffusion along the Cu/SiCN cap interface dominates the mass transport and thus controls EM reliability. The EM lifetime degrades by half for each new generation due to the scaling of the critical void volume which induces the EM failure. To improve the EM performance, a metal cap such as CoWP was applied to the Cu surface to suppress the interfacial diffusion. By this approach, two orders of magnitude improvement in the EM lifetime was demonstrated. For Cu lines narrower than 90 nm, the Cu grain structure degraded from bamboo-like grains to polycrystalline grains due to the insufficient grain growth in the trench. Such a change in Cu grain structures can increase the mass transport through grain boundaries and thus degrade the EM performance. The objective of this study is to investigate the scaling effect on EM lifetime and Cu microstructure, and more importantly, the grain structure effect on EM behaviors of Cu interconnects with the CoWP cap compared to those with the SiCN cap only.
This thesis is organized into three parts. In the first part, the effect of via scaling on EM reliability was studied by examining two types of specially designed test structures. The EM lifetime degraded with the via size scaling because the critical void size that causes the EM failure is the same with the via size. The line scaling effect on Cu grain structures were identified by examining Cu lines down to 60 nm in width using both plan-view and cross-sectional view transmission electron microscopy.
In the second part, the effect of grain structure was investigated by examining the EM lifetime, statistics and failure modes for Cu interconnects with different caps. A more significant effect of the grain structure on EM characteristics was observed for the CoWP cap compared to the SiCN cap. For the CoWP cap, the grain structure not only affected the mass transport rate along the Cu line, but also impacted the flux divergence site distribution which determined the voiding location and the lifetime statistics.
Finally, the effect of grain structure on EM characteristics of CoWP capped Cu interconnects was examined using a microstructure-based statistical model. In this model, the microstructure of Cu interconnects was simplified as cluster and bamboo grains connected in series. Based on the weakest-link approximation, it was shown that the EM lifetime and statistics could be adequately modeled by combining the measured cluster length distribution with the EM lifetime-cluster length correlation for each individual failure unit.text
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Chia-LinHsu and 許嘉麟. "Defect and Reliability Studies of Chemical Mechanical Polish Applications in Advanced Interconnects." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/52264892923920589088.
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Chang, Choon Wai, Z. S. Choi, Carl V. Thompson, C. L. Gan, Kin Leong Pey, Wee Kiong Choi, and N. Hwang. "The Influence of Adjacent Segment on the Reliability of Cu Dual Damascene Interconnects." 2005. http://hdl.handle.net/1721.1/7533.
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Three terminal âdotted-I’ interconnect structures, with vias at both ends and an additional via in the middle, were tested under various test conditions. Mortalities (failures) were found in right segments with jL value as low as 1250 A/cm, and the mortality of a dotted-I segment is dependent on the direction and magnitude of the current in the adjacent segment. Some mortalities were also found in the right segments under a test condition where no failure was expected. Cu extrusion along the delaminated Cu/Si₃N₄ interface near the central via region was believed to cause the unexpected failures. From the time-to-failure (TTF), it is possible to quantify the Cu/Si₃N₄ interfacial strength and bonding energy. Hence, the demonstrated test methodology can be used to investigate the integrity of the Cu dual damascene processes. As conventionally determined critical jL values in two-terminal via-terminated lines cannot be directly applied to interconnects with branched segments, this also serves as a good methodology to identify the critical effective jL values for immortality.Singapore-MIT Alliance (SMA)