Relevant bibliographies by topics / Reliability of metallic interconnects

Academic literature on the topic 'Reliability of metallic interconnects'

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Published: 10 December 2022
Last updated: 29 January 2023

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Journal articles on the topic "Reliability of metallic interconnects"

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Zhao, Wen-Sheng, Kai Fu, Da-Wei Wang, Meng Li, Gaofeng Wang, and Wen-Yan Yin. "Mini-Review: Modeling and Performance Analysis of Nanocarbon Interconnects." Applied Sciences 9, no. 11 (May 28, 2019): 2174. http://dx.doi.org/10.3390/app9112174.

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As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic interconnects face several serious challenges in aspects of performance and reliability. To address these issues, nanocarbon materials, including carbon nanotube (CNT) and graphene, have been proposed as promising candidates for interconnect applications. Considering the rapid development of nanocarbon interconnects, this paper is dedicated to providing a mini-review on our previous work and on related research in this field.
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Kuruvilla, Nisha, J. P. Raina, Arun Greig John, and A. Athulya. "Performance and Reliability Analysis of Bundled SWCNT as IC Interconnects." Advanced Materials Research 129-131 (August 2010): 920–25. http://dx.doi.org/10.4028/www.scientific.net/amr.129-131.920.

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This work has investigated the performance of Single-walled carbon nanotube bundle as futuristic interconnect material under process constraints and compared its suitability as IC interconnect material as per ITRS predictions. It also analyzes variance of each parasitic effect along with the variations in process parameters. This paper pinpoints the variables causing bottlenecks in realizing optimum performance and improving reliability. It also evaluates the effect of diameter variations of CNTs in an SWCNT bundle and metallic tube ratio on the performance and reliability for 22nm technological node. The results demonstrate that the relative variations in the resistance are critically effected by the variations in metallic tube ratios rather than diameter variations. The diameter variation introduces its critical effect only at global level.
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Katkar, Rajesh, Michael Huynh, and Laura Mirkarimi. "Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 002404–23. http://dx.doi.org/10.4071/2011dpc-tha33.

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Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.
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Gelatos, A. V., A. Jain, R. Marsh, and C. J. Mogab. "Chemical Vapor Deposition of Copper for Advanced On-Chip Interconnects." MRS Bulletin 19, no. 8 (August 1994): 49–54. http://dx.doi.org/10.1557/s0883769400047734.

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Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density, and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length will be at 0.18 μm, while microprocessors will pack more than 15 million transistors over an area ~700 mm. To conserve area, interconnects will continue to be stacked at an increasing number of levels (six by the year 2000, versus four in today's leading microprocessors), and the minimum spacing and width within an interconnect layer will shrink to 0.3 μm. In addition, it is expected that future interconnects will need to sustain increasingly higher current densities without electromigration failures.Aluminum alloys are the conductors of choice in present-day interconnects, and much effort is focused on means to extend the usefulness of aluminum through improvements in reliability, either by new alloy formulations or by the development of complicated multimetal stacks. A more radical approach, which is gaining increased attention, is the replacement of aluminum altogether by copper. The bulk resistivity of copper is significantly lower than that of aluminum (1.7 μΩ cm for Cu versus 3.0 μΩ cm for Al-Cu), which is expected to translate to interconnects of higher performance because of reduction in signal propagation delay. In addition, the significantly higher melting temperature of copper (~1100°C versus ~600°C for Al-Cu alloys) and its higher atomic weight are expected to translate to improved resistance to electromigration.
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Sasagawa, K., N. Yamaji, and S. Fukushi. "Threshold Current Density of Electromigration Damage in Angled Polycrystalline Line." Key Engineering Materials 353-358 (September 2007): 2958–61. http://dx.doi.org/10.4028/www.scientific.net/kem.353-358.2958.

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As silicon ICs continue to scale down, several reliability issues have emerged. Electromigration- the transportation of metallic atoms by the electron wind- has been recognized as one of the key damage mechanisms in metallic interconnects. It is known that there is a threshold current density of electromigration damage in via-connected lines. The evaluation of the threshold current density is a matter of the great interest from the viewpoint of IC reliability. In this study, Al polycrystalline lines with two-dimensional shape, i.e. angled lines are experimentally treated for the evaluation. Comparing the experimental result with that of straight-shaped line, the effect of line-shape on the threshold current density of electromigration damage is discussed.
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Chen, Giin-Shan, Ching-En Lee, Yi-Lung Cheng, Jau-Shiung Fang, Chien-Nan Hsiao, Wei-Chun Chen, Yiu-Hsiang Chang, Yen-Chang Pan, Wei Lee, and Ting-Hsun Su. "Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer." Journal of The Electrochemical Society 169, no. 8 (August 1, 2022): 082519. http://dx.doi.org/10.1149/1945-7111/ac89b8.

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The downsizing of integrated circuits for the upcoming technology nodes has brought attention to sub-2 nm thin organic/inorganic materials as an alternative to metallic barrier/capping layers for nanoscaled Cu interconnects. While self-assembled monolayers (SAMs) serving as the barrier materials for copper metalized films are well studied, electromigration (EM) of Cu interconnects encapsulated by SAMs is an untouched research topic. In this study, we report an all-wet encapsulating process involving SAM seeding/encapsulating and electroless narrow-gap filling to fabricate nanoscaled copper interconnects that are completely encapsulated by a 1 nm-thin amino-based SAM, subsequently annealed to some extents prior to EM testing. Both annealing and SAM encapsulation retard EM of the Cu interconnects tested at current densities on orders of 108–109 A cm−2. Particularly, SAM encapsulation quintuples the lifetime of, for example, as-fabricated Cu interconnects from 470 to 2,890 s. Electromigration failure mechanisms are elucidated from analyses of activation energies and current-density scale factors obtained from the accelerated EM testing. The importance of SAM qualities (e.g., ordering and layered structure) as a prerequisite for the reliability enhancement cannot be overestimated, and the results of the SAM quality evaluation are presented. The mechanism of reliability enhancement is also thoroughly discussed.
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Xu, Zhijie, Wei Xu, Elizabeth Stephens, and Brian Koeppel. "Mechanical reliability and life prediction of coated metallic interconnects within solid oxide fuel cells." Renewable Energy 113 (December 2017): 1472–79. http://dx.doi.org/10.1016/j.renene.2017.06.103.

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Saito, T., H. Ashihara, K. Ishikawa, M. Miyauchi, Y. Yamada, and H. Nakano. "A Reliability Study of Barrier-Metal-Clad Copper Interconnects With Self-Aligned Metallic Caps." IEEE Transactions on Electron Devices 51, no. 12 (December 2004): 2129–35. http://dx.doi.org/10.1109/ted.2004.838512.

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Amoah, Papa K., Christopher E. Sunday, Chukwudi Okoro, Jungjoon Ahn, Lin You, Dmitry Veksler, Joseph Kopanski, and Yaw Obeng. "(Invited) Towards the Physical Reliability of 3D-Integrated Systems: Broadband Dielectric Spectroscopic (BDS) Studies of Material Evolution and Reliability in Integrated Systems." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 859. http://dx.doi.org/10.1149/ma2022-0217859mtgabs.

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In this talk, we present an overview of our current research focus in developing non-destructive metrology for monitoring reliability issues in 3D-integrated electronic systems. Working closely with the semiconductor industry, we have been looking at various performance limiting phenomena in 3D-interconnects, the associated dielectrics, and advanced packaging for integrated circuits. The talk will identify some common reliability concerns, and identify some metrology gaps, for 3-D integrated systems. We will introduce a suite of microwave-based Broadband Dielectric Spectroscopic (BDS) techniques and show how these non-destructive metrologies can serve as early warning monitors for reliability issues. These techniques are based on the application of high frequency microwaves, to probe impedance changes due to material and structural changes in integrated circuits under various external stress. For example, we will also discuss the combination of BDS with scanning probe infrastructure to create the Scanning Microwave Microscopy (SMM) technique, which has been used to detect buried artifacts and characterize metallic contacts. We further illustrate the capabilities of the BDS-based techniques with case studies of three potential reliability issues in 3D IC. We conclude with a forward look at the future metrology and standards needs 3-D interconnects and the associated advanced packaging.
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Hau-Riege, Stefan P., and Carl V. Thompson. "The Effects of the Mechanical Properties of the Confinement Material on Electromigration in Metallic Interconnects." Journal of Materials Research 15, no. 8 (August 2000): 1797–802. http://dx.doi.org/10.1557/jmr.2000.0259.

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New low-dielectric-constant interlevel dielectrics are being investigated as alternatives to SiO2 for future integrated circuits. In general, these materials have very different mechanical properties from SiO2. In the standard model, electromigration-induced stress evolution caused by changes in the number of available lattice sites in interconnects is described by an effective elastic modulus, B. Finite element calculations were carried out to obtain B as a function of differences in the modulus, E, of interlevel dielectrics, for several stress-free homogeneous dilational strain configurations, for several line aspect ratios, and for different metallization schemes. In contradiction to earlier models, we found that for Cu-based metallization schemes with liners, a decrease in E by nearly two orders of magnitude has a relatively small effect on B, changing it by less than a factor of 2. However, B, and therefore the reliability of Cu interconnects, can be strongly dependent on the modulus and thickness of the liner material.
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Dissertations / Theses on the topic "Reliability of metallic interconnects"

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Gurrum, Siva P. "Thermal Modeling and Characterization of Nanoscale Metallic Interconnects." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10435.

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Temperature rise due to Joule heating of on-chip interconnects can severely affect performance and reliability of next generation microprocessors. Thermal predictions become difficult due to large number of features, and the impact of electron size effects on electrical and thermal transport. It is thus necessary to develop efficient numerical approaches, and accurate metal and dielectric thermal characterization techniques. In this research, analytical, numerical, and experimental techniques were developed to enable accurate and efficient predictions of interconnect temperature rise. A finite element based compact thermal model was developed to obtain temperature rise with fewer elements and acceptable accuracy. Temperature drop across the interconnect cross-section was ignored. The compact model performed better than standard finite element model in two and three-dimensional case studies, and the predictions for a real world structure agreed closely with experimentally measured temperature rise. A numerical solution was developed for electron transport based on the Boltzmann Transport Equation (BTE). This deterministic technique, based on the path integral solution of BTE within the relaxation time approximation, free electron model, and linear response, was applied to a constriction in a finite size thin metallic film. A correlation for effective conductance was obtained for different constriction sizes. The Atomic Force Microscope (AFM) based Scanning Joule Expansion Microscopy (SJEM) was used to develop a new technique to measure thermal conductivity of thin metallic films in the size effect regime. This technique does not require suspended metal structures, and thus preserves the original electron interface scattering characteristics. The thermal conductivities of 43 nm and 131 nm gold films were extracted to be 82 W/mK and 162 W/mK respectively. These measurements were close to Wiedemann-Franz Law predictions and are significantly smaller than the bulk value of 318 W/mK due to electron size effects. The technique can potentially be applied to interconnects in the sub-100 nm regime. A semi-analytical solution for the 3-omega method was derived to account for thermal conduction within the metallic heater. It is shown that significant errors can result when the previous solution is applied for anisotropic thermal conductivity measurements.
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Choi, Zung-Sun. "Reliability of copper interconnects in integrated circuits." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/39553.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.
Includes bibliographical references.
As dimensions shrink and current densities increase, the reliability of metal interconnects becomes a serious concern. In copper interconnects, the dominant diffusion path is along the interface between the copper and the top passivation layer (usually Si3N4). One of the predominant failure mechanisms in Cu has been open-circuit failure due to electromigration-induced void nucleation and growth near the cathode ends of interconnect segments. However, results from accelerated electromigration tests show that the simple failure analyses based on simple void nucleation and growth can not explain the wide range of times-to-failure that are observed, suggesting that other types of failure mechanisms are present. In this thesis, by devising and performing unique experiments through the development of an electromigration simulation tool, unexpected complex failure mechanisms have been identified that have significant effects on the reliability of copper interconnects. A simulation tool was developed by implementing the one-dimensional non-linear differential equation model first described by Korhonen et al. By applying an implicit method (Backward Euler method), the calculation time was significantly reduced, and stability increased, compared to previous tools based on explicit methods (Forward Euler method).
(cont.) The tool was crosschecked with experimental results by comparing void growth rates in simulations and experiments. Using this tool, one can simulate stress and atomic concentration states over the entire length of an interconnect segment or throughout a multi-segment interconnect tree, to identify analyze possible failure locations and mechanisms. Experiments were carried out on dotted-i structures, where two 25jim-lomg segments were connected by a via in the middle. Electrical currents were applied to the two segments independently, and lifetime effects of adjacent segments were determined. Using the simulation tool and calculations, it was shown that adjacent segments have a significant effect on a segment's stress state, even if the adjacent segment has no electrical current. This explains experimental observations. This also suggests that for reliability analyses to be accurate, the states of all adjacent segments must be considered, including the ones without electrical current. In a second set of experiments, the importance of pre-existing voids was investigated. Using in-situ scanning electron microscopy, voids away from the cathode were observed. These voids grew and drifted toward the cathode and the shape of the voids were found to be closely related to the texture and stress state of individual grains in the interconnect.
(cont.) The drift velocity of voids was shown to be directly proportional to surface diffusivity. Electromigration tests on unpassivated samples were performed under vacuum to obtain the surface diffusivity of copper and its dependence on texture orientations. Simulation results show that pre-existing voids cause void growth away from the cathode. Subsequent failure mechanisms differ depending on the location of the pre-existing void and the critical void volume for de-pinning from grain boundaries. If pre-existing voids are present, void-growth-limited failure is expected in interconnects at low current densities, due to growth of pre-existing void, and the lifetimes are expected to scale inversely with j. However, at higher current densities (typical for accelerated testing), failure can occur through nucleation of new voids at the cathode (so that lifetimes scale inversely with j2), or through a mixture of nucleation of new voids and growth of pre-existing voids. These effects must be taken into account to accurately project the reliability of interconnects under service conditions, based on experiments carried out under accelerated conditions.
by Zung-Sun Choi.
Ph.D.
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Garcia-Vargas, Maria José. "Oxidation behaviour of potential materials for metallic SOFC interconnects." Lille 1, 2006. https://pepite-depot.univ-lille.fr/RESTREINT/Th_Num/2006/50376_2006_208.pdf.

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Les interconnecteurs de SOFC à haute température ont deux rôles principaux: la connexion électrique entre les cellules et l'approvisionnement des gaz dans le stack. Ce travail porte sur l'étude d'interconnecteurs métalliques pour SOFC fonctionnant à une température d'environ 800°e. Deux matériaux austénitiques et trois ferritiques, ayant un pourcentage de Cr compris entre 17% et 27%, ont été sélectionnés pour étudier le comportement en oxydation dans différentes atmosphères. Une étude par diffraction des rayons-X (ORX) du comportement d'oxydation de ces matériaux à 800°C a été réalisée pendant les premières 100 h sous air sec et humide. Des essais d'oxydation à moyen terme (1000 h) ont été de plus réalisés. Chaque échantillon a été caractérisé microscopiquement après les essais d'oxydation à temps court et à moyen terme. Pour éviter le problème de la migration du chrome, montré par les études précédentes sur ce type de matériaux, deux couches protectrices de type spinelle ont été développées. Ensuite, quelques échantillons ont été recouverts avec ces couches de protection en utilisant la projection au plasma atmosphérique (APS). Des essais d'oxydation à moyen terme ont été réalisés, sans montrer de migration du chrome à travers la couche de protection. Finalement trois interconnecteurs, avec ou sans une couche de protection, ont été essayés sur la cathode d'une cellule. Les interconnecteurs et les cellules ont été analysées par MEB, après chaque test.
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Gall, Martin. "Investigation of electromigration reliability in Al(Cu) interconnects /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Bashir, Muhammad Muqarrab. "Modeling reliability in copper/low-k interconnects and variability in cmos." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41092.

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The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.
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Garcia-Vargas, Maria J. [Verfasser]. "Oxidation behaviour of potential materials for metallic SOFC interconnects / Maria J Garcia-Vargas." Aachen : Shaker, 2007. http://d-nb.info/1170527221/34.

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Zheng, Yunqi. "Effect of surface finishes and intermetallics on the reliability of SnAgCu interconnects." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/2427.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.
Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Lee, Kitae 1966. "The influence of texture on the reliability of aluminum and copper interconnects /." Thesis, McGill University, 2000. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=37759.

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Texture in films develops during deposition processes and annealing of patterned wafers. Recent studies show that texture influences the performance and reliability of both aluminum and copper interconnects. To improve the current understanding of this matter, the influence of texture on reliability was studied.
The influence of texture on electromigration and stress-induced failures in aluminum interconnects was studied since these are the most often responsible for failures observed in aluminum interconnects. Results obtained showed that a strong {111} texture in aluminum interconnects improves their median time-to-failure. The grain boundary character distribution and percentage of coincidence site lattice (CSL) boundaries, was quantified using orientation imaging microscopy. It was found that the median time-to-failure of specimens increased as the number of low angle and CSL boundaries increased. These boundaries are known to have low diffusivity. It was also demonstrated that while the investigated specimens had grains of comparable size, the grains of similar orientations were clustered in the specimens having the stronger {111} texture. This phenomenon contributed to the longer median time-to-failure of the interconnects by reducing the frequency of high angle grain boundaries. The experimental data obtained shows that the residual stress in films decreases as the intensity of the {111} texture increases. A model based on Monte-Carlo simulation of texture formation during the deposition of aluminum film was proposed to suggest the optimum conditions for a growth of a strong {111} texture component. A low deposition rate and a high mobility of atoms on the surface, which corresponds to a high substrate temperature, can strengthen {111} texture.
Copper has been recently used as an interconnecting material because of its good electromigration resistance and low electrical resistivity. One of the major problems of copper as an interconnecting material is that it easily oxidizes at relatively low temperatures. The formation of oxide degrades the electrical and mechanical properties of copper interconnects. The influence of substrate texture on the oxidation kinetics was studied to suggest methods to reduce copper oxidation. Copper single crystals having (100), (110), (123), (314), (111) and (311) orientations were oxidized at 200ºC in air. Only the Cu2O phase was formed during oxidation. The oxidation of the (100) single crystal substrate was much faster than that of the others. This is attributed to a large number of fine oxide grains on the (100) crystal in the initial stages of oxidation. It is recommended that the {100} texture in copper interconnects should be avoided in order to reduce oxidation rate. A quantitative model was proposed to predict the oxidation kinetics of copper from the texture of the specimens. Reasonable agreement was obtained comparing the model predictions and the experimental results obtained from the test of oxidation of polycrystalline copper specimens. However, further improvement of the model can be done if more data from single crystal experiments are obtained.
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Srikar, V. T. (Vengallatore Thattai) 1972. "Electromigration behavior and reliability of bamboo Al(Cu) interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/85249.

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Sarvari, Reza. "Impact of size effects and anomalous skin effect on metallic wires as GSI interconnects." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/31636.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Meindl, James D.; Committee Member: Davis, Jeffrey A.; Committee Member: Gaylord, Thomas K.; Committee Member: Hess, Dennis W.; Committee Member: Peterson, Andrew F. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Books on the topic "Reliability of metallic interconnects"

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Digital signal integrity: Modeling and simulation with interconnects and packages. Upper Saddle River, NJ: Prentice Hall PTR, 2001.

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Electromigration in thin films and electronic devices: Materials and reliability. Oxford: Woodhead Publishing, 2011.

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Gunawan, Indra. Fundamentals of reliability engineering: Applications in multistage interconnection networks. Hoboken, N.J: John Wiley & Sons, Inc., 2014.

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Wei dian zi ji shu de ke kao xing: Hu lian , qi jian ji xi tong = Reliability of Microtechnology : Interconnects, Devices and Systems. Beijing: Ke xue chu ban she, 2013.

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Symposium on Reliability of Metals in Electronics (1995 Reno, Nev.). Proceedings of the Symposium on Reliability of Metals in Electronics. Pennington, NJ: Electrochemical Society, 1995.

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Symposium F, "Materials, Technology and Reliability of Low-K Dielectrics and Copper Interconnects" (2006 San Francisco, Calif.). Materials, technology and reliability of low-k dielectrics and copper interconnects: Symposium held April 18-21, 2006, San Francisco, California, U.S.A. Edited by Tsui Ting Y and Materials Research Society Meeting. Warrendale, Pa: Materials Research Society, 2006.

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Symposium F, "Materials, Technology and Reliability of Low-K Dielectrics and Copper Interconnects" (2006 San Francisco, Calif.). Materials, technology and reliability of low-k dielectrics and copper interconnects: Symposium held April 18-21, 2006, San Francisco, California, U.S.A. Edited by Tsui Ting Y and Materials Research Society Meeting. Warrendale, Pa: Materials Research Society, 2006.

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Symposium F, "Materials, Technology and Reliability of Low-K Dielectrics and Copper Interconnects" (2006 San Francisco, Calif.). Materials, technology and reliability of low-k dielectrics and copper interconnects: Symposium held April 18-21, 2006, San Francisco, California, U.S.A. Edited by Tsui Ting Y and Materials Research Society Meeting. Warrendale, Pa: Materials Research Society, 2006.

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J, McKerrow Andrew, Materials Research Society Meeting, and Symposim on Materials, Technology and Reliability for Advanced Interconnects and Low-k Dielectrics (2003 : San Francisco, Calif.), eds. Materials, technology and reliability for advanced interconnects and low-k dielectrics, 2003: Symposium held April 21-25, 2003, San Francisco, California, U.S.A. Warrendale, Pa: Materials Research Society, 2003.

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Maex, Karen. Materials, technology and reliability for advanced interconnects and low-k dielectrics: Symposium held April 23-27, 2000, San Fransico, California, U.S.A. Warrendale, Pa: Materials Research Society, 2001.

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Book chapters on the topic "Reliability of metallic interconnects"

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King, Mark K., and Manoj K. Mahapatra. "Protective Coatings for SOFC Metallic Interconnects." In Proceeding of the 42nd International Conference on Advanced Ceramics and Composites, 149–58. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2019. http://dx.doi.org/10.1002/9781119543343.ch14.

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Menzler, Norbert H., Frank Tietz, Martin Bram, Izaak C. Vinke, and L. G. J. Bert de Haart. "Degradation Phenomena in SOFCs with Metallic Interconnects." In Advances in Solid Oxide Fuel Cells IV, 93–104. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2009. http://dx.doi.org/10.1002/9780470456309.ch9.

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Vanstreels, Kris, Han Li, and Joost J. Vlassak. "Mechanical Reliability of Low-k Dielectrics." In Advanced Interconnects for ULSI Technology, 339–67. Chichester, UK: John Wiley & Sons, Ltd, 2012. http://dx.doi.org/10.1002/9781119963677.ch10.

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Oates, Anthony S., Richard C. Blish, Gennadi Bersuker, and Lu Kasprzak. "Reliability of Electron Devices, Interconnects and Circuits." In Guide to State-of-the-Art Electron Devices, 107–19. Chichester, UK: John Wiley & Sons, Ltd, 2013. http://dx.doi.org/10.1002/9781118517543.ch9.

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Hu, Chao-Kun, René Hübner, Lijuan Zhang, Meike Hauschildt, and Paul S. Ho. "Scaling and Microstructure Effects on Electromigration Reliability for Cu Interconnects." In Advanced Interconnects for ULSI Technology, 291–337. Chichester, UK: John Wiley & Sons, Ltd, 2012. http://dx.doi.org/10.1002/9781119963677.ch9.

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Zhu, Q. S., H. Y. Liu, L. Zhang, Q. L. Zeng, Z. G. Wang, and J. K. Shang. "Electromechanical Coupling in Sn-Rich Solder Interconnects." In Lead-Free Solders: Materials Reliability for Electronics, 251–71. Chichester, UK: John Wiley & Sons, Ltd, 2012. http://dx.doi.org/10.1002/9781119966203.ch10.

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Fu, Bo, and Paul Ampadu. "Solutions to Improve the Reliability of On-Chip Interconnects." In Error Control for Network-on-Chip Links, 17–31. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9313-7_2.

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Quadakkers, W. J., J. Piron-Abellan, V. Shemet, and L. Singheiser. "Suitability of Metallic Materials for Interconnects in Solid Oxide Fuel Cells." In New and Renewable Technologies for Sustainable Development, 391–98. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-0296-8_31.

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Khatibi, Golta, Herbert Ipser, Martin Lederer, and Brigitte Weiss. "Influence of Miniaturization on Mechanical Reliability of Lead-Free Solder Interconnects." In Lead-Free Solders: Materials Reliability for Electronics, 443–85. Chichester, UK: John Wiley & Sons, Ltd, 2012. http://dx.doi.org/10.1002/9781119966203.ch18.

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Yang, Zhenguo, Guanguang Xia, and Jeffry W. Stevenson. "Electrical Contacts Between Cathodes and Metallic Interconnects in Solid Oxide Fuel Cells." In Ceramic Engineering and Science Proceedings, 217–24. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2008. http://dx.doi.org/10.1002/9780470291245.ch25.

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Conference papers on the topic "Reliability of metallic interconnects"

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Sasagawa, Kazuhiko, Akihiko Kirita, Takehiro Abo, and Abdul Hafiz Nor Hassan. "Numerical Simulation of Threshold Current Density of Electromigration Damage in Cu Interconnect Tree." In ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASMEDC, 2009. http://dx.doi.org/10.1115/interpack2009-89229.

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As silicon integrated circuits (ICs) continue to scale down, several reliability issues have emerged. Electromigration — the transportation of metallic atoms by the electron wind — has been recognized as one of the key damage mechanisms in metallic interconnects. It is known that there is the threshold current density of electromigration damage in via-connected line. The evaluation of the threshold current density is one of the great interests from the viewpoint of IC reliability. Recently, the threshold current density in interconnect tree was evaluated. However, it might not be so accurate because of evaluation of two-dimensional structure by combining one-dimensional analysis. In this study, the evaluation method of the threshold current density based on the numerical simulation is applied to several kinds of interconnect tree.
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Park, S. B., and Ganesh R. Iyer. "The Role of Intermetallics in Electromigration in Solder Pumps for Lead Free Solder Structure and Its Solder Pad Combination." In ASME 2004 International Mechanical Engineering Congress and Exposition. ASMEDC, 2004. http://dx.doi.org/10.1115/imece2004-62494.

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It is attempted to quantify the role of intermetallics for the electromigration in flip chip solder interconnects (C4). Intermetallics are formed at the interface of solder and metallic pad where they serve as metallic bonding agent. For the transition to the Pb-free solder interconnects, electromigration is one of the prime reliability concerns. It is observed that some flip chip solder interconnect fails earlier than the estimated time to failure. It is explained by the effect of intermetallics formed by solder and different matching pad metallurgies. This paper quantifies the role of the intermetallics in the time to failure for a system. A series of experiments are being conducted to determine the current exponent and activation energies of the Black’s equation for different solder and pad metallurgy combinations. Two test structures are proposed. The first test structure was made to study the role of the intermetallics and the second structure was made to characterize the pure solder’s electromigration.
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Alajlouni, Sami, Kerry Maize, Peter Bermel, and Ali Shakouri. "Thermoreflectance Imaging of Electromigration in Aluminum Interconnects at Different Ambient Temperatures." In ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/ipack2019-6413.

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Abstract Electromigration (EM) is the process of displacing atoms in metals due to current flow leading to interconnect failures in electronic circuits. As electronics feature sizes continue to shrink, EM is becoming an increasingly serious reliability concern. EM, in aluminum (Al) interconnects, has been studied previously, but typically on the device level using Black’s law [1], without emphasis on the localized heating and defect generation around the failure site. To better understand the local EM process, thermoreflectance (TR) thermal imaging technique is used to obtain temperature profiles with submicron resolution [2]. We show that a simple lifetime prediction using Black’s law is not possible for a micro Al wire having a patterned constriction. The wire fails at two distinct failure locations depending on the level of current excitation. Moreover, the lifetime dependence on ambient temperature was studied. Each failure location had its own extracted activation energy. Our findings suggest that Black’s law may be extended to local features. They also show the potential for the design of local features in extending the lifetime of metallic interconnects. In summary, the temperature profile with submicron spatial resolution offers a unique opportunity to better understand the different mechanisms contributing to EM failures which can be used to design highly reliable interconnects.
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Amalu, E. H., N. N. Ekere, and G. Aminu. "Effects of inter-metallic compound on high temperature reliability of flip chip interconnects for fine pitch applications." In Technology (ICAST). IEEE, 2011. http://dx.doi.org/10.1109/icastech.2011.6145173.

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Sasagawa, Kazuhiko, and Shota Fukushi. "Evaluation of Threshold Current Density of Electromigration Damage in Angled Bamboo Lines." In ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/ipack2007-33237.

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As silicon integrated circuits (ICs) continue to scale down, several reliability issues have emerged. Electromigration — the transportation of metallic atoms by the electron wind — has been recognized as one of the key damage mechanisms in metallic interconnects. It is known that there is the threshold current density of the electromigration damage in the via-connected line. The evaluation of the threshold current density is one of the great interests from the viewpoint of IC reliability. In this study, metal lines with two-dimensional shape, i.e. angled metal lines are treated. The evaluation method of the threshold current density is applied to the metal line. The method is based on the numerical simulation of the building-up process of the atomic density distribution in the bamboo line by using the governing parameter for electromigration damage. Comparing the evaluated results of the angled line with that of straight-shaped line, the effects of corner position and line length on threshold current density of electromigration damage are discussed.
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Horiuchi, Ryota, Kazuhiko Sasagawa, and Kazuhiro Fujisaki. "Damage of Flexible Electronic Line Under Mechanical and Electrical Stress Loading." In ASME 2021 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/ipack2021-68902.

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Abstract Flexible printed circuits (FPCs) are widely used in electronic devices such as movable part line or wearable sensor. Inkjet printing is attracting attention because it can draw electric lines of any shape without a photo mask. The mechanical characteristics such as flexibility or durability of electric lines have been evaluated by bending and tensile tests. Moreover, the reliability characteristics of metal particle ink lines under electric current loading have been recently evaluated. However, the electronic line has not been evaluated under both the mechanical stress due to bending deformation and the electrical stress due to electric current. According to scaling down of electric devices, the current density and Joule heat in interconnect line increase and electromigration (EM) damage becomes a serious problem. EM is a transportation phenomenon of metallic atoms caused by electron wind under high-density electric current. Reducing EM damage is extremely important to enhance device reliability. In this study, high-density current loading tests of flexible electronic line were conducted under bending deformation of the substrate in order to investigate the effect of mechanical stress on the EM damage of the electronic line. As the results of current loading tests, the specimens with bending deformation became open circuits in shorter time than that without bending deformation. Therefore, it is considered that the bending deformation is affected on the electric reliability characteristic of the flexible electronic lines reflecting EM damage.
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Beniam, Iyoel, Scott A. Mathews, Nicholas A. Charipar, Raymond C. Y. Auyeung, and Alberto Piqué. "Laser printing of 3D metallic interconnects." In SPIE LASE, edited by Bo Gu, Henry Helvajian, and Alberto Piqué. SPIE, 2016. http://dx.doi.org/10.1117/12.2213646.

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Saito, Daiki, Kazuhiko Sasagawa, Takeshi Moriwaki, and Kazuhiro Fujisaki. "Damage of Flexible Electronic Line Printed With Ag Nanoparticle Ink due to High-Current Density." In ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/ipack2019-6408.

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Abstract Flexible printed circuits (FPCs) are widely used in electronic devices such as movable part line or wearable sensor. Photolithography is one of the most popular processes for fabricating electric interconnect lines. However, inkjet printing has attracted attention because the method can draw an arbitrary-shape electric lines without any mask. Therefore, nanoparticle metal ink is widely used for printing of conductive electric lines with lowering cost and small-lot production. The physical characteristics such as flexibility or durability of metal nanoparticle ink lines have been evaluated by bending or tensile tests. By contrast, the evaluation method has not been sufficiently established for the electrical characteristics of these lines, and the failure mechanism under high-current density has not been clarified. According to scaling down of electric devices, current density and Joule heating in device lines increase and electromigration (EM) damage becomes a serious problem. EM is a transportation phenomenon of metallic atoms caused by electron wind under high-current density. Reducing EM damage is extremely important to enhance device reliability. In this study, current loading tests of metal nanoparticle ink line were performed to discuss damage mechanism and evaluate electrical reliability under high-current density condition. As the results of current loading tests, the thickness of cathode part of straight-test line was decreased. It is considered that atomic transport from the cathode to the anode occurred by EM phenomenon. The line surface became rough and aggregates of particles generated at middle or anode parts of straight-test line by high-current loading. Both of atomic transport and aggregate generation were closely related the changes of potential drop, their dominances were varied depending the current density value.
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Brandao, Mauricio, Fabio Pires, Ingrid Poloponsky, Fabio Santos, and Diogo Lopes. "Flexible Pipes Subjected to SCC CO2: Review and Means to Increase Reliability on Service Life Applied to Brazilian Pre-Salt Fields." In Offshore Technology Conference. OTC, 2021. http://dx.doi.org/10.4043/31135-ms.

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Abstract Flexible Pipes were widely used in Brazil offshore developments and the challenge on overcoming increasing water depths, high pressures and fluids with high contaminants was always present. In 2017 a new failure mode, called SCC CO2 was disclosed bringing such disruption in the use of this equipment since, at that time, the conditions observed in Brazilian Pre salt were like the "perfect storm" for the failure mode to happen. It had high concentrations of CO2, therefore high permeation in the anulus, high stresses and the possibility to have anulus flooded as result of an outer sheath breach or even due to permeated water. These were the triple conditions needed to have the failure, considering that all metallic material used in the pipe were subjected to this phenomenon. Since the discovery was made, several test campaigns to better understand and replicate the phenomena started. They covered pipe retrieved from field dissection, several small-scale materials testing, and fracture mechanics to create reliable crack propagation calculations. There were 3 mains focus areas; to understand how to deal with the installed fleet, to define the conditions in which a crack would appear and define, using fracture mechanics, how long a crack would take to break the wire. In other words, it was intended to define what is the remaining service life. As a result of this investigation some initial beliefs like that all materials were subjected to the phenomena and that a solution was far away were somehow reduced and reshaped. There was also the initiative to embark on technology for detection of the anulus condition, mainly to define if it is flooded or not. Some ROV inspection means were added to the endfitting and some sensors were added to the interconnected pipe sections that allow conditioning monitoring or inspection from the floating unit, not using a ROV. This paper will cover the improvements done since the disclosure of the phenomena in 2017, reviewing what is known about it so far, what is still to be discovered and how the results achieved to date can contribute for a more reliable and longer service life for the flexible pipes to be applied in a rich CO2 environment.
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Chiriac, Victor Adrian, and Tien-Yu Tom Lee. "Thermal Design Analysis of Free Space Optical Interconnect (FSOI) Package Module." In ASME 2001 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2001. http://dx.doi.org/10.1115/imece2001/htd-24389.

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Abstract A detailed thermal analysis for the FSOI (Free Space Optical Interconnect) technology incorporating VCSEL (Vertical Cavity Surface Emitting Laser) devices is performed using commercially available software. FSOI is one of the latest technologies used to transmit information at high-speed to/from a microprocessor to memory device via photons. Due to large heat dissipation and compact packaging design, temperature and associated thermal strain/stress could reach high values in the FSOI assembly, causing serious reliability and quality problems. Several design options are investigated in order to provide optimal thermal management for the FSOI module, and maintain VCSEL temperatures within reasonable limits. Convective cooling results for both organic and ceramic boards are investigated. For designs with organic boards and without any thermal enhancement, the VCSEL temperature is well above the acceptable limit of 85°C at an ambient temperature of 30°C. The sequential inclusion of pedestals, board thermal vias, conductive rings between the optical modules, and metallic (Al) rods will significantly enhance the module thermal performance and reduce VCSEL temperature to 46°C. The presence of thermal vias in the organic board is critical; however, if the copper area percentage in the via block vs. the die area is above 3%, the VCSEL temperatures will remain constant. The ceramic boards provide a good thermal solution, as VCSEL temperatures remain below the upper limit without including any thermal vias in the board. The comparison between the effect of convective air speed on FSOI with ceramic versus organic boards reveals that the VCSEL temperature is slightly higher (less than 2°C) for the case incorporating a ceramic board. However, the ceramic board has no thermal vias, compared to the 100% copper via block in the organic board. Hence, the same results are accomplished with much less complexity in the ceramic substrate design alternative. This option is suggested for manufacturing purposes, with improved thermal performances.
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Reports on the topic "Reliability of metallic interconnects"

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Anil V. Virkar. Electrically Conductive, Corrosion-Resistant Coatings Through Defect Chemistry for Metallic Interconnects. Office of Scientific and Technical Information (OSTI), December 2006. http://dx.doi.org/10.2172/920189.

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Vladimir Gorokhovsky. Oxidation Resistant, Cr Retaining, Electrically Conductive Coatings on Metallic Alloys for SOFC Interconnects. Office of Scientific and Technical Information (OSTI), March 2008. http://dx.doi.org/10.2172/947016.

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Kang, Seung Hyuk. Effects of microstructural control on the failure kinetics and the reliability improvement of Al and Al-alloy interconnects. Office of Scientific and Technical Information (OSTI), December 1996. http://dx.doi.org/10.2172/469118.

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Michael, Joseph Richard, Richard P. Grant, Mark Andrew Rodriguez, Jamin Pillars, Donald Francis Susan, Bonnie Beth McKenzie, and William Graham Yelton. Understanding and predicting metallic whisker growth and its effects on reliability : LDRD final report. Office of Scientific and Technical Information (OSTI), January 2012. http://dx.doi.org/10.2172/1038184.

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Ritchie, Robert O., and Mukul Kumar. A Study on the Role of Grain-Boundary Engineering in Promoting High-Cycle Fatigue Resistance and Improving Reliability in Metallic Alloys for Propulsion Systems. Fort Belvoir, VA: Defense Technical Information Center, April 2005. http://dx.doi.org/10.21236/ada456825.

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