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Journal articles on the topic 'Regular architecture'

Author: Grafiati

Published: 28 June 2021

Last updated: 5 February 2022

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1

Trobec, Roman, Janez Korenini, and Ludvik Gyergyek. "A regular WSI-node architecture." Microprocessing and Microprogramming 21, no. 1-5 (August 1987): 75–81. http://dx.doi.org/10.1016/0165-6074(87)90021-4.

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2

Antonov, Vadim G. "A regular architecture for operating system." ACM SIGOPS Operating Systems Review 24, no. 3 (July 1990): 22–39. http://dx.doi.org/10.1145/382244.382830.

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3

Parravicini, Daniele, Davide Conficconi, Emanuele Del Sozzo, Christian Pilato, and Marco D. Santambrogio. "CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–24. http://dx.doi.org/10.1145/3476982.

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Regular Expression (RE) matching is a computational kernel used in several applications. Since RE complexity and data volumes are steadily increasing, hardware acceleration is gaining attention also for this problem. Existing approaches have limited flexibility as they require a different implementation for each RE. On the other hand, it is complex to map efficient RE representations like non-deterministic finite-state automata onto software-programmable engines or parallel architectures. In this work, we present CICERO , an end-to-end framework composed of a domain-specific architecture and a companion compilation framework for RE matching. Our solution is suitable for many applications, such as genomics/proteomics and natural language processing. CICERO aims at exploiting the intrinsic parallelism of non-deterministic representations of the REs. CICERO can trade-off accelerators’ efficiency and processors’ flexibility thanks to its programmable architecture and the compilation framework. We implemented CICERO prototypes on embedded FPGA achieving up to 28.6× and 20.8× more energy efficiency than embedded and mainstream processors, respectively. Since it is a programmable architecture, it can be implemented as a custom ASIC that is orders of magnitude more energy-efficient than mainstream processors.

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4

Korotkiy, V. A., and E. A. Usmanova. "Regular linear surfaces in architecture and construction." Journal of Physics: Conference Series 1441 (January 2020): 012065. http://dx.doi.org/10.1088/1742-6596/1441/1/012065.

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5

Polimeni, Beniamino. "PRODUCING DESIGN OBJECTS FROM REGULAR POLYHEDRA: A PRACTICAL APPROACH." Boletim da Aproged, no. 34 (December 2018): 49–55. http://dx.doi.org/10.24840/2184-4933_2018-0034_0007.

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In the last few years, digital modelling techniques have played a major role in architecture and design, influencing, at the same time, the creative process and the fabrication of objects. This revolution has produced a new productive generation of architects and designers focused on the expanding possibilities of material and formal production, reinforcing the idea of architecture as an interaction between art and artisanship. This original perspective inspires this paper, which illustrates the contemporary scenario and provides some practical guidance about tools and technologies the designers most often use for creating geometric sculptures with 3D printing. Creative possibilities of topological mesh modelling are used to generate complex geometries from regular polyhedra. This process explores how combining different geometric operations can activate architectural inquiry and generate fascinating shapes with creative flexibility.

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DEPRETTERE, ED F., PETER HELD, and PAUL WIELAGE. "MODEL AND METHODS FOR REGULAR ARRAY DESIGN." International Journal of High Speed Electronics and Systems 04, no. 02 (June 1993): 133–201. http://dx.doi.org/10.1142/s012915649300008x.

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We present a unified framework for the transformation of algorithms to architectures in the domains of high speed signal and algebraic processing. The framework starts from algorithmic specifications in a language suited for numerical analysis (such as Matlab), transforms the high level description into hierarchical and structured data flow dependence graphs, allows the designer to manipulate the graphs, to merge them, abstract them, regularize them, cluster and partition them etc… until the description of an architecture which can represent the hardware in a precise manner is obtained. A generic model for hierarchical, parametrized descriptions assures a consistent design methodology throughout. In the process, we not only generate attractive parallel architectures based on a fixed array of processing elements, but also their control and the program that has to be executed by the host processor. Because of the parametrization, the designs are "generic" and hence reusable, but they are restricted to cases where the parameters are known at "generation time".

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7

Lalvani, Haresh. "Higher Dimensional Periodic Table Of Regular And Semi-Regular Polytopes." International Journal of Space Structures 11, no. 1-2 (April 1996): 155–71. http://dx.doi.org/10.1177/026635119601-222.

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This paper presents a higher-dimensional periodic table of regular and semi-regular n-dimensional polytopes. For regular n-dimensional polytopes, designated by their Schlafli symbol {p,q,r,…u,v,w}, the table is an (n-1)-dimensional hypercubic lattice in which each polytope occupies a different vertex of the lattice. The values of p,q,r,…u,v,w also establish the corresponding n-dimensional Cartesian co-ordinates (p,q,r,…u,v,w) of their respective positions in the hypercubic lattice. The table is exhaustive and includes all known regular polytopes in Euclidean, spherical and hyperbolic spaces, in addition to others candidate polytopes which do not appear in the literature. For n-dimensional semi-regular polytopes, each vertex of this hypercubic lattice branches into analogous n-dimensional cubes, where each n-cube encompasses a family with a distinct semi-regular polytope occupying each vertex of each n-cube. The semi-regular polytopes are obtained by varying the location of a vertex within the fundamental region of the polytope. Continuous transformations within each family are a natural fallout of this variable vertex location. Extensions of this method to less regular space structures and to derivation of architectural form are in progress and provide a way to develop an integrated index for space structures. Besides the economy in computational processing of space structures, integrated indices based on unified morphologies are essential for establishing a meta-structural knowledge base for architecture.

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Badran, Tamer, Hany Ahmad, and Mohamad Abdel-Gawad. "A reconfigurable multi-byte regular-expression matching architecture." International Conference on Electrical Engineering 6, no. 6 (May 1, 2008): 1–10. http://dx.doi.org/10.21608/iceeng.2008.34330.

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9

Hawkes. "A Regular Fault-Tolerant Architecture for Interconnection Networks." IEEE Transactions on Computers C-34, no. 7 (July 1985): 677–80. http://dx.doi.org/10.1109/tc.1985.1676608.

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10

Mangard, S., M. Aigner, and S. Dominikus. "A highly regular and scalable aes hardware architecture." IEEE Transactions on Computers 52, no. 4 (April 2003): 483–91. http://dx.doi.org/10.1109/tc.2003.1190589.

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11

Lee, Tsern-Huei. "Hardware Architecture for High-Performance Regular Expression Matching." IEEE Transactions on Computers 58, no. 7 (July 2009): 984–93. http://dx.doi.org/10.1109/tc.2008.145.

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12

Beck Lassen, Frank. "Regular, Dependable, Mechanical." Contributions to the History of Concepts 5, no. 1 (May 1, 2009): 94–116. http://dx.doi.org/10.1163/187465609x430872.

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This article examines the de facto rule of Johann Friedrich Struensee from 1770 to 1772 in Denmark, in which an effort was made to implement administrative reforms inspired by the ideas of French materialism and Prussian cameralism. Metaphors, particularly mechanical ones, had an important role in Struensee's attempt to legitimize his actions. Based on theoretical premises first presented by Hans Blumenberg, this article investigates two issues: first, how explicit and implicit mechanical and machine-like metaphors were used by Struensee to indicate the ideal architecture of the Danish absolutist state in the 1770s; and second, how his opponents made use of the same metaphors to describe what they saw as Struensee's illegitimate reach for power.

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13

Yun, SangKyun. "Regular Expression Matching Processor Architecture Supporting Character Class Matching." Journal of KIISE 42, no. 10 (October 15, 2015): 1280–85. http://dx.doi.org/10.5626/jok.2015.42.10.1280.

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14

Li, Qiyue, Jie Li, Jianping Wang, Baohua Zhao, and Yugui Qu. "A pipelined processor architecture for regular expression string matching." Microprocessors and Microsystems 36, no. 6 (August 2012): 520–26. http://dx.doi.org/10.1016/j.micpro.2012.04.004.

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15

Shi, Jiang Yi, Jie Pang, Zhi Xiong Di, Yao Hui Liu, and Yun Song Li. "High Throughput VLSI Architecture of MQ-Coder for JPEG2000." Advanced Materials Research 403-408 (November 2011): 2321–24. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.2321.

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In this paper, a design of high throughput VLSI architecture of MQ-Coder is proposed. Usually, because the regular operation of the MQ-Coder is sequential, the coding speed will be bottlenecked at the interface between the output of the Bit-Plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture can process two symbols for each clock cycle. The main characteristics are the prediction of index, the simplified condition of renormalization, and the partly parallel architecture in renormalization. From synthesis results of the DC tools, using the TSMC 0.18 μm technology library, the frequency can reach 285.4MHz, which is comparable to that of other architectures and suitable for chip implementation.

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HAEGEMAN, LILIANE, ANDRÉ MEINUNGER, and ALEKSANDRA VERCAUTEREN. "The architecture of it-clefts." Journal of Linguistics 50, no. 2 (April 3, 2013): 269–96. http://dx.doi.org/10.1017/s0022226713000042.

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This paper examines quasi-monoclausal left-peripheral analyses of English it-clefts. Though attractive because such analyses bring out commonalities between it-clefts on the one hand and focus fronting and wh-questions on the other, the range of word order variations available in English it-clefts reveals that such monoclausal analyses of it-clefts lead to considerable complications of implementation, ultimately undoing the gain in terms of economy that initially would seem to justify them. In particular, we will show that, on closer inspection, the presumed focus fronting in it-clefts cannot be targeting the position deployed for ‘regular’ left-peripheral focus fronting. Moreover, both implementations of the monoclausal analysis discussed make the wrong predictions with respect to the distribution of it-clefts. In particular, as already argued by Hooper & Thompson (1973) and Emonds (1976), English it-clefting, unlike ‘regular’ focus fronting, is not a main clause phenomenon. Given these objections, we conclude that the left-peripheral analyses of it-clefts are ill-founded.

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17

Song, Wei, Huijing Han, Jianhua Wu, and Meiran Xie. "Ladder-like polyacetylene with excellent optoelectronic properties and regular architecture." Chem. Commun. 50, no. 85 (August 29, 2014): 12899–902. http://dx.doi.org/10.1039/c4cc05524a.

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18

Astola, J., and D. Akopian. "Architecture-oriented regular algorithms for discrete sine and cosine transforms." IEEE Transactions on Signal Processing 47, no. 4 (April 1999): 1109–24. http://dx.doi.org/10.1109/78.752608.

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19

Brodie, Benjamin C., David E. Taylor, and Ron K. Cytron. "A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching." ACM SIGARCH Computer Architecture News 34, no. 2 (May 2006): 191–202. http://dx.doi.org/10.1145/1150019.1136500.

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20

Manic, Bozidar, Dragana Vasiljevic-Tomic, and Ana Nikovic. "Contemporary Serbian Orthodox church architecture: Architectural competitions since 1990." Spatium, no. 35 (2016): 10–21. http://dx.doi.org/10.2298/spat1635010m.

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This paper focuses on the architectural competitions for Orthodox Christian churches in Serbia since 1990, both on the analysis of the designs submitted and the competition requirements. The first competition for an Orthodox church in Serbia after World War II was announced for Pristina in 1991. After that, competitions for the temple in Cukarica, Novi Beograd, Nis, Aleksinac and Krusevac were conducted. Thanks to the fact that architectural competitions allow a greater degree of creative freedom to the architects than regular practice, various solutions were offered, from replicas of models from architectural history and tradition to fully non-traditional proposals. Depending on the relationship to tradition, architectural design approaches can be classified into three main groups: radically modernizing, conservatively traditionalist, and compromising. Of the six competitions conducted, four churches were built, which are among the most architecturally successful newer churches in Serbia. This points to the importance of the implementation of the architectural competition in this field of architecture. The diversity of the award-winning projects shows that there is awareness of the possibility for the further development of church architecture, favouring a moderate approach.

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21

Kreft, Lev. "Architecture through sport." SAJ - Serbian Architectural Journal 4, no. 2 (2012): 176–87. http://dx.doi.org/10.5937/saj1202176k.

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We can find certain parallelism between architecture and sport in history (Rome) and in contemporaneity with spectacular sport as most global kind of entertainment, and recognizable sport architecture as sign of its universal presence. London Olympic Games 2012 followed slogan "Architecture for Humanity", adding ecological and social concern to more traditional idea of sport objects as modern cathedrals. Sport architecture has become a statement, and it embodies ideology which turns sport into reason for hope. Sport architecture is created on the field where standardization of space (and time) exists for more than hundred years, together with concentration of power in sport associations which, during these hundred years, changed their identity from civil society movements into capital enterprise institutions. Original meaning of "sport" (desportes, deport) as activity deported beyond regular and ordinary everyday life was extended into new region of space and time where mass media entertainment is produced. Contemporary sport architecture has to follow specifically sport rules for playground space, and rules of media presence. Sport places are spaces where massive audience watches the game, and were it watches itself watching - to be seen by massive media audience whose virtual presence is perhaps today the most important concern of architectural design for sport.

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22

Neumann, B., T. von Sydow, H. Blume, and T. G. Noll. "Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic." Advances in Radio Science 4 (September 6, 2006): 251–57. http://dx.doi.org/10.5194/ars-4-251-2006.

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Abstract. Future SoCs will feature embedded FPGAs (eFPGAs) to enable flexible and efficient implementations of high-throughput digital signal processing applications. Current research projects on and emerging products containing FPGAs are mainly based on "standard FPGA"-architectures that are optimised for a very wide range of applications. The implementation costs of these FPGAs are dominated by a very complex interconnect network. This paper presents a method to improve the efficiency of eFPGAs by tailoring them for a certain application domain using a parametrisable architecture template derived from the results of a systematic evaluation of the requirements of the application domain. Two different architectures are discussed, a reference architecture to illustrate the methodology and possible optimisation measures as well as a specialised arithmetic-oriented eFPGA for applications like correlators, decoders, and filters. For the arithmetic-oriented architecture, a novel logic element (LE) and a special interconnect architecture that was designed with respect to the connectivity characteristics of regular datapaths, are presented. For both architecture templates, physically optimised implementations based on an automatic design approach have been created. As a first cost comparison of these implementations with standard FPGAs, the LE-density (number of logic elements per mm2) is evaluated. For the arithmetic-oriented architecture, the LE-density could be increased by an order of magnitude compared to standard architectures.

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23

Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.

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24

Abd Elaal, Mohamed, and Fadhel Ghannouchi. "A2×1LINC Transceiver for Enhanced Power Transmission in Wireless Systems." Research Letters in Communications 2007 (2007): 1–4. http://dx.doi.org/10.1155/2007/45301.

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A2×1LINC transceiver based on linear amplification using nonlinear components (LINC) architecture for wireless systems applications is proposed. The layout of the new architecture is presented and the simulation results show that the overall power efficiency of this architecture is superior by more than 300% when compared with that of a regular LINC amplifier. Also the adjacent channel power ratio (ACPR) is lowered to−64.2dBc, compared to−26.1dBc for regular LINC, which improves the system immunity against complex gain imbalances between LINC branches.

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25

Bensaci, Chaima, Youcef Zennir, Denis Pomorski, Fares Innal, and Yiliu Liu. "Distributed vs. Hybrid Control Architecture Using STPA and AHP - Application to an Autonomous Mobile Multi-robot System." International Journal of Safety and Security Engineering 11, no. 1 (February 28, 2021): 1–12. http://dx.doi.org/10.18280/ijsse.110101.

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Systems composed of a fleet of autonomous mobile robots are among the most complex control systems. This control complexity is at a high level especially when those robots navigate in hazardous and dynamic environments such as chemical analysis laboratories. These systems include different dangerous and harmful products (toxic, flammable, explosive...) with different quantity. In order to perform its mission on a regular basis, this multi-robot system can be controlled according to multiple architectures. We propose, firstly, to apply the System Theoretic Process Analysis (STPA) on two selected control architectures, namely distributed and hybrid architectures in order to obtain a set of loss scenarios for each kind of architecture. For further assessment, the Analytic Hierarchy Process (AHP) is used to choose the best architecture. The proposed approach provides a risk analysis and a more practical comparison between the two control architectures of a mobile multi-robot system and facilitates decision-making, even in complex situations.

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26

Linhai, Cui. "An Innovative Approach for Regular Expression Matching Based on NoC Architecture." International Journal of Smart Home 8, no. 1 (January 31, 2014): 45–52. http://dx.doi.org/10.14257/ijsh.2014.8.1.06.

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27

Yang, Yi-Hua, and Viktor Prasanna. "High-Performance and Compact Architecture for Regular Expression Matching on FPGA." IEEE Transactions on Computers 61, no. 7 (July 2012): 1013–25. http://dx.doi.org/10.1109/tc.2011.129.

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28

Matschegewski, Claudia, Susanne Staehlke, Ronny Loeffler, Regina Lange, Feng Chai, Dieter P. Kern, Ulrich Beck, and Barbara J. Nebe. "Cell architecture–cell function dependencies on titanium arrays with regular geometry." Biomaterials 31, no. 22 (August 2010): 5729–40. http://dx.doi.org/10.1016/j.biomaterials.2010.03.073.

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29

Shi, Yuanyuan. "The Three Levels of Education in Site Design Course of Architecture." Journal of World Architecture 5, no. 3 (June 8, 2021): 18–23. http://dx.doi.org/10.26689/jwa.v5i3.2178.

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“Professional Guiding Standards for Advanced Education Architecture in University Undergraduate Students” (2013 edition) indicates that the education system of architecture should include a section on “environment and site.” It should involve six learning components which are concepts of site and environment, site terrain classifications, environment of two tendencies, elements involved in the sites, elements of environmental impact, and site design.[1] As site design (drawing) has become a significant topic in the examination of registered architects, many domestic architecture colleges have set up site design courses as independent ones. After more than ten years of exploration and research in developing the education system of site design courses, teaching experiences and achievements have been acquired. Site design courses have been gradually integrated with general plan design, registered architect examination, and architectural programming. Teachers have specified relevant learning goals in the regular daily curriculum in addition to the basic and vocational education of architecture. In this way, the site design course would be more in line with the educational goals of architecture. This paper aims to analyze the education of site design courses in hope of developing the future architectural education.

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Cui, Linhai, Yusen Qin, Fanyang Kong, and Kaihong Yu. "Design of a Regular Expression Matching System Based on Network on Chip." Open Electrical & Electronic Engineering Journal 7, no. 1 (June 14, 2013): 46–50. http://dx.doi.org/10.2174/1874129001307010046.

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This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

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31

KYRIAKIS-BITZAROS, E. D., D. J. SOUDRIS, and C. E. GOUTIS. "TRANSFORMATION OF NESTED LOOPS INTO UNIFORM RECURRENCES AND THEIR MAPPING TO REGULAR PROCESSOR ARRAYS." Journal of Circuits, Systems and Computers 06, no. 03 (June 1996): 243–65. http://dx.doi.org/10.1142/s0218126696000194.

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A methodology for transforming a class of iterative algorithms, expressed in nested loops, into Uniform Recurrent Equation (URE) forms and their mapping into regular processor array architectures is presented. The propagation space of the variables of the original nested loop is specified by a system of linear equations formed by their index functions. The data flow within the index space, is then localized by the derivation of a set of parametric dependence vectors, which eventually can be used to transform the initial algorithm into a set of UREs. The mapping of the UREs is accomplished by decomposition of the index space into independent subsets of variable instances using the derived dependence vectors. The dependence graphs of the subsets are normalized and subsequently, are mapped on the processor array architecture. The exploitation of the independent subsets leads to significant improvement of the efficiency of the processor array compared to architectures derived by using linear transformations of the entire index space. Under certain conditions, only local interconnections in the processor array are required. The proposed methodology is illustrated by the design of alternative processor arrays implementing the convolution algorithm.

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32

AL-TOWAIQ, MOHAMMAD H., and KHALED DAY. "PARALLEL GAUSS-SEIDEL ON A TORUS NETWORK-ON-CHIP ARCHITECTURE." Journal of Interconnection Networks 13, no. 01n02 (March 2012): 1250001. http://dx.doi.org/10.1142/s0219265912500016.

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Network-on-chip multicore architectures with a large number of processing elements are becoming a reality with the recent developments in technology. In these modern systems the processing elements are interconnected with regular network-on-chip (NoC) topologies such as meshes and trees. In this paper we propose a parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a torus NoC architecture. The proposed parallel algorithm is O (Nn2/k2) time complexity for solving a system with matrix of order n on a k × k torus NoC architecture with N iterations assuming n and N are large compared to k (i.e. for large linear systems that require a large number of iterations). We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

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33

Gal-Ezer, Judith, and Mark Trakhtenbrot. "Algebraic characterization of regular languages." ACM SIGCSE Bulletin 38, no. 3 (September 26, 2006): 325. http://dx.doi.org/10.1145/1140123.1140232.

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34

Narayan, Apurva, Greta Cutulenco, Yogi Joshi, and Sebastian Fischmeister. "Mining Timed Regular Specifications from System Traces." ACM Transactions on Embedded Computing Systems 17, no. 2 (April 26, 2018): 1–21. http://dx.doi.org/10.1145/3147660.

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35

de Paulo, Vitor, and Cristinel Ababei. "3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/603059.

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We propose new 3D 2-layer and 3-layer NoC architectures that utilizehomogeneousregular mesh networks on a separate layer and one or twoheterogeneousfloorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, or mesh size. Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network performance under the assumption that the clock frequency is given by the length of the physical links. In addition, the 3-layer architecture can offer significantly better network performance compared to the 2-layer architecture.

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36

Guey-Yun Chang, G. J. Chang, and Gen-Huey Chen. "Diagnosabilities of regular networks." IEEE Transactions on Parallel and Distributed Systems 16, no. 4 (April 2005): 314–23. http://dx.doi.org/10.1109/tpds.2005.44.

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37

Tang, Qiu, Lei Jiang, Xin-xing Liu, and Qiong Dai. "A Real-time Updatable FPGA-based Architecture for Fast Regular Expression Matching." Procedia Computer Science 31 (2014): 852–59. http://dx.doi.org/10.1016/j.procs.2014.05.336.

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38

Yun, Sang-Kyun, and Kyu-Hee Lee. "A Hardware Architecture of Regular Expression Pattern Matching for Deep Packet Inspection." Journal of the Korea Society of Computer and Information 16, no. 5 (May 31, 2011): 13–22. http://dx.doi.org/10.9708/jksci.2011.16.5.013.

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39

Day, Khaled, and Mohammad H. Al-Towaiq. "An Efficient Parallel Gauss-Seidel Algorithm on a 3D Torus Network-on-Chip." Sultan Qaboos University Journal for Science [SQUJS] 20, no. 1 (June 1, 2015): 29. http://dx.doi.org/10.24200/squjs.vol20iss1pp29-38.

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Network-on-chip (NoC) multi-core architectures with a large number of processing elements are becoming a reality with the recent developments in technology. In these modern systems the processing elements are interconnected with regular NoC topologies such as meshes and tori. In this paper we propose a parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus NoC architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with a matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

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40

Zhang, Yanjun, and S. Q. Zheng. "An Efficient Parallel VLSI Sorting Architecture." VLSI Design 11, no. 2 (January 1, 2000): 137–47. http://dx.doi.org/10.1155/2000/14617.

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We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively to sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is proposed. This architecture consists of three components, linear arrays that support constant-time operations, a multilevel sorting network, and a termination detection tree, all operating concurrently in systolic processing fashion. The structure of this sorting architecture is simple and regular, highly suitable for VLSI realization. Theoretical analysis and experimental data indicate that the performance of this architecture is likely to be excellent in practice.

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Tyng, Anne Griswold. "Inner Vision Toward An Architecture Of Organic Humanism." International Journal of Space Structures 11, no. 1-2 (April 1996): 69–84. http://dx.doi.org/10.1177/026635119601-213.

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Perception of geometry as inorganic/abstract is changed to natural/human by electron-microscopic discoveries of the geometry of molecules within us, by discoveries in the unconscious mind of archetypal geometry that orients and directs conscious attitudes and creativity. A mathematical model of random process and ordered synthesis for geometries of matter and mind is seen in a Fibonacci-Divine Proportion (F-DP) Matrix of Simultaneous Randomness and Order. Fibonacci summations of cross-sections of random probability in (2 D) Pascal Triangle and of successive slices through (3 D Pascal) Probability Pyramid (Tyng and Yanchenko) accumulate toward precise Divine Proportion connection between summations, offering possible ordered recombinations of dot patterns/information bits in morphology/creativity. Fibonacci dot patterns expanded into Fibonacci circle-packings within circles and sphere-packings within spheres produce regular polygons and regular polyhedra. The Divine Proportion extends regular Higher Solids to helix and spiral toward greater complexity and randomness, offering new possibilities for order and synethesis. Fibonacci fitting of circled rather than squared sides of right-angled triangles within next larger Fibonacci circle, and Fibonacci right-angled triangulation of sphere-packings within spheres, expands the Pythagorean Theorem to overlapping summation sequence toward Divine Proportion precision. A natural cycle of the F-DP matrix occurs in Deoxyhemoglobin molecule in relative distances between the four hemes that order its 10,000 atom complexity within simplicity. Cycles of underlying geometric order toward entropy to order correlate with changing form empathies in history and in individual human creative process. Examples in current architectural cycle show a shift from perception of geometry as inorganic to geometry expressing “growth”, human scales and orientations to geometry with a “life of its own” toward resonant life-enhancing architecture of Organic Humanism.

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Guo, Shaori, and Wayne Luk. "An integrated system for developing regular array designs." Journal of Systems Architecture 47, no. 3-4 (April 2001): 315–37. http://dx.doi.org/10.1016/s1383-7621(00)00052-7.

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Cachera, David, and Katell Morin-Allory. "Verification of safety properties for parameterized regular systems." ACM Transactions on Embedded Computing Systems 4, no. 2 (May 2005): 228–66. http://dx.doi.org/10.1145/1067915.1067917.

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Majumdar, Rupak, Elaine Render, and Paulo Tabuada. "A theory of robust omega-regular software synthesis." ACM Transactions on Embedded Computing Systems 13, no. 3 (December 2013): 1–27. http://dx.doi.org/10.1145/2539036.2539044.

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45

Baverel, Olivier, and Hoshyar Nooshin. "Nexorades Based on Regular Polyhedra." Nexus Network Journal 9, no. 2 (October 2007): 281–98. http://dx.doi.org/10.1007/s00004-007-0043-0.

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46

Keller, Jörg. "Regular layouts of butterfly networks." Integration 17, no. 3 (November 1994): 253–63. http://dx.doi.org/10.1016/0167-9260(94)90003-5.

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47

Lv, Yisheng, Liquan Wang, Fan Liu, Weisheng Feng, Jie Wei, and Shaoliang Lin. "Self-assembly of amphiphilic alternating copolymers with stimuli-responsive rigid pendant groups." Polymer Chemistry 11, no. 29 (2020): 4798–806. http://dx.doi.org/10.1039/d0py00765j.

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Melenka, Garrett W., and Jason P. Carey. "Development of a generalized analytical model for tubular braided-architecture composites." Journal of Composite Materials 51, no. 28 (February 21, 2017): 3861–75. http://dx.doi.org/10.1177/0021998317695421.

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Tubular braided composites are manufactured using a Maypole braiding machine which interlaces yarns in order to manufacture a braided structure. Braids can be produced in Diamond (1/1), Regular (2/2) and Hercules (3/3) patterns. In addition, axial yarns can be included in order to produce triaxial braid structures. Several analytical and finite element analysis models have been developed in order to predict the elastic properties of braided composites. Despite the fact that many models exist for braided composites, a comprehensive model has not been presented that can capture the variety of braiding patterns which can be manufactured using the braiding process. In this study, a new analytical model has been developed that can describe the elastic properties of Diamond, Regular and Hercules braids. The proposed analytical model uses a volume averaging stiffness method in order to account for yarn undulations and the orientation of braid yarns within the braid structure. The model presented here has been compared with the existing FEA and analytical models and has also been validated experimentally. Experimental validation comprised tensile and torsional tests in order to predict the longitudinal and shear moduli for both Diamond and Regular braid geometries. The experimental and proposed model results highlight the effect of braiding pattern and braiding angle on the mechanical properties.

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Lamb, Matthew D. "Traceur as Bricoleur. Poaching public space through bricolent use of architecture and the body." Journal of Public Space 2, no. 1 (May 1, 2017): 33. http://dx.doi.org/10.5204/jps.v2i1.48.

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<p>This paper emerged from many months of regular participation in the parkour community in Indianapolis, Indiana. First, this study looks at the art of parkour as a bricolent engagement with architecture. Acts of bricolage, a sort of artistic making-do with objects (including one’s body) in the environment, play with(in) the dominant order to “manipulate the mechanisms of discipline and conform to them only in order to evade them” (de Certeau, 1984: xiv). Second, this study investigates architecture’s participation in the production and maintenance of what de Certeau calls, “operational logic” (p. xi). That is, how architecture acts as a communicative mode of space; one, which conveys rationalized or acceptable ways of being in space. This critical ethnography, then, takes to task the investigation of how traceurs, the practitioners of parkour, uncover emancipatory potential in city space through bricolent use of both architecture and the body.</p>

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Verdier, F., and D. Declercq. "A low-cost parallel scalable FPGA architecture for regular and irregular LDPC decoding." IEEE Transactions on Communications 54, no. 7 (July 2006): 1215–23. http://dx.doi.org/10.1109/tcomm.2006.877980.

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