Dissertations / Theses on the topic 'Regular architecture'

Three models are proposed to evaluate and design distributed reconfigurable systems for fault tolerant, highly reliable applications. These models serve as valuable tools for developing fault tolerant systems. In each model, cells work together in parallel to change the global structure through a series of separate actions. In the Local Supervisor Model (LSM), selected cells guide the reconfiguration process. In the Tessellation Automata Model (TAM), each cell determines its next state based on its state and its neighbors' states, and communicates its state information to its neighbors. In the Interconnected Finite State Machine Model (IFS:MM:), each cell determines its next state and outputs based on its state and its inputs. The hierarchical nature of the TAM and IFSMM provides advantages in evaluating, comparing, and designing systems. The use of each of these models in describing systems is demonstrated. The IFSMM: is emphasized since it is the most versatile of the three models. The IFSMM: is used to identify algorithm weaknesses and improvements, compare existing algorithms, and develop a novel design for a reconfigurable hypercube.
Ph. D.

The aim of this research is to develop computational tools to predict the large amplitude motions and loads on ships travelling with forward speed in waves. An experimental research programme was completed to validate the non-linear prediction method. In this thesis, the results of theoretical and experimental investigations to predict the non-linear ship motions, slamming pressures and bending moments in regular head seas are presented. The ship hull is considered to be a Timoshenko beam, where the vibratory elastic response of the ship is calculated by the modal superposition method with the solution represented in terms of a series of normal modes. It is assumed that the mode shapes and natural frequencies can be determined by a separate structural analysis where this modal information is appropriate to the vessel in the equilibrium reference condition when floating in calm water. The global dynamic shear force and bending moment values are predicted using two different methods:The first method developed is based on the elastic vibratory response due to the total hydrodynamic force; The other is based on the rigid body response due to the linear force superimposed with the elastic response due to the impact forces. The results by the elastic vibratory response due to the total hydrodynamic force (method 1) have a good agreement with the experimental results and these are much better than the results by the rigid body response superimposed with the elastic response (method 2). The non-linear effects due to the change of the hydrodynamic coefficients and the non-linear restoring force should be considered in the ship motion and load predictions. The nonlinearity of ship motions as well as a significant nonlinearity between the hogging and sagging wave and global bending moments are shown in the results obtained from the non-linear theoretical predictions and the experimental data. The non-linear ship motions and sea loads, predicted by the practical computational tools, newly developed in this thesis, can be used to further ship structural strength analysis and guide ship hull design.

The diploma thesis deals with the study of perovskite solar cells with a regular n-i-p architecture. The theoretical part of this work is mainly focused on the stability of perovskite solar cells, i.e. thermal stability and the influence of UV radiation on final perovskite solar cell stability. Furthermore, the deposition methods, the architecture of solar cells and the materials used for the preparation of electron and hole transport layers were described in more detail. The experimental part deals with the optimization of the preparation of perovskite solar cells (especially in terms of resulting photovoltaic conversion efficiency), with a description of the structure preparation process of the final photovoltaic cell and the interpretation of the measured results.

With lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard. Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design. To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called â Sigmaâ architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept. The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor. This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a â non-obstacleâ path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective. In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for futureâ s lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved.
Master of Science

Cette étude menée sur les fondations canoniales de Geoffroy du Loroux, archevêque de Bordeaux de 1136 à 1158, a pour objectif de montrer une implication du prélat dans le parti architectural de ses fondations qui présentent a priori une similitude en plan et en élévation. Grand artisan de la réforme grégorienne en Aquitaine, l'action de Geoffroy du Loroux est bien cernée par sa collection de sermons mais ses fondations n'ont jamais fait l'objet d'une étude de synthèse. Chacune des quatre fondations attribuées à l'archevêque, l'Isle et Pleine-Selve (Gironde), Sablonceaux (Charente-Maritime) et Fontaine-le-Comte (Vienne), a été soumise à une analyse architecturale approfondie, complétée d'une étude métrologique, afin d'appréhender chaque édifice dans sa globalité. Les éléments conservés du XIIe siècle ont ensuite été soumis à une étude comparative. En outre, une discussion est menée autour de l'attribution à Geoffroy du Loroux de la reconstruction de la cathédrale de Bordeaux dès le XIIe siècle.Il s'avère que les fondations liées à Geoffroy du Loroux adoptent un parti architectural stéréotypé et d'une esthétique ostensiblement austère. L'archevêque apparaît comme un prélat soucieux de laisser à ses successeurs des modèles pour transmettre le message de la réforme grégorienne, tant au travers de ses sermons qu'au niveau de ses fondations. Ces dernières se devaient d'être représentatives d'une grande humilité et du retour à la rigueur prôné par la réforme, en totale opposition avec le faste clunisien. Ce travail amène à s'interroger sur le rôle des collégiales qui, utilisées tel un outil de diffusion de la réforme, ont pu freiner l'implantation de Cluny dans le Bordelais.

The plant endoplasmic reticulum (ER), a highly dynamic membrane-bound organelle, is not only the site of secretory protein production and lipid synthesis, but also responsible for calcium storage. It is currently hypothesised that the shape of the ER network relates to these functions. The sheets, large at areas of network are proposed to be the sites of protein production and the tubules, thin, highly-mobile and interconnected, the regions of lipid production and calcium storage. The reticulon protein family has been shown to bend the ER lipid bilayer to form tubules and the edges of sheets. Identifying protein interactors to reticulons may help to understand how the morphology of the ER is controlled or in uenced. Mass spectrometry and co-immunoprecipitation techniques were used to identify protein interactors to the Arabidopsis thaliana seed-specific reticulon, RTN13. Five non-reticulon proteins were found to interact with RTN13 in developing A. thaliana seed; GTP-binding protein 2, lysophospholipase 1, NADH: Cytochrome B5 Reductase 1, sterol methyltransferase 2 and synaptotagmin a. Microscopy analysis of the ER in over-expression lines and T-DNA insertions lines for each putative interactor, showed that only sterol methyltransferase 2 and synaptotagmin a influenced the ER morphology. Additionally, the morphology of the ER was analysed during seed development and germination through confocal microscopy. An image analysis macro was used to determine the percentage of sheet morphology in the network. Significant changes in the amount of sheet morphology were recorded in the ER of cotyledon cells during seed development and over the first six days of germination. Wild type embryos were also compared to mutants known to have altered ER morphology. The analysis suggested that the amount of sheet morphology is maximal at times of maximum protein production, highlighting the link between ER form and function.

Since future microprocessors will have higher current in accordance with Mooreâ s law, there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only for easy thermal management, but also for saving on electricity costs for data centers, or battery life extension for laptop computers. At the same time, high power density is required due to the increased power of the microprocessors. This is especially true for data centers, since more microprocessors are required within a given space (per rack). High power density is also required for laptop computers to reduce the size and the weight. To improve power density, a high frequency is required to shrink the size of the output inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz. Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power density is very low. To attain high efficiency and high power density at the same time, two-stage power architecture was proposed. The concept is â Divide and Conquerâ . A single-stage VR is split into two stages to get better performance. The second stage has about 5V-6V input voltage; thus the duty cycle can be extended and the switching losses are greatly reduced compared with a single-stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high frequencies. The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is required for the first stage since it is in series with the second stage. Previous first stage which is a buck converter has good efficiency but bulky size due to low frequency operation. Another problem with using a buck converter is that light-load efficiency of the first stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does not require voltage regulation, the sweet point for the voltage divider can be determined and high efficiency can be achieved. At the same time, since there are no magnetic components for the switched-capacitor voltage divider, high power density can be achieved. By very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can be as high as 99% by reducing the switching frequency at light load. As for the second stage, different low-voltage devices are evaluated, and the best device combinations are found for high-frequency operation. It has been demonstrated that 91% efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a 1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage respectively. Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other systems. In this dissertation, the two-stage power architecture is applied to two different applications: laptop computers and high-end server microprocessors. The common characteristics of the two applications are their thermal design power (TDP) requirement. Thus the first stage can be designed with much lower power than the maximum system power. It has been demonstrated that the two-stage power architecture can achieve either higher efficiency or higher power density and a lower cost when compared with the single-stage VR. To get higher efficiency, a parallel two-stage power architecture, named sigma architecture, is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the output power, while using a low-power buck converter to achieve voltage regulation. Both the DCX converter and the buck converter can achieve around 90% efficiency when used in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can also be applied to low-power point of load (POL) applications to reduce the magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly compared.
Ph. D.

With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data centers have replaced the 12V DC server rack distribution with a 48V DC distribution, producing a significant overall system efficiency improvement. However, 48V rack architecture raises significant challenges for the voltage regulator modules (VRMs) required for powering the processor. The 48V VRM in the vicinity of the CPU needs to be designed with very high efficiency, high power density, high light-load efficiency, as well as meet all transient requirements by the CPU and GPU. Transferring the well-developed multi-phase buck converter used in the 12V VRM to the 48V distribution platform is not that simple. The buck converter operating with 48V, stepping down to sub 2V, will be subjected to significant switching related loss, resulting in lower overall system efficiency. These challenges drive the need to look for more efficient architectures for 48V VRM solutions. Two-stage conversions can help solve the design challenges for 48V VRMs. A first-stage unregulated converter is used to step-down the 48V to a specific intermediate bus voltage. This voltage will feed a multi-phase buck converter that powers the CPU. An unregulated LLC converter is used for the first-stage converter, with zero voltage switching (ZVS) operation for the primary side switches, and zero current switching (ZCS) along with ZVS operation, for the secondary side synchronous rectifiers (SRs). The LLC converter can operate at high frequency, in order to reduce the magnetic components size, while achieving high-efficiency. The high-efficiency first-stage, along with the scalability and high bandwidth control of the second-stage, allows this architecture to achieve high-efficiency and power density. This architecture is simpler to adopt by industry, by plugging the unregulated converter before the existing multi-phase buck converters on today's platforms. The first challenge for this architecture is the transformer design of the first-stage LLC converter. It must avoid all of the loss associated with high frequency operations, and still achieve high power density without scarifying efficiency. In this thesis, the integrated matrix transformer structure is optimized by SR integration with windings, interleaved primary side termination, and a better PCB winding arrangement to achieve high-efficiency and power density, and minimize the losses associated with high-frequency operations. The second challenge is the light load efficiency improvement. In this thesis a light load efficiency improvement is proposed by a dynamic change of the intermediate bus voltage, resulting in more than 8 % light load efficiency improvements. The third challenge is the selection of the optimal bus voltage for the two-stage architecture. The impact of different bus voltages was analyzed in order to maximize the overall conversion efficiency. Multiple 48V unregulated converters were designed with maximum efficiency >98 %, and power densities >1000 W/in3, with different output voltages, to select the optimal bus voltage for the two-stage VRM. Although the two-stage VRM is more scalable and simpler to design and adopt by current industry, the efficiency will reduce as full power flows in two cascaded DC/DC converters. Single-stage conversion can achieve higher-efficiency and power-density. In this thesis, a quasi-parallel Sigma converter is proposed for the 48V VRM application. In this structure, the power is shared between two converters, resulting in higher conversion efficiency. With the aid of an optimized integrated magnetic design, a Sigma converter suitable for narrow voltage range applications was designed with 420 W/in3 and a maximum efficiency of 94 %. Later, another Sigma converter suitable for wide voltage range applications was designed with 700W/in3 and a maximum efficiency of 95 %. Both designs can achieve higher efficiency than the two-stage VRM and all other state-of-art solutions. The challenges associated with the Sigma converter, such as startup and closed loop control were addressed, in order to make it a viable solution for the VRM application. The 48V rack architecture requires regulated 12V output converters for various loads. In this thesis, a regulated LLC is used to design a high-efficiency and power-density 48V bus converter. A novel integration method of the inductor and transformer helps the LLC achieve the required regulation capability with minimum losses, resulting in a converter that can provide 1KW of continuous power with efficiency of 97.8 % and 700 W/in3 power density. This dissertation discusses new power architectures with an optimized design for the 48V rack architectures. With the academic contributions in this dissertation, different conversion architectures can be utilized for 48V VRM solutions that solve all of the challenges associated with it, such as scalability, high-efficiency, high density, and high BW control.
Doctor of Philosophy
With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. The data center manufacturers have recently adopted a more efficient architecture that supplies a 48V DC server rack distribution instead of a 12V DC distribution to the server motherboard. This helped reduce costs and losses, but as a consequence, raised a challenge in the design of the DC/DC voltage regulator modules (VRM) supplied by the 48V, in order to power the CPU and GPU. In this work, different architectures will be explored for the 48V VRM, and the trade-off between them will be evaluated. The main target is to design the VRM with very high-efficiency and high-power density to reduce the cost and size of the CPU/GPU motherboards. First, a two-stage power conversion structure will be used. The benefit of this structure is that it relies on existing technology using the 12V VRM for powering the CPU. The only modification required is the addition of another converter to step the 48V to the 12V level. This architecture can be easily adopted by industry, with only small modifications required on the system design level. Secondly, a single-stage power conversion structure is proposed that achieves higher efficiency and power density compared to the two-stage approach; however, the structure is very challenging to design and to meet all requirements by the CPU/GPU applications. All of these challenges will be addressed and solved in this work. The proposed architectures will be designed using an optimized magnetic structure. These structures achieve very high efficiency and power density in their designed architectures, compared to state-of-art solutions. In addition, they can be easily manufactured using automated manufacturing processes.

Prohexadione-calcium (P-ca), as ApogeeTM, was evaluated in 2000 and 2001 for impact to grape vegetative and reproductive development. In 2000, P-ca (250 mg/L) was applied to Seyval, Cabernet Sauvignon, and Cabernet franc (125, 250, and 375 mg/L). P-ca reduced primary shoot growth for all cultivars and decreased cane pruning weight of Seyval. P-ca (375 mg/L) increased Cabernet franc canopy gaps but increased Cabernet Sauvignon lateral leaf area and leaf layer number. P-ca reduced components of yield for all cultivars. In 2001, P-ca (250 mg/L) was applied singularly at weekly intervals to Cabernet Sauvignon clusters and pre and post-bloom to Cabernet franc and Chardonnay canopies. Application at E-L stages 21 and 23 decreased Cabernet Sauvignon fruit set whereas application at E-L stages 26, 27, and 29 reduced berry weight without impacting fruit set. Berry weight reduction correlated to higher color intensity (420+520 nm), anthocyanins, total phenols and phenol-free glycosyl-glucose (PFGG). Cabernet franc vegetative and reproductive development was generally not affected yet treatment increased absorbance at 280, 420, and 520 nm, color intensity, anthocyanins and total phenols. Pre-bloom applications inhibited Chardonnay vegetative development, and reduced components of yield, and fruit chemistry values: hydroxycinnamates, total phenols, flavonoids, PPFG and absorbance at 280 and 320 nm. Post-bloom applications did not affect Chardonnay vegetative or reproductive development, yet increased PFGG. Treatment did not affect Chardonnay wine chemistry but two post-bloom applications increased Cabernet franc wine anthocyanins and total phenols. Wine aroma and flavor triangle difference tests did not indicate significant treatment differences.
Master of Science

博士
國立清華大學
資訊工程學系
96
The main purpose of a network intrusion detection system (NIDS) is to inspect the packet header and payload against thousands of predefined malicious or suspicious patterns. These patterns describe behaviors such as denial of service attacks, port scans, or malware. To efficiently represent suspicious patterns, regular expressions are commonly adopted such as Snort[22], Bro[24], and ClamAV[25] because they have better expressive power and flexibility than explicit string patterns. Due to the increasing complexity of network traffic and the growing number of attacks, traditional software-based NIDS will become inadequate for networking needs due to its slowness. To speed up pattern matching, many researchers have proposed hardware approaches which can be classified into two main categories, the logic and the memory architectures. The logic architectures are mostly implemented on Field-Programmable Gate Array (FPGA) because FPGA allows for updating new attack patterns. In addition, the logic architecture is easy to handle certain types of regular expressions containing meta-characters, such as ‘*’, ‘|’, and ‘+’, etc. However, due to the increasing number of attacks, it is important to develop a new methodology to minimize the circuit area of the large number of regular expressions. Although the minimization of logic equations has been studied intensively in the area of computer-aided design (CAD), the minimization of multiple regular expressions has been largely neglected. In the first part of this dissertation, we present a novel sharing architecture allowing our algorithm to extract and share common sub-regular expressions. On the other hand, the memory architecture is also widely adopted by NIDS because of the advantages of easy re-configurability and scalability. Due to the increasing number of attacks, the required memory increases tremendously. Because the performance, cost, and power consumption of the memory architecture are directly related to the memory size, reducing the memory size has become imperative. In the second part of this dissertation, we propose a memory-efficient pattern-matching algorithm which can significantly reduce the memory requirement for the memory architecture. However, the memory architecture suffers the problem of memory explosion caused by certain types of regular expressions. It is well known that the number of states and transitions of a DFA can be exponential to the size of its corresponding regular expression. Implementing such regular expression pattern leads to extremely large memory requirements for storing the corresponding state transition table. In the third part of this dissertation, we propose a novel memory architecture which inserts marginal logic elements to improve the ability of traditional memory architecture to deal with complex regular expressions.

碩士
國立臺灣大學
電機工程學研究所
97
Regular expressions are very suitable to describe the features of network attacks in an Intrusion Detection System (IDS). NFA-based hardware architectures might cause two problems. 1. NFA-based architectures occupy too much hardware area.2. NFA-based architecture can not add new rule dynamically. This paper focus on these two issues .For the first one, we propose a string mechanism to improve the hardware area of NFA circuit. The experiment results of the proposed Regular Expression matching engine can scan the payload up to the rate of 2.4 Gbps, and have 23.51% space improvement (for the snort 2.8) For the second one, we also propose a matching architecture that can support dynamic updating of new rule sets.this comparator is going to support new rule in the future.

The rampant growth of the Internet has been coupled with an equivalent growth in cyber crime over the Internet. With our increased reliance on the Internet for commerce, social networking, information acquisition, and information exchange, intruders have found financial, political, and military motives for their actions. Network Intrusion Detection Systems (NIDSs) intercept the traffic at an organization’s periphery and try to detect intrusion attempts. Signature-based NIDSs compare the packet to a signature database consisting of known attacks and malicious packet fingerprints. The signatures use regular expressions to model these intrusion activities. This thesis presents a memory efficient pattern matching system for the class of regular expressions appearing frequently in the NIDS signatures. Proposed Cascaded Automata Architecture is based on two stage automata. The first stage recognizes the sub-strings and character classes present in the regular expression. The second stage consumes symbol generated by the first stage upon receiving input traffic symbols. The basic idea is to utilize the research done on string matching problem for regular expression pattern matching. We formally model the class of regular expressions mostly found in NIDS signatures. The challenges involved in using string matching algorithms for regular expression matching has been presented. We introduce length-bound transitions, counter-based states, and associated counter arrays in the second stage automata to address these challenges. The system uses length information along with counter arrays to keep track of overlapped sub-strings and character class based transition. We present efficient implementation techniques for counter arrays. The evaluation of the architecture on practical expressions from Snort rule set showed compression in number of states between 50% to 85%. Because of its smaller memory footprint, our solution is suitable for both software based implementations on network chips as well as FPGA based designs.

碩士
國立臺灣大學
電機工程學研究所
97
Network security has recently become an important issue. With the growing of high-speed networks, there is a growing demand for high performance network intrusion detection systems (NIDSs). Some NIDSs may use regular expressions to describe the signatures of security threats. Traditionally, we can build finite-state automaton corresponding to these regular expressions to identify the suspicious packets. Deterministic finite-state automata (DFA) and non-deterministic finite-state automata (NFA) are commonly used for regular expressions matching. The DFA does one-pass scanning with a larger storage cost, while the NFA does multi-pass scanning with a less storage cost. This thesis focuses on the state explosion problem existing in the common signature patterns of an NIDS, and how to reduce the state storage cost from the exponential complexity to linear complexity. Through the common string states sharing, we propose a two-phases matching architecture combining DFA and NFA. This architecture constructs circuit-based parallel matching with prefix sharing, while the remains state transition tables stored in off-chip memory spaces. Furthermore, with multiplexers, fully system matching patterns are dynamically reconfigurable. We also implement the two-phase matching engine in a field programmable gate array (FPGA). Through parallel state operations, the optimized architecture will process four characters at 230 MHz, resulting in a concurrent throughput of 1.84 Gbps. If the 4-character processing module is implemented, higher throughput can be achieved.

Graphics Processing Units (GPUs) have become a popular platform for executing general purpose (i.e., non-graphics) applications. To run efficiently on a GPU, applications must be parallelized into many threads, each of which performs the same task but operates on different data (i.e., data parallelism). Previous work has shown that some applications experience significant speedup when executed on a GPU instead of a CPU. The applications that benefit most tend to have certain characteristics such as high computational intensity, regular control-flow and memory access patterns, and little to no communication among threads. However, not all parallel applications have these characteristics. Applications with a more balanced compute to memory ratio, divergent control flow, irregular memory accesses, and/or frequent communication (i.e., not-so-regular applications) will not take full advantage of the GPU's resources, resulting in performance far short of what could be delivered. The goal of this dissertation is to enhance the GPU architecture to better handle not-so-regular parallelism. This is accomplished in two parts. First, I analyze a diverse set of data parallel applications that suffer from divergent control-flow and/or significant stall time due to memory. I propose two microarchitectural enhancements to the GPU called the Large Warp Microarchitecture and Two-Level Warp Scheduling to address these problems respectively. When combined, these mechanisms increase performance by 19% on average. Second, I examine one of the most important and fundamental applications in computing: database search. Database search is an excellent example of an application that is rich in parallelism, but rife with not-so-regular characteristics. I propose enhancements to the GPU architecture including new instructions that improve intra-warp thread communication and decision making, and also a row-buffer locality hint bit to better handle the irregular memory access patterns of index-based tree search. These proposals improve performance by 21% for full table scans, and 39% for index-based search. The result of this dissertation is an enhanced GPU architecture that better handles not-so-regular parallelism. This increases the scope of applications that run efficiently on the GPU, making it a more viable platform not only for current parallel workloads such as databases, but also for future and emerging parallel applications.
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碩士
國立臺灣大學
電機工程學研究所
96
A regular expression is powerful to describe signature patterns used in an Intrusion Detection System (IDS). This paper focuses on how to employ a pipeline architecture to NFA-based hardware implementations in order to increase the system performance. We propose a comparator that shares comparison operators including the ASCII decoder, the static pattern matching, and the char classes, and then we partition the comparator into two stages. As a result, we apply a three-stage pipeline to our Perl compatible regular expression pattern matching engine (PCRE engine) including a two-stage pipeline comparator and a one-stage NFA-based pattern recognizer. In addition, we can easily implement Caret meta-character (means the beginning of a string) when using the three-stage pipeline architecture. Finally, experimental results show that the proposed three-stage PCRE engine has a throughput of 2.4 Gbps as compared with the 1.8 Gpbs of the original PCRE engine in an Altera DE2 platform. This means that the proposed approach can have 30% performance increase in the current implementation with respect to the non-pipeline one.

Poaceae (or Gramineae) belong to the grass family and is one of the largest families among flowering plants on land. They include some of the most important cereal crops such as rice (Oryza sativa), barley (Hordeum vulgare), wheat (Triticum aestivum), maize (Zea mays), and sorghum (Sorghum bicolor). The characteristic bushy appearance of grass plants, including cereal crops, is formed by the activities of axillary meristems (AMs) generated in the leaf axil. These give rise to tillers from the basal nodes which recapitulate secondary growth axis and AMs are formed during vegetative development. On transition to flowering the apical meristem transforming to an inflorescence meristem (IM) which produces branches from axillary meristem. These IM gives rise to branches that ultimately bear florets. Vegetative branching/tillering determines plant biomass and influences the number of inflorescences per plant. While inflorescence branching determines the number of florets and hence seeds. Thus the overall activity of axillary meristems plays a key role in determining plant architecture during both vegetative and reproductive stages. In Arabidopsis, research on the plant specific transcription factor LEAFY (LFY) has pioneered our understanding of its regulatory functions during transition from vegetative to reproductive development and its role in specifying a floral meristem (FM) identity to the newly arising lateral meristems. In the FM LFY activates other FM genes and genes for floral organ patterning transcription factors. LFY is strongly expressed throughout the young floral meristems from the earliest stages of specification but is completely absent from the IM (Weigel et al., 1992). LFY expression can also be detected at low levels in the newly emerging leaf primordia during the vegetative phase, and these levels gradually increase until the floral transition (Blazquez et al., 1997; Hempel et al., 1997). In rice, the LFY ortholog-RFL/APO2 is expressed predominantly in very young branching panicles/ inflorescence meristems (Kyozuka et al., 1998; Prasad et al., 2003) while in the vegetative phase RFL is expressed at axils of leaves (Rao et al., 2008). In rice FMs expression is restricted to primordia of lodicules, stamens, carpels and ovules (Ikeda-Kawakatsu et al., 2012). Knockdown of RFL activity or loss of function mutants show delayed flowering and poor panicle branching with reduced number of florets and lower fertility (Rao et al., 2008, Ikeda-Kawakatsu et al., 2012). In some genotypes reduced vegetative axillary branching is also compromised (Rao et al., 2008). On the other hand RFL overexpression leads to the early flowering, attributing a role as an activator for the transition of vegetative meristems to inflorescence meristems (Rao et al., 2008). Thus, RFL shows a distinct developmental expression profile, has unique mutant phenotypes as compared to Arabidopsis LFY thus indicating a divergence in functions. We have used various functional genomics approaches to investigate regulatory networks controlledby RFL in the vegetative axillary meristems and in branching panicles with florets. These regulatory effects influence tillering and panicle branching, thus contributing to rice plant architecture. RFL functions in axillary meristem Vegetative AMs are secondary shoot meristems whose outgrowth determines plant architecture. In rice, AMs form tillers from basal nodes and mutants with altered tillering reveal that an interplay between transcription factors and the phytohormones - auxin, strigolactone underpins this process. We probed the relationship between RFL and other factors that control AM development. Our findings indicate that the derangements in AM development that occur on RFL knockdown arise from its early effects during specification of these meristems and also later effects during their outgrowth of AM as a tiller. Overall, the derailments of both steps of AM development lead to reduced tillering in plants with reduced RFL activity. Our studies on the gene expression status for key transcription factor genes, genes for strigolactone pathway and for auxin transporters gave an insight on the interplay between RFL, LAX1 and strigolactone signalling. Expression levels of LAX1 and CUC genes, that encode transcription factors with AM specification functions, were modulated upon RFL knockdown and on induction of RFL:ΔGR fusion protein. Thus our findings imply a likely, direct activating role for RFL in AM development that acts in part, through attaining appropriate LAX1 expression levels. Our data place meristem specification transcription factors LAX1 and CUC downstream to RFL. Arabidopsis LFY has a predominant role in conferring floral meristem (FM) identity (Weigel et al., 1992; Wagner, 2009; Irish, 2010; Moyroud et al., 2010). Its functions in axillary meristems were not known until recently. The latter functions were uncovered with the new LFYHARA allele with only partial defects in floral meristem identity (Chahtane et al., 2013). This mutant allele showed LFY can promote growth of vegetative AMs through its direct target REGULATOR OF AXILLARY MERISTEMS1 (RAX1), a R2R3 myb domain factor (Chahtane et al., 2013). These functions for Arabidopsis LFY and RAX1 in AMs development are parallel to and redundant with the pathway regulated by LATERAL SUPPRESSOR (LAS) and REGULATOR OF AXILLARY MERISTEM FORMATION1 (ROX1) (Yang et al., 2012; Greb et al., 2003). Interestingly, ROX1 is orthologous to rice LAX1 and our data show LAX1 expression levels in rice panicles and in culms with vegetative AMs is dependent on the expression status of RFL. Thus, we speculate that as compared to Arabidopsis AM development, in rice the LFY-dependent and LFY-independent regulatory pathways for AMs development are closely linked. In Arabidopsis, CUC2 and CUC3 genes in addition to their role in shoot meristem formation and organ separation play a role in AM development possibly by defining a boundary for the emerging AM. These functions for the Arabidopsis CUC genes are routed through their effects on LAS and also by mechanisms independent of LAS (Hibara et al., 2006; Raman et al., 2008). These data show modulation in RFL activity using the inducible RFL:∆GR protein leads to corresponding expression changes in CUC1/CUC2 and CUC3 genes expression in culm tissues. Thus, during rice AM development the meristem functions of RFL and CUC genes are related. Consequent to specification of AM the buds are kept dormant. Bud outgrowth is influenced by auxin and strigolactone signalling pathways. We investigated the transcript levels, in rice culms of genes involved in strigolactone biosynthesis and perception and found the strigolactone biosynthesis gene D10 and hormone perception gene are significantly upregulated in RFL knockdown plants. Further, bioassays were done for strigolactone levels, where we used arbuscular mycorrhiza colonization assay as an indicator for strigolactone levels in wild type plants and in RFL knockdown plants. These data validate higher strigolactone signalling in RFL knockdown plants. To probe the relationship between RFL and the strigolactone pathway we created plants knocked down for both RFL and D3. For comparison of the tillering phenotype of these double knockdown plants we created plants with D3 knockdown alone. We observed reduced tillering in plants with knockdown of both RFL and D3 as compared to the tiller number in plants with knockdown of D3 alone. These data suggest that RFL acts upstream to D3 of control bud outgrowth. As effects of strigolactones are influenced by auxin transport we studied expression of OsPIN1 and OsPIN3 in RFL knockdown plants. Their reduced expression was correlated with auxin deficiency phenotypes of the roots in RFL knockdown plants. These data in conjunction with observations on OsPIN3 the gene expression modulation by the induction of RFL:∆GR allow us to speculate on a relationship between RFL, auxin transport and strigolactones with regard to bud outgrowth. We propose that the low tillering phenotype of RFL knockdown plants arises from weakened PATS, consequent to low levels of PIN1 and PIN3, coupled with moderate increase in strigolactones. Taken together, our findings suggest functions for RFL during AM specification and tiller bud outgrowth. RFL functions in panicle branching Prior studies on phenotypes of RFL knockdown or loss of function mutants suggested roles for RFL in transition to flowering, inflorescence meristem development, emergence of lateral organs and floral organ development (Rao et al., 2008; Ikeda-Kawakatsu et al., 2012). It has been speculated that RFL acts to suppress the transition from inflorescence meristem to floral meristem through its interaction with APO1 (Ikeda-Kawakatsu et al., 2012). The downstream genes regulated by RFL in these processes have not yet been elucidated. To identify direct targets of RFL in developing panicles we adopted ChIP-seq coupled with studies on gene expression modulation on induction of RFL. For the former we raised polyclonal anti-sera and chromatin from branching panicles with few florets. For gene expression modulation studies, we created transgenics with a T-DNA construct where an artificial miRNA against 3’UTR specifically knocked endogenous RFL and the same T-DNA had a second expression cassette for generation of a chemically inducible RFL-ΔGR protein that is not targeted by amiR RFL. Our preliminary ChIP-seq data in the wild type panicle tissues hints that RFL binds to hundreds of loci across the genome thus providing first glimpse of direct targets of RFL in these tissues. These data, while preliminary, were manually curated to identify likely targets that function in flowering, we summarize here some key findings. Our study indicates a role of RFL in flowering transition by activating genes like OsSPL14 and OsPRMT6a. Recent studies indicate that OsSPL14 directly binds to the promoter of OsMADS56 or FTL1, the rice homologs of SOC1 and FT to promote flowering (Lu et al., 2013). As RFL knockdown plants show highly reduced expression of OsMADS50/SOC1 and for RFT1 (Rao et al., 2008), and we show here RFL can bind and induce OsSPL14 expression we suggest the RFL¬OsSPL14 module can contribute to the transition of the SAM to flowering. Further, OsSPL14 in the young panicles directly activates DENSE AND ERECT PANICLE1 (DEP1) to control panicle length (Lu et al., 2013). Thus RFL-OsSPL14-DEP1 module could explain the role of RFL in controlling panicle architecture (Rao et al., 2008; Ikeda-Kawakatsu et al., 2012). Thus RFL plays a role in floral transition and this function is conserved across several LFY homologs. Our data ChIP-seq in the wild type tissue and gene expression modulation studies in transgenics also give molecular evidences for the role of RFL in suppression of floral fate. The direct binding of RFL to OsMADS17, OsYABBY3, OsMADS58 and HD-ZIP-IV loci and the changes in their transcript levels on induction of RFL support this hypothesis. Once the transition from SAM to FM takes place, we speculate RFL represses the conversion of inflorescence branch meristems to floral fate by negatively regulating OsYABBY3, HD-ZIP class IV and OsMADS17 that can promote differentiation. These hypotheses indicate a diverged function for RFL in floral fate repression. Arabidopsis LFY is known to activate the expression of AGAMOUS (AG), whose orthologs in rice are OsMADS3 and OsMADS58. Our studies confirm conservation with regard to RFL binding to cis elements at OsMADS58 locus that is homologous to Arabidopsis AG. But importantly we show altered consequences of this binding on gene expression. We find RFL can suppress the expression of OsMADS58 which we speculate can promote a meristematic fate. Further, we also present the abnormal upregulation of floral organ fate genes on RFL downregulation. These data too indicate functions of RFL, are in part, distinct from the role of Arabidopsis LFY where it works in promoting floral meristem specification and development. These inferences are supported by our data that rice gene homologs for AP1, AP3 and SEP3 are not directly regulated by RFL, unlike their direct regulation by Arabidopsis LFY during flower development. We also report the expression levels of LAX1, FZP, OsIDS1 and OsMADS34 genes involved in meristem phase change and IM branching are RFL dependent. This is consistent with its role in the suppression of determinacy, thereby extending the IM activity for branch formation. But as yet we do not know if these effects are direct. Together, our data report direct targets of RFL that contribute to its functions in meristem regulation, flowering transition, and suppression of floral organ development. Overall, our preliminary data on RFL chromatin occupancy combined with our detailed studies on the modulation of gene expression provides evidence for targets and pathways unique to the rice RFL during inflorescence development. Comparative analysis of genes downstream to RFL in vegetative tillers Vs panicles Tillers and panicle branches arise from the axillary meristems at vegetative and reproductive stages, respectively, of a rice plant and overall contribute to the plant architecture. Some regulatory factors control branching in both these tissues - for example, MOC1 and LAX1. Mutants at these loci affect tillers and panicle branch development thus indicating common mechanisms control lateral branch primordia development (Li et al., 2003; Komatsu et al., 2003; Oikawa and Kyozuka, 2009). Knockdown of RFL activity or loss-of-function mutants cause significantly reduced panicle branching and in few instances, reduction in vegetative axillary branching (Rao et al., 2008; Ikeda- Kawakatsu et al., 2012). We took up the global expression profiling of RFL knockdown plants compared to wild type plants in the axillary meristem and branching panicle tissue. These data provide a useful list of potential targets of RFL in axillary meristem and branching panicle tissue. The comparative analysis of the genes affected in the two tissues indicates only a subset of genes is affected by RFL in both the vegetative axillary meristems and branching panicle. These genes include transcription factors (OsSPL14, Zn finger domain protein, and bHLH domain protein), hormone signalling molecules (GA2 ox9) and cell signalling (LRR protein) as a set of genes activated by RFL in both tissues. On the other hand, these comparative expression profiling studies also show distinct set of genes deregulated by RFL knockdown in these two tissues therefore implicating RFL functions have a tissue-specific context. The genes deregulated only in axillary meristem tissue only include D3- involved in the perception of strigolactone, OsMADS34 speculated to have a role in floral transition and RCN1 involved in transition to flowering. On the other hand, the genes – CUC1, OsMADS3, OsMADS58 involved in organ development and floral meristem determination were found to be deregulated only in panicle tissues of RFL knockdown plants. These data point towards presence of distinct mechanisms for the development of AMs as tillers versus the development of panicle axillary as rachis branches. Overall, these data implicate genes involved in transition to flowering, axillary meristem development and floral meristem development are controlled by RFL in different meristems to thereby control plant architecture and transition to flowering.

Tese de Doutoramento em Informática - Área de Especialização em Tecnologia da Programação
Nas últimas décadas assistimos a uma mudança paradigmática na utilização das tecnologias da informação e comunicação que potenciaram a criação de uma sociedade de informação e conhecimento, abrangendo e influenciando praticamente todos os domínios da sociedade. O tradicional uso das tecnologias de informação e comunicação no auxílio à execução de actividades de âmbito profissional, numa interacção restrita entre homem e máquina, deu lugar a ambientes virtuais de interacção social, onde pessoas interagem com pessoas, criando relações estreitas e realizando as mais diversas actividades. O crescimento da Internet e das tecnologias associadas fomentou o crescimento e difusão dos ambientes virtuais de interacção social, tornando-os acessíveis `a grande maioria da população. Actualmente estes ambientes estão espalhados por toda a Internet e abrangem um vasto leque de áreas, da educação ao entretenimento. Contudo, a imaturidade associada ao rápido crescimento destes ambientes levou a que fossem descurados factores que actualmente condicionam a interacção social, nomeadamente ao nível da sua coordenação e regulação. A regulação e coordenação da interacção social nos ambientes virtuais pode constituir uma solução possível para organização da actual interacção “ad hoc”, que persiste nestes ambientes, contribuindo inerentemente para o aumento da sua credibilidade. Nesta tese é proposto um modelo para a regulação da interacção social e controlo dos ambientes virtuais: o modelo dos Teatros Sociais. O conceito de Teatro Social resulta da aplicação da metáfora teatral a ambientes virtuais de interacção social destinados a reproduzir virtualmente situações do quotidiano. Dentro destes ambientes os utilizadores tornam-se actores, desempenhando papéis bem definidos, num cenário virtual de interacção conhecido e, idealmente, estabelecido de forma comum. O modelo dos Teatros Sociais é implementado por uma arquitectura de software dinâmica que permite a criação de ambientes de interacção regulados e assegura a adaptação dos conteúdos da interacção aos canais de comunicação dos utilizadores, embora condicionados pelas restrições tecnológicas dos dispositivos usados na interacção. Para a validação do modelo e da arquitectura de suporte foram criados dois casos de estudo que suportaram um conjunto de experiências realizadas com utilizadores reais.
Throughout the last decades we have observed a paradigmatic change on the use of information and communication technologies, which have powered the creation of an information and knowledge society, covering and influencing almost every domain of society. The traditional usage of information and communication technologies as an aid to the execution of professional activities, in a restrictive man-machine interaction, has given way to social interaction virtual environments where people interact with each other, creating close relationships and doing the most different activities. The growth of the Internet and its associated technologies encouraged the expansion and diffusion of virtual environments where social interaction takes place, allowing easy access to the great majority of population. Nowadays these environments are spread all over the Internet and cover a vast rage of areas, from education to entertainment. However, immaturity together with the fast growth of these environments led to the disregard of factors, which condition interaction today, namely the coordination and regulation of interaction activities. The regulation and coordination of interaction in social, virtual interaction environments may be a possible solution to the organisation of today’s “ad hoc” interaction, which persists in these environments, inherently contributing to the increase of its credibility. In this Thesis a model to regulate social interaction and control virtual environments is proposed: the Social Theatres model. Social Theatres stand for the application of the theatrical metaphor to social virtual environments, intended to virtually reproduce some of the common and useful people’s interaction contexts. Inside these environments, users become actors, playing previously well defined roles within a well known, commonly established virtual interaction scenario. The Social Theatres model is implemented by a dynamic software architecture that allows the creation of regulated interaction environments and guarantees adaptation to users’ devices and input channels. In order to validate the model and the supporting architecture two case studies were created, which supported a group of experiments carried out with real users.
Fundação para a Ciência e Tecnologia (FCT) - no âmbito do III Quadro Comunitário de Apoio, comparticipado pelo Fundo Social Europeu
Ministério da Ciência e do Ensino Superior (MCES) - Bolsa de Doutoramento com a referência SFRH/BD/10304/2002

This thesis presents the design, construction, and control of a two-wheeled inverted pendulum (TWIP) robotic walker prototype for assisting mobility-impaired users with balance and fall prevention. A conceptual model of the robotic walker is developed and used to illustrate the purpose of this study. A linearized mathematical model of the two-wheeled system is derived using Newtonian mechanics. A control strategy consisting of a decoupled LQR controller and three state variable controllers is developed to stabilize the platform and regulate its behavior with robust disturbance rejection performance. Simulation results reveal that the LQR controller is capable of stabilizing the platform and rejecting external disturbances while the state variable controllers simultaneously regulate the system’s position with smooth and minimum jerk control. A prototype for the two-wheeled system is fabricated and assembled followed by the implementation and tuning of the control algorithms responsible for stabilizing the prototype and regulating its position with optimal performance. Several experiments are conducted, confirming the ability of the decoupled LQR controller to robustly balance the platform while the state variable controllers regulate the platform’s position with smooth and minimum jerk control.