Relevant bibliographies by topics / Regular architecture

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Regular architecture'

Author: Grafiati
Published: 28 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Regular architecture"

1

Trobec, Roman, Janez Korenini, and Ludvik Gyergyek. "A regular WSI-node architecture." Microprocessing and Microprogramming 21, no. 1-5 (August 1987): 75–81. http://dx.doi.org/10.1016/0165-6074(87)90021-4.

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Antonov, Vadim G. "A regular architecture for operating system." ACM SIGOPS Operating Systems Review 24, no. 3 (July 1990): 22–39. http://dx.doi.org/10.1145/382244.382830.

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Parravicini, Daniele, Davide Conficconi, Emanuele Del Sozzo, Christian Pilato, and Marco D. Santambrogio. "CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–24. http://dx.doi.org/10.1145/3476982.

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Regular Expression (RE) matching is a computational kernel used in several applications. Since RE complexity and data volumes are steadily increasing, hardware acceleration is gaining attention also for this problem. Existing approaches have limited flexibility as they require a different implementation for each RE. On the other hand, it is complex to map efficient RE representations like non-deterministic finite-state automata onto software-programmable engines or parallel architectures. In this work, we present CICERO , an end-to-end framework composed of a domain-specific architecture and a companion compilation framework for RE matching. Our solution is suitable for many applications, such as genomics/proteomics and natural language processing. CICERO aims at exploiting the intrinsic parallelism of non-deterministic representations of the REs. CICERO can trade-off accelerators’ efficiency and processors’ flexibility thanks to its programmable architecture and the compilation framework. We implemented CICERO prototypes on embedded FPGA achieving up to 28.6× and 20.8× more energy efficiency than embedded and mainstream processors, respectively. Since it is a programmable architecture, it can be implemented as a custom ASIC that is orders of magnitude more energy-efficient than mainstream processors.
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Korotkiy, V. A., and E. A. Usmanova. "Regular linear surfaces in architecture and construction." Journal of Physics: Conference Series 1441 (January 2020): 012065. http://dx.doi.org/10.1088/1742-6596/1441/1/012065.

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Polimeni, Beniamino. "PRODUCING DESIGN OBJECTS FROM REGULAR POLYHEDRA: A PRACTICAL APPROACH." Boletim da Aproged, no. 34 (December 2018): 49–55. http://dx.doi.org/10.24840/2184-4933_2018-0034_0007.

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In the last few years, digital modelling techniques have played a major role in architecture and design, influencing, at the same time, the creative process and the fabrication of objects. This revolution has produced a new productive generation of architects and designers focused on the expanding possibilities of material and formal production, reinforcing the idea of architecture as an interaction between art and artisanship. This original perspective inspires this paper, which illustrates the contemporary scenario and provides some practical guidance about tools and technologies the designers most often use for creating geometric sculptures with 3D printing. Creative possibilities of topological mesh modelling are used to generate complex geometries from regular polyhedra. This process explores how combining different geometric operations can activate architectural inquiry and generate fascinating shapes with creative flexibility.
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DEPRETTERE, ED F., PETER HELD, and PAUL WIELAGE. "MODEL AND METHODS FOR REGULAR ARRAY DESIGN." International Journal of High Speed Electronics and Systems 04, no. 02 (June 1993): 133–201. http://dx.doi.org/10.1142/s012915649300008x.

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We present a unified framework for the transformation of algorithms to architectures in the domains of high speed signal and algebraic processing. The framework starts from algorithmic specifications in a language suited for numerical analysis (such as Matlab), transforms the high level description into hierarchical and structured data flow dependence graphs, allows the designer to manipulate the graphs, to merge them, abstract them, regularize them, cluster and partition them etc… until the description of an architecture which can represent the hardware in a precise manner is obtained. A generic model for hierarchical, parametrized descriptions assures a consistent design methodology throughout. In the process, we not only generate attractive parallel architectures based on a fixed array of processing elements, but also their control and the program that has to be executed by the host processor. Because of the parametrization, the designs are "generic" and hence reusable, but they are restricted to cases where the parameters are known at "generation time".
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Lalvani, Haresh. "Higher Dimensional Periodic Table Of Regular And Semi-Regular Polytopes." International Journal of Space Structures 11, no. 1-2 (April 1996): 155–71. http://dx.doi.org/10.1177/026635119601-222.

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This paper presents a higher-dimensional periodic table of regular and semi-regular n-dimensional polytopes. For regular n-dimensional polytopes, designated by their Schlafli symbol {p,q,r,…u,v,w}, the table is an (n-1)-dimensional hypercubic lattice in which each polytope occupies a different vertex of the lattice. The values of p,q,r,…u,v,w also establish the corresponding n-dimensional Cartesian co-ordinates (p,q,r,…u,v,w) of their respective positions in the hypercubic lattice. The table is exhaustive and includes all known regular polytopes in Euclidean, spherical and hyperbolic spaces, in addition to others candidate polytopes which do not appear in the literature. For n-dimensional semi-regular polytopes, each vertex of this hypercubic lattice branches into analogous n-dimensional cubes, where each n-cube encompasses a family with a distinct semi-regular polytope occupying each vertex of each n-cube. The semi-regular polytopes are obtained by varying the location of a vertex within the fundamental region of the polytope. Continuous transformations within each family are a natural fallout of this variable vertex location. Extensions of this method to less regular space structures and to derivation of architectural form are in progress and provide a way to develop an integrated index for space structures. Besides the economy in computational processing of space structures, integrated indices based on unified morphologies are essential for establishing a meta-structural knowledge base for architecture.
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Badran, Tamer, Hany Ahmad, and Mohamad Abdel-Gawad. "A reconfigurable multi-byte regular-expression matching architecture." International Conference on Electrical Engineering 6, no. 6 (May 1, 2008): 1–10. http://dx.doi.org/10.21608/iceeng.2008.34330.

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Hawkes. "A Regular Fault-Tolerant Architecture for Interconnection Networks." IEEE Transactions on Computers C-34, no. 7 (July 1985): 677–80. http://dx.doi.org/10.1109/tc.1985.1676608.

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Mangard, S., M. Aigner, and S. Dominikus. "A highly regular and scalable aes hardware architecture." IEEE Transactions on Computers 52, no. 4 (April 2003): 483–91. http://dx.doi.org/10.1109/tc.2003.1190589.

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Dissertations / Theses on the topic "Regular architecture"

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DeBrunner, Linda Sumners. "Modeling reconfiguration algorithms for regular architecture." Diss., Virginia Tech, 1991. http://hdl.handle.net/10919/29254.

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Three models are proposed to evaluate and design distributed reconfigurable systems for fault tolerant, highly reliable applications. These models serve as valuable tools for developing fault tolerant systems. In each model, cells work together in parallel to change the global structure through a series of separate actions. In the Local Supervisor Model (LSM), selected cells guide the reconfiguration process. In the Tessellation Automata Model (TAM), each cell determines its next state based on its state and its neighbors' states, and communicates its state information to its neighbors. In the Interconnected Finite State Machine Model (IFS:MM:), each cell determines its next state and outputs based on its state and its inputs. The hierarchical nature of the TAM and IFSMM provides advantages in evaluating, comparing, and designing systems. The use of each of these models in describing systems is demonstrated. The IFSMM: is emphasized since it is the most versatile of the three models. The IFSMM: is used to identify algorithm weaknesses and improvements, compare existing algorithms, and develop a novel design for a reconfigurable hypercube.
Ph. D.
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2

Haddad, Nicholas. "Transmission of digital images using data-flow architecture." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1184007755.

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Tao, Zhixiang. "Theoretical and experimental investigations of large amplitude ship motions and loads in regular head seas." Thesis, University of Glasgow, 1996. http://theses.gla.ac.uk/6900/.

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The aim of this research is to develop computational tools to predict the large amplitude motions and loads on ships travelling with forward speed in waves. An experimental research programme was completed to validate the non-linear prediction method. In this thesis, the results of theoretical and experimental investigations to predict the non-linear ship motions, slamming pressures and bending moments in regular head seas are presented. The ship hull is considered to be a Timoshenko beam, where the vibratory elastic response of the ship is calculated by the modal superposition method with the solution represented in terms of a series of normal modes. It is assumed that the mode shapes and natural frequencies can be determined by a separate structural analysis where this modal information is appropriate to the vessel in the equilibrium reference condition when floating in calm water. The global dynamic shear force and bending moment values are predicted using two different methods:The first method developed is based on the elastic vibratory response due to the total hydrodynamic force; The other is based on the rigid body response due to the linear force superimposed with the elastic response due to the impact forces. The results by the elastic vibratory response due to the total hydrodynamic force (method 1) have a good agreement with the experimental results and these are much better than the results by the rigid body response superimposed with the elastic response (method 2). The non-linear effects due to the change of the hydrodynamic coefficients and the non-linear restoring force should be considered in the ship motion and load predictions. The nonlinearity of ship motions as well as a significant nonlinearity between the hogging and sagging wave and global bending moments are shown in the results obtained from the non-linear theoretical predictions and the experimental data. The non-linear ship motions and sea loads, predicted by the practical computational tools, newly developed in this thesis, can be used to further ship structural strength analysis and guide ship hull design.
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Poláková, Simona. "Příprava perovskitových solárních článků se standardní n-i-p strukturou a jejich optimalizace." Master's thesis, Vysoké učení technické v Brně. Fakulta chemická, 2021. http://www.nusl.cz/ntk/nusl-444539.

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The diploma thesis deals with the study of perovskite solar cells with a regular n-i-p architecture. The theoretical part of this work is mainly focused on the stability of perovskite solar cells, i.e. thermal stability and the influence of UV radiation on final perovskite solar cell stability. Furthermore, the deposition methods, the architecture of solar cells and the materials used for the preparation of electron and hole transport layers were described in more detail. The experimental part deals with the optimization of the preparation of perovskite solar cells (especially in terms of resulting photovoltaic conversion efficiency), with a description of the structure preparation process of the final photovoltaic cell and the interpretation of the measured results.
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Nayak, Amiyaranjan Carleton University Dissertation Engineering Electrical. "On reconfigurability of some regular architectures." Ottawa, 1991.

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Lai, Pengjie. "Improvement of Sigma Voltage Regulator - A New Power Architecture." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/31412.

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With lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard. Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design. To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called â Sigmaâ architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept. The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor. This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a â non-obstacleâ path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective. In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for futureâ s lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved.
Master of Science
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Masson, Juliette. "Geoffroi du Loroux et l'architecture religieuse en Aquitaine au XIIème siècle." Phd thesis, Université Michel de Montaigne - Bordeaux III, 2012. http://tel.archives-ouvertes.fr/tel-00735961.

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Cette étude menée sur les fondations canoniales de Geoffroy du Loroux, archevêque de Bordeaux de 1136 à 1158, a pour objectif de montrer une implication du prélat dans le parti architectural de ses fondations qui présentent a priori une similitude en plan et en élévation. Grand artisan de la réforme grégorienne en Aquitaine, l'action de Geoffroy du Loroux est bien cernée par sa collection de sermons mais ses fondations n'ont jamais fait l'objet d'une étude de synthèse. Chacune des quatre fondations attribuées à l'archevêque, l'Isle et Pleine-Selve (Gironde), Sablonceaux (Charente-Maritime) et Fontaine-le-Comte (Vienne), a été soumise à une analyse architecturale approfondie, complétée d'une étude métrologique, afin d'appréhender chaque édifice dans sa globalité. Les éléments conservés du XIIe siècle ont ensuite été soumis à une étude comparative. En outre, une discussion est menée autour de l'attribution à Geoffroy du Loroux de la reconstruction de la cathédrale de Bordeaux dès le XIIe siècle.Il s'avère que les fondations liées à Geoffroy du Loroux adoptent un parti architectural stéréotypé et d'une esthétique ostensiblement austère. L'archevêque apparaît comme un prélat soucieux de laisser à ses successeurs des modèles pour transmettre le message de la réforme grégorienne, tant au travers de ses sermons qu'au niveau de ses fondations. Ces dernières se devaient d'être représentatives d'une grande humilité et du retour à la rigueur prôné par la réforme, en totale opposition avec le faste clunisien. Ce travail amène à s'interroger sur le rôle des collégiales qui, utilisées tel un outil de diffusion de la réforme, ont pu freiner l'implantation de Cluny dans le Bordelais.
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Dzimitrowicz, Natasha. "Investigating proteins that regulate the architecture of the plant endoplasmic reticulum." Thesis, University of Warwick, 2018. http://wrap.warwick.ac.uk/100895/.

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The plant endoplasmic reticulum (ER), a highly dynamic membrane-bound organelle, is not only the site of secretory protein production and lipid synthesis, but also responsible for calcium storage. It is currently hypothesised that the shape of the ER network relates to these functions. The sheets, large at areas of network are proposed to be the sites of protein production and the tubules, thin, highly-mobile and interconnected, the regions of lipid production and calcium storage. The reticulon protein family has been shown to bend the ER lipid bilayer to form tubules and the edges of sheets. Identifying protein interactors to reticulons may help to understand how the morphology of the ER is controlled or in uenced. Mass spectrometry and co-immunoprecipitation techniques were used to identify protein interactors to the Arabidopsis thaliana seed-specific reticulon, RTN13. Five non-reticulon proteins were found to interact with RTN13 in developing A. thaliana seed; GTP-binding protein 2, lysophospholipase 1, NADH: Cytochrome B5 Reductase 1, sterol methyltransferase 2 and synaptotagmin a. Microscopy analysis of the ER in over-expression lines and T-DNA insertions lines for each putative interactor, showed that only sterol methyltransferase 2 and synaptotagmin a influenced the ER morphology. Additionally, the morphology of the ER was analysed during seed development and germination through confocal microscopy. An image analysis macro was used to determine the percentage of sheet morphology in the network. Significant changes in the amount of sheet morphology were recorded in the ER of cotyledon cells during seed development and over the first six days of germination. Wild type embryos were also compared to mutants known to have altered ER morphology. The analysis suggested that the amount of sheet morphology is maximal at times of maximum protein production, highlighting the link between ER form and function.
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Gishto, Arsela. "SCAFFOLD COMPOSITION AND ARCHITECTURE CRITICALLY REGULATE EXTRACELLULAR MATRIX SYNTHESIS BY CARDIOMYOCYTES." Cleveland State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=csu1386941945.

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Sun, Julu. "Investigation of Alternative Power Architectures for CPU Voltage Regulators." Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/30119.

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Since future microprocessors will have higher current in accordance with Mooreâ s law, there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only for easy thermal management, but also for saving on electricity costs for data centers, or battery life extension for laptop computers. At the same time, high power density is required due to the increased power of the microprocessors. This is especially true for data centers, since more microprocessors are required within a given space (per rack). High power density is also required for laptop computers to reduce the size and the weight. To improve power density, a high frequency is required to shrink the size of the output inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz. Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power density is very low. To attain high efficiency and high power density at the same time, two-stage power architecture was proposed. The concept is â Divide and Conquerâ . A single-stage VR is split into two stages to get better performance. The second stage has about 5V-6V input voltage; thus the duty cycle can be extended and the switching losses are greatly reduced compared with a single-stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high frequencies. The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is required for the first stage since it is in series with the second stage. Previous first stage which is a buck converter has good efficiency but bulky size due to low frequency operation. Another problem with using a buck converter is that light-load efficiency of the first stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does not require voltage regulation, the sweet point for the voltage divider can be determined and high efficiency can be achieved. At the same time, since there are no magnetic components for the switched-capacitor voltage divider, high power density can be achieved. By very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can be as high as 99% by reducing the switching frequency at light load. As for the second stage, different low-voltage devices are evaluated, and the best device combinations are found for high-frequency operation. It has been demonstrated that 91% efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a 1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage respectively. Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other systems. In this dissertation, the two-stage power architecture is applied to two different applications: laptop computers and high-end server microprocessors. The common characteristics of the two applications are their thermal design power (TDP) requirement. Thus the first stage can be designed with much lower power than the maximum system power. It has been demonstrated that the two-stage power architecture can achieve either higher efficiency or higher power density and a lower cost when compared with the single-stage VR. To get higher efficiency, a parallel two-stage power architecture, named sigma architecture, is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the output power, while using a low-power buck converter to achieve voltage regulation. Both the DCX converter and the buck converter can achieve around 90% efficiency when used in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can also be applied to low-power point of load (POL) applications to reduce the magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly compared.
Ph. D.
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Books on the topic "Regular architecture"

1

F, Stout Quentin, ed. Parallel algorithms for regular architectures: Meshes and pyramids. Cambridge, Mass: MIT Press, 1996.

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Contento, José Javier Barranquero. Conventos de la provincia de Ciudad Real: Devoción y clero regular. Ciudad Real: Diputación Provincial de Ciudad Real, Área de Cultura, 2003.

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O'Keeffe, Tadhg. An Anglo-Norman monastery: Bridgetown Priory and the architecture of the Augustinian canons regular in Ireland. Cork: Cork County Council, 1999.

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Aliata, Fernando. La ciudad regular: Arquitectura, programas e instituciones en el Buenos Aires posrevolucionario, 1821-1835. Bernal: Universidad Nacional de Quilmes, 2006.

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Ana Palmira Bittencourt Santos Casimiro. Mentalidade e estética na Bahia colonial: A venerável Ordem Terceira de São Francisco de Assis da Bahia e o frontispício da sua igreja. Salvador: Secretaria da Cultura e Turismo, Fundação Cultural do Estado da Bahia, 1996.

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Jones, Mark T. A language comparison for scientific computing on MIMD architectures. Hampton, Va: ICASE, 1989.

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Alvarez, Vidal de la Madrid. La arquitectura de la ilustración en Asturias: Manuel Reguera, 1731-1798. Oviedo: Real Instituto de Estudios Asturianos, 1995.

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Salvestrini, Francesco, ed. La Basilica di San Miniato al Monte di Firenze (1018-2018). Florence: Firenze University Press, 2021. http://dx.doi.org/10.36253/978-88-5518-295-9.

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Between the 11th and the 20th century, the monastery of San Miniato al Monte in Florence played a leading role in the religious and cultural life of the city. The volume analyses for the first time the historical and documentary evolution of this regular institute, famous almost only from the architectural and artistic points of view. The book focuses the period of the bishop’s patronage in the 11th century, when the monastery and some of its members emerged in the context of the ecclesiastical reform, and continues with the study of the the Olivetan monks community, during the 14th-16th centuries, to arrive at the important structural and functional, but also semantic, transformations of the monument between the 18th century and the contemporary times.
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La Ciudad Regular. Universidad Nacional de Quilmes, 2006.

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Miller, Russ, and Quentin F. Stout. Parallel Algorithms for Regular Architectures: Meshes and Pyramids. MIT Press, 1996.

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Book chapters on the topic "Regular architecture"

1

Aiken, Alexander, and Brian R. Murphy. "Implementing regular tree expressions." In Functional Programming Languages and Computer Architecture, 427–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/3540543961_21.

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Zawidzki, Machi. "Polarized Film Shading System in Regular Grids (PFSS)." In Discrete Optimization in Architecture, 63–75. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1391-1_3.

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Sheeran, Mary. "Designing regular array architectures using higher order functions." In Functional Programming Languages and Computer Architecture, 220–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 1985. http://dx.doi.org/10.1007/3-540-15975-4_39.

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Atencio, M. A., C. de Rosa, A. Esteves, M. Basso, and J. L. Cortegoso. "Solar Potential of Regular Gridiron Urban Environments in Western Argentina." In 1989 2nd European Conference on Architecture, 286–89. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-017-0556-1_82.

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Paolieri, Marco, Ivano Bonesana, and Marco Domenico Santambrogio. "ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching." In VLSI-SoC: Advanced Topics on Systems on a Chip, 1–20. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-89558-1_6.

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Xu, Chengcheng, Baokang Zhao, Shuhui Chen, and Jinshu Su. "A Novel Hybrid Architecture for High Speed Regular Expression Matching." In Communications in Computer and Information Science, 164–74. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7850-7_15.

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O'Keeffe, Tadhg. "Augustinian Regular Canons in Twelfth- and Thirteenth-Century Ireland: History, Architecture, and Identity." In Medieval Church Studies, 469–84. Turnhout: Brepols Publishers, 2011. http://dx.doi.org/10.1484/m.mcs-eb.5.100396.

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Baud, Anne, and Christian Sapin. "L’abbaye de Cluny, entre architecture et liturgie au xie siècle." In Consuetudines et Regulae, 117–35. Turnhout: Brepols Publishers, 2014. http://dx.doi.org/10.1484/m.dm-eb.5.102137.

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Becker, Bernd, and Uwe Sparmann. "Regular structures and testing: RCC-adders." In VLSI Algorithms and Architectures, 288–300. New York, NY: Springer New York, 1988. http://dx.doi.org/10.1007/bfb0040396.

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Bonde, Sheila, and Clark Maines. "Consuetudines in Context : Change and Continuity in the Customs and Architecture of Augustinian Saint-Jean-des-Vignes, Soissons, 1098-1783." In Consuetudines et Regulae, 175–267. Turnhout: Brepols Publishers, 2014. http://dx.doi.org/10.1484/m.dm-eb.5.102139.

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Conference papers on the topic "Regular architecture"

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Manjunathaiah, M. "Hierarchical Composite Regular Parallel Architecture." In 2009 Eighth International Symposium on Parallel and Distributed Computing (ISPDC). IEEE, 2009. http://dx.doi.org/10.1109/ispdc.2009.41.

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Divyasree, J., H. Rajashekar, and Kuruvilla Varghese. "Dynamically reconfigurable regular expression matching architecture." In 2008 International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2008. http://dx.doi.org/10.1109/asap.2008.4580165.

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Comodi, Alessandro, Davide Conficconi, Alberto Scolari, and Marco D. Santambrogio. "TiReX: Tiled Regular eXpression Matching Architecture." In 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 2018. http://dx.doi.org/10.1109/ipdpsw.2018.00028.

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Kheterpal, V., A. J. Strojwas, and L. Pileggi. "Routing architecture exploration for regular fabrics." In the 41st annual conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/996566.996625.

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Lin, Cheng-Hung. "Hybrid memory architecture for regular expression matching." In 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2009. http://dx.doi.org/10.1109/mwscas.2009.5235940.

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Yun, SangKyun. "Efficient Failure Processing Architecture in Regular Expression Processor." In Third International Conference of Advanced Computer Science & Information Technology. Academy & Industry Research Collaboration Center (AIRCC), 2015. http://dx.doi.org/10.5121/csit.2015.51201.

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Kořenek, Jan, and Vlastimil Košař. "NFA split architecture for fast regular expression matching." In the 6th ACM/IEEE Symposium. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1872007.1872024.

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Wang, Hao, Shi Pu, Gabriel Knezek, and Jyh-Charn Liu. "A modular NFA architecture for regular expression matching." In the 18th annual ACM/SIGDA international symposium. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1723112.1723149.

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Anggraeni, Silvia, Fawnizu Azmadi Hussin, and Varun Jeoti. "High rate (3, k) regular LDPC encoder architecture." In 2011 National Postgraduate Conference (NPC). IEEE, 2011. http://dx.doi.org/10.1109/natpc.2011.6136390.

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Teodorov, Ciprian, Pritish Narayanan, Loic Lagadec, and Catherine Dezan. "Regular 2D NASIC-based architecture and design space exploration." In 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, 2011. http://dx.doi.org/10.1109/nanoarch.2011.5941486.

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