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Academic literature on the topic 'Reference spurs'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Reference spurs"

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Hirst, Peter M., and David C. Ferree. "Rootstock Effects on the Flowering of `Delicious' Apple. II. Nutritional Effects with Specific Reference to Phosphorus." Journal of the American Society for Horticultural Science 120, no. 6 (November 1995): 1018–24. http://dx.doi.org/10.21273/jashs.120.6.1018.

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In each of 3 years, vegetative spurs were sampled from l-year-old wood of `Starkspur Supreme Delicious' apple trees (Malus domestica Borkh.) growing on B.9, M.26 EMLA, M.7 EMLA, P.18, and seedling rootstocks. Mineral concentrations of spur leaves and bud apical meristems were determined, and related to spur bud development. The spur leaf P concentration decreased during the growing season each year, hut was unaffected by rootstock. Spur leaves of trees on B.9 rootstock had 30% higher Ca concentrations than trees on M.26 EMLA or seedling rootstocks. In each year, trees growing on M.26 EMLA rootstocks had the highest leaf Mg concentrations. Mineral concentrations were generally unrelated to spur leaf number, leaf area, leaf dry weight, or specific leaf weight. Phosphorus concentrations in spur bud apical meristems declined during two of the three growing seasons of the study and were unaffected by rootstock. Bud P concentration was weakly negatively related to bud diameter and bud appendage number in one year of the study. More vigorous spurs (as indicated by higher spur leaf number, leaf area, and leaf dry weight) had higher bud K levels during each year. No relationships between bud development and either spur leaf mineral concentration or bud apical meristem mineral levels were evident, suggesting that a direct role of mineral nutrition influenced by rootstock at the site of flower formation was unlikely.
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Solomko, V. A., and P. Weger. "Monolithically integrated frequency synthesiser with distributed reference spurs." IET Circuits, Devices & Systems 2, no. 6 (2008): 527. http://dx.doi.org/10.1049/iet-cds:20080059.

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Zahnreich, Sebastian, Hans-Peter Rösler, Carina Schwanbeck, Heiko Karle, and Heinz Schmidberger. "Radiation-induced DNA double-strand breaks in peripheral leukocytes and therapeutic response of heel spur patients treated by orthovoltage X-rays or a linear accelerator." Strahlentherapie und Onkologie 196, no. 12 (July 10, 2020): 1116–27. http://dx.doi.org/10.1007/s00066-020-01662-4.

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Abstract Purpose Biodosimetric assessment and comparison of radiation-induced deoxyribonucleic acid (DNA) double-strand breaks (DSBs) by γH2AX immunostaining in peripheral leukocytes of patients with painful heel spur after radiation therapy (RT) with orthovoltage X‑rays or a 6-MV linear accelerator (linac). The treatment response for each RT technique was monitored as a secondary endpoint. Patients and methods 22 patients were treated either with 140-kV orthovoltage X‑rays (n = 11) or a 6-MV linac (n = 11) with two weekly fractions of 0.5 Gy for 3 weeks. In both scenarios, the dose was prescribed to the International Commission on Radiation Units and Measurements (ICRU) dose reference point. Blood samples were obtained before and 30 min after the first RT session. γH2AX foci were quantified by immunofluorescence microscopy to assess the yield of DSBs at the basal level and after radiation exposure ex vivo or in vivo. The treatment response was assessed before and 3 months after RT using a five-level functional calcaneodynia score. Results RT for painful heel spurs induced a very mild but significant increase of γH2AX foci in patients’ leukocytes. No difference between the RT techniques was observed. High and comparable therapeutic responses were documented for both treatment modalities. This trial was terminated preliminarily after an interim analysis (22 patients randomized). Conclusion Low-dose RT for painful heel spurs with orthovoltage X‑rays or a 6-MV linac is an effective treatment option associated with a very low and comparable radiation burden to the patient, as confirmed by biodosimetric measurements.
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Nouri, Mohamed T., Daniel P. Lawrence, Mohammad A. Yaghmour, Themis J. Michailides, and Florent P. Trouillas. "Neoscytalidium dimidiatum Causing Canker, Shoot Blight and Fruit Rot of Almond in California." Plant Disease 102, no. 8 (August 2018): 1638–47. http://dx.doi.org/10.1094/pdis-12-17-1967-re.

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Almond trees with trunk and branch cankers were observed in several orchards across almond-producing counties in California. Symptoms of cankers included bark lesions, discoloration of xylem tissues, longitudinal wood necrosis, and extensive gumming. Spur and shoot blight associated with rotted fruit were detected in two orchards in Kern County. The fungus Neoscytalidium dimidiatum was consistently recovered from the various cankers, infected fruit, and blighted shoots and its identity was confirmed based on phylogenetic and morphological studies. Phylogenetic analyses of the internal transcribed spacer, translation elongation factor 1-α, and β-tubulin genes comparing 47 strains from California with reference specimens within the family Botryosphaeriaceae and coupled with detailed morphological observations validated the identity of the pathogenic fungus. Pathogenicity tests conducted in the field using 1- to 2-year-old branches inoculated with mycelium plugs or conidial suspensions and attached fruit inoculated with conidial suspensions fulfilled Koch’s postulates. N. dimidiatum appeared highly virulent in almond-producing cankers of up to 22 cm in length within 4 weeks using mycelium plug inoculations as well as severe fruit rot combined with spur blight on the fruit-bearing spurs. This study reports, for the first time, the fungus N. dimidiatum as a pathogen of almond in California causing canker, shoot blight, and fruit rot. Disease symptoms are described and illustrated.
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Herzel, Frank, and Dietmar Kissinger. "Design and layout strategies for integrated frequency synthesizers with high spectral purity." International Journal of Microwave and Wireless Technologies 9, no. 9 (June 5, 2017): 1791–97. http://dx.doi.org/10.1017/s1759078717000654.

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Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.
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Blakey, Gregory L., Cindy B. McCloskey, Joel M. Guthridge, Christopher L. Williams, Rufei Lu, Jon T. Hayes, Kendal G. Pinkston, and Michael L. Talbert. "COVID-19 Pandemic Spurs Evolution of an Academic Pathology Department and Laboratory." Academic Pathology 8 (January 1, 2021): 237428952110370. http://dx.doi.org/10.1177/23742895211037029.

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The COVID-19 pandemic has caused much suffering through disease and death, disruption of daily life, and economic havoc. Global health infrastructure has been challenged, in some cases failing. In the United States, the inability of laboratories to provide adequate testing for the causative pathogen, severe acute respiratory syndrome coronavirus 2, has been the subject of negative press and national debate. Even so, these challenges have prompted pathology practices and clinical labs to change their organizations and operations for the better. The natural positive evolution of the University of Oklahoma Department of Pathology and OU Health Laboratories has been greatly accelerated by the global pandemic. While developing a substantial COVID testing response, our department of pathology and laboratories have evolved a much nimbler organizational structure, established an important research partnership, built a translational research resource, created a significant reference lab capability, and completed many key hires against a national background of hiring freezes and pay cuts. Also, the high visibility of the clinical lab and pathologists during the outbreak has reinforced the value of lab medicine to patient care across our health system. In the midst of significant ongoing changes to the structure and financing of our underlying organizations, high trust among departmental, hospital, health system, and medical school leadership during the pandemic has promoted these positive changes, allowing us to emerge much stronger from this crisis.
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Yu, He, Cong Wang, David A. Humphreys, Maoliu Lin, Luqman Ali, and Fanyi Meng. "Analysis of Time and Frequency Response for Single/Multi-Tone Stimulus Harmonic Phase-Reference Based on Prime Number Algorithm." Electronics 9, no. 11 (November 3, 2020): 1836. http://dx.doi.org/10.3390/electronics9111836.

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We present a spectrally-dense phase-reference and its calibration for nonlinear vector network analyzers (NVNAs) using a step recovery diode (SRD) comb-generator with a multi-tone stimulus. Frequency selection for multi-tone stimulus based on prime number algorithms was used with the Digital Real-Time Oscilloscope (DRTO) to avoid the sub-Nyquist spurs components and to increase the effective sampling rate so that the waveform can be observed in greater detail. The measured results were calibrated to minimize drift and jitter and achieved excellent agreement between the prime number and the exact frequency strategies except at the sub-Nyquist frequencies. The analysis indicates that the prime number selected frequencies show significantly improved performance by avoiding the DRTO distortion components. We have verified the validity of the method described in this paper by experimental measurement results.
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Martins, D. J., and S. D. Johnson. "Hawkmoth pollination of aerangoid orchids in Kenya, with special reference to nectar sugar concentration gradients in the floral spurs." American Journal of Botany 94, no. 4 (April 1, 2007): 650–59. http://dx.doi.org/10.3732/ajb.94.4.650.

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Han, Jae-Soub, Tae-Hyeok Eom, Seong-Wook Choi, Kiho Seong, Dong-Hyun Yoon, Tony Tae-Hyong Kim, Kwang-Hyun Baek, and Yong Shim. "A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator." Sensors 21, no. 20 (October 14, 2021): 6824. http://dx.doi.org/10.3390/s21206824.

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Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.
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Kuo, Feng-Wei, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Mark Chen, and Robert Bogdan Staszewski. "An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs." IEEE Transactions on Circuits and Systems I: Regular Papers 65, no. 11 (November 2018): 3756–68. http://dx.doi.org/10.1109/tcsi.2018.2855972.

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Dissertations / Theses on the topic "Reference spurs"

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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.

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Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.
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Gupta, Shashi Kant. "Understanding the process of Portfolio-Supported Learning & Assessment (PSLA) with reference to the learning attitudes of Postgraduate Medical Students (SpRs) at the Queen's School of Anaesthesia." Thesis, University of Newcastle Upon Tyne, 2006. http://hdl.handle.net/10443/927.

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Rapidly changing technology, the knowledge explosion and socio-economic transformations owing to globalisation have made it necessary for most people to learn throughout life. The terms such as `lifelong learning' and `continuous professional development' have become part of the educational lexicon as never before. Yet the formal education system alone cannot provide lifelong education for career development and there is research interest in promoting individual responsibility for becoming a self-directed autonomous learner. However, this idea is inconsistent with the prevailing teaching and assessment practices, namely, didactic teaching methods and norm-referenced summative assessment, where students are excluded from the process of deciding targets for learning, setting criteria and standards for assessment, designing assessment schemes and implementing them. Methods and techniques which are claimed to transfer the control of the educational and assessment process form teacher to student such as `Problem-Based Learning' and `Portfolio- Based Assessment', have been seen by researchers in the field of assessment as suitable alternatives to foster autonomy and intrinsic motivation in students. Although medical education in the UK has taken the lead in adopting `Problem Based Learning', teacher education is considerably ahead in the case of `Portfolio-Based Assessment'. Recently, medical education has also started to introduce `Portfolio-Based Assessment' in some colleges. However, its effectiveness in the context of medical education is yet to be established. This study, therefore, attempts to understand the process of `Portfolio-Based Assessment' with reference to the learning attitudes of postgraduate medical students (SpRs) in the context of the Queen's School of Anaesthesia situated in the north of England. The basic aim of this study was to evaluate the effectiveness of PBA in transforming the attitudes of the SpRs. The study revealed that it was very difficult to measure any change in attitude. Moreover, it was realised that in comparison to measuring change in attitudes it was more important to understand the process of intervention of the PBA in order to evolve remedial measures to make it more effective. This early finding considerably changed the focus of the study, research questions and methods. I also realised that the relationship between the effectiveness of the portfolio and the attitudes of SpRs was symbiotic, and so it was also important to understand these attitudes in order to understand the dynamics of portfolio use. The final aim was to understand the process of PBA, rather than to prove any particular theory or measure change in attitudes. Hence, the methodology adopted was more qualitative and naturalistic in nature than quantitative, with the aim of studying the process of PBA through a flexible methodology, and without any pre-conceived theories about the portfolio. However, findings concerning the process of PBA are situated in my understanding of theories of learning and current approaches to assessment within a particular context. The fieldwork combined two separate questionnaires distributed to all 90 SpRs, of whom about 50% responded. In order to understand their perceptions regarding the portfolio, nondirective interviews were carried out with 24 SpRs. Content analysis of the 24 portfolios was carried out to explore the extent to which the SpRs had developed the portfolios and the amount and type of reflection in which they engaged. Non-directed interviews and the content analysis of the portfolios raised questions about the SpRs' professionalism and their attitudes towards self-directed learning. To obtain a better understanding of these issues, focused interviews of 16 SpRs, based on the content analysis of the portfolios, were conducted. The understanding developed from this study and the findings and suggestions that have emerged from it are applicable mainly to postgraduate medical education. However, three propositions emerged from this study which may be relevant to the use of the portfolio for professional development in other educational contexts: (i) The term `Portfolio-Based Assessment' is a misnomer, since a portfolio does not become so central to the assessment process that it can be used to assess all types of ability. It may be concluded that a portfolio only supports the existing assessment system. (ii) The process of portfolio preparation itself leads to learning, while in the case of most of the other assessment processes the learning loop is completed after assessors have provided feedback. The portfolio should therefore be treated as a tool for both assessment and learning, and the term `Portfolio-Supported Assessment and Learning (PSLA)' is more appropriate. (iii) Other assessment methods may be used simultaneously for summative as well as for formative assessment without affecting the quality of formative assessment to a great degree. However, the use of portfolio for both purposes of assessment simultaneously creates a conflict and to a large extent reduces its potential for encouraging the trainees to engage in self-assessment and reflection, thus defeating the basic purpose for which it was introduced. It may be concluded that the same portfolio should not be used for both purposes of assessment. The emergence of the above propositions from the study may be considered as an original contribution to knowledge in this field. Further debate and studies are required in order to develop theories based on these propositions.
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Hsiao, Sen-Wen. "Built-in test for performance characterization and calibration of phase-locked loops." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51790.

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The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.
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Kamal, Noorfazila. "Reference spurs in an integer-N phase-locked loop : analysis, modelling and design." Thesis, 2013. http://hdl.handle.net/2440/80592.

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The Phase-Locked Loop (PLL) is commonly used for frequency synthesis in RF transceivers. It can be implemented in two architectures, namely, fractional-N and integer- N. In this thesis, the integer-N architecture is chosen due to its suitability for frequency planning. Here, a PLL with a low noise output is important to ensure signal purity. There are two dominant noise sources in a PLL, namely, phase noise and periodic noise. In the integer-N PLL, periodic noise is also referred to as a reference spur, where the noise gives rise to multiple reference frequency offsets at the PLL output. Of these two noise sources, this thesis is focused on the analysis and suppression of reference spurs. It is because less work has been carried in the literature regarding spurs, and phase noise is better studied. The main factors underlying reference spurs are discussed. These factors are mainly from the charge pump and phase/frequency detector (PFD) circuit non-idealities, namely, PFD delay, charge pump current leakage, charge pump current mismatch, and rise and fall times characteristic of the charge pump current. Reference spur magnitude can be predicted via a transient analysis. The simulation is time consuming, as the reference spur magnitude can only be captured after the PLL in its locked state. Therefore, the simulation period has to be set long enough to ensure enough data can be obtained to read that state. In this thesis, a reference spur mathematical analysis is presented to accurately estimate the reference spur magnitude. In the analysis, all the circuit non-idealities that contribute to the reference spur are considered. Circuit parameters required in the mathematical analysis can be obtained from transistor level simulation for each circuit. As the simulation for each circuit can be carried out separately, a large amount of simulation time can be saved. The proposed mathematical analysis also can be used to determine the major contributing factor to the problem of reference spurs. The reference spur also can be estimated via behavioural modelling simulation. Behavioural modelling of the PLL using Simulink is presented in this thesis. Each PLL component is modelled separately, and circuit non-idealities contributing to the reference spur are included in the behavioural model. In addition to reference spur estimation, the PLL behavioural model also can be used to visualise the dynamic behaviour of the system. Results from the spur analysis show that a slight mismatch current in the charge pump helps to improve the reference spur performance. This thesis presents an analysis to determine an optimum charge pump current ratio for reference spur suppression, which is caused by the charge pump current mismatch and the switching delay. Further, a ratioed current charge pump circuit is proposed to replace the conventional charge pump circuit for a reference spur performance improvement. This spur suppression technique is implemented using a 180 nm SiGe BiCMOS technology for performance evaluation.
Thesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 2013
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Pu, Xiao. "A bandwidth-enhanced fractional-N PLL through reference multiplication." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-4149.

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The loop bandwidth of a fractional-N PLL is a desirable parameter for many applications. A wide bandwidth allows a significant attenuation of phase noise arising from the VCO. A good VCO typically requires a high Q LC oscillator. It is difficult to build an on-chip inductor with a high Q factor. In addition, a good VCO also requires a lot of power. Both these design challenges are relaxed with a wide loop bandwidth PLL. However a wide loop bandwidth reduces the effective oversampling ratio (OSR) between the update rate and loop bandwidth and makes quantization noise from the ΔΣ modulator a much bigger noise contributor. A wide band loop also makes the noise and linearity performance of the phase detector more significant. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this dissertation we present a new PLL architecture for bandwidth extension or phase noise reduction. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single cycle of a sinusoidal reference and used for phase updates, effectively forming a reference frequency multiplier. A higher update rate enables a higher OSR which allows for better quantization noise shaping and makes a wideband fractional-N PLL possible. However since the proposed reference multiplier utilizes the magnitude information from a sinusoidal reference to obtain phases, the derived new edges tend to cluster around the zero-crossings and form an irregular clock. This presents a challenge in lock acquisition. We have demonstrated for the first time that an irregular clock can be used to lock a PLL. The irregularity of the reference clock is taken into account in the divider by adding a cyclic divide pattern along with the ΔΣ control bits, this forces the loop to locally match the incoming patterns and achieve lock. Theoretically this new architecture allows for a 6x increase in loop BW or a 24dB improvement in phase noise. One potential issue associated with the proposed approach is the degraded spurious performance due to PVT variations, which lead to unintended mismatches between the irregular period and the divider pattern. A calibration scheme was invented to overcome this issue. In simulation, the calibration scheme was shown to lower the spurs down to inherent spurs level, of which the total energy is much less than the integrated phase noise. A test chip for proof of concept is presented and measurements are carefully analyzed.
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Liao, Te-Wen, and 廖德文. "Low Reference-Spur and Low Phase-Noise Frequency Synthesizers for Wireless Communication Systems." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/86dfh4.

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博士
國立交通大學
電信工程研究所
101
Spur reduction and low phase noise techniques are proposed that allow integer-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Three integer-N synthesizers are presented. These circuits are targeted for analog TV (ATV) and mobile WIMAX applications. Synthesizer design still remains one of the most challenge issues in the RF system because it must meet very stringent requirements, such as settling time, phase noise, reference feedthrough, etc. Several trade-offs exist in the synthesizer design. First, the settling time is largely determined by the loop bandwidth which is limited to approximately 1/10 of the reference frequency for the loop stability consideration. Second, the phase noise of the oscillator is reduced by the feedback loop only within the loop bandwidth. Finally, in order to suppress the reference spur, a small loop bandwidth is required. To solve all these trade-offs, we have proposed several new architectures adopting random pulsewidth matching, sub-sampling charge-pump, and randomly selected PFD to achieve low reference spur and low phase noise PLLs. The first one is the Random pulsewidth matching frequency synthesizer with sub-sampling charge pump. Measurement results of a prototype TSMC 90nm CMOS synthesizer show that the reference spur is suppressed by 35dB. These represent a new analysis technique that is useful in the characterization of integer-N frequency synthesizers. The other is a spur-reduction frequency synthesizer exploiting randomly selected PFD. The oscillator frequency is tunable between 2500~2700 MHz, phase noise is -105dBc/Hz @1 MHz offset, and the spurious tone is -72dBc. Finally, a low phase-noise ring VCO based frequency synthesizer with multi-phase over-sampling charge-pump is implemented. To achieve good phase noise performance with a simple design, the multi-phase over-sampling charge-pump and one-shot circuits to reduce ripples on the control voltage of the VCO provide a smooth spectrum. Measured results from a prototype by TSMC 0.18um CMOS technology show the phase noise below–100 dBc/Hz from 15 Hz to 100 KHz and–108 dBc/Hz with 1 MHz offset.
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Wang, Shun Min, and 王舜民. "Digital MDLL-based clock generator using random code to achieve low reference spur." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/02130033451681210929.

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Fu, Chu-Hao, and 傅祖晧. "A 5.2-GHz All-Digital Frequency Synthesizer Chip Design with Reference Spur Reduction Technique." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/51003733798257168482.

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碩士
國立臺灣科技大學
電子工程系
103
Because of the rapid development of wireless communication systems, PLL-based frequency synthesizers are widely used for the past few years. With the promotion in integrated circuit technology, advanced fabrication processes are very favorable for digital design. In an all-digital phase-locked loop, the analog charge pump circuit and loop filter are replaced by a digital loop filter. This proposed study not only reduces the chip area but also avoids the effect of process shrinks. Besides, a digital design is scalable, easy to redesign with process changes, and has the advantage of noise immunity. Nowadays, the market demand trends towards low power supply and small chip area design, and that further promotes development of all-digital designs. This thesis adopts TSMC 0.18 um CMOS processing to realize an all-digital 5.2 GHz frequency synthesizer with reference spur reduction technique. The proposed architecture adopts a phase detector which only transfers phase error information when phase error is detected and can reduce the updating frequency for DCO control code and achieves lower reference spur. The proposed frequency synthesizer operates with 1.8 V supply voltage for both analog and digital circuits. The measuring results show that when output frequency is 5.22 GHz, the output signal power is -8.03 dBm. After locking, the phase noise is -110.74 dBc/Hz@1 MHz and the power consumption is 16.2 mW, while the chip area is 0.901 × 0.935 mm2.
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Yang, Jia-lun, and 楊佳倫. "A 1-V 2.4-GHz Fractional-N Frequency Synthesizer Chip Design with Reference Spur Reduction Techniques." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/yty4mt.

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碩士
國立臺灣科技大學
電子工程系
102
In recent year, with the rapid growing of the wireless communication system, many of PLL architectures are created. Normally, the loop filter of a conventional PLL are using continuous-time passive loop filter, it needs a large capacitance to meet system requirements. And the control node of the VCO is directly connected to the loop filter that will introduce ripples. Usually deals with a tradeoff between the settling time and the magnitude of the reference sideband that appears at the PLL output. The first chip, we introduce a 2.4 GHz fractional-N frequency synthesizer architecture with a reference spur reduction technique. It adopts a sample-hold-reset loop filter to isolate the charge pump output node and the VCO control node, which has a better linearity of PFD and CP. It achieves low spur and low phase noise performance, and save the capacitance area while a narrow loop bandwidth is used. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.21 GHz to 2.52 GHz corresponding to a frequency tuning range of 13.1%, a phase noise of -117.1 dBc/Hz at 1 MHz offset from 2.4 GHz, a reference spur of -65 dBc, a power consumption of 15.2 mW and the with pads chip area is only 1.06 mm2. The second chip, we adopt a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur. The frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage controlled oscillator to reduce the reference spur at the output of the phase-locked loop. The SSCP circuit is also utilized to reduce ripples on the control voltage to achieve low spur level. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.235 GHz to 2.579 GHz corresponding to a frequency tuning range of 14.3%, a phase noise of -113.17 dBc/Hz at 1 MHz offset from 2.41 GHz, a reference spur of -70.4 dBc, a power consumption of 9 mW and the with pads chip area is only 0.695 mm2.
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Books on the topic "Reference spurs"

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Murphy, John McLeod. Spars and rigging from Nautical routine, 1849. Mineola, N.Y: Dover Publications, 2003.

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Murphy, John M'Leod, and W. N. Jeffers. Spars and Rigging: From Nautical Routine, 1849. Dover Publications, 2003.

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Book chapters on the topic "Reference spurs"

1

Singh, Radhika, K. K. Abdul Majeed, and Umakanta Nanda. "Transmission Gate Based PFD Free of Glitches for Fast Locking PLL with Reduced Reference Spur." In Communications in Computer and Information Science, 404–14. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_32.

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Wittig, Steffen. "In Verteidigung der Gleichheit." In Kritik und Post-Kritik, 73–90. Bielefeld, Germany: transcript Verlag, 2022. http://dx.doi.org/10.14361/9783839459799-005.

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Der Beitrag versucht die Rancièresche Spur der Gleichheit, auf die sich das 'Manifest für eine Post-Kritische Pädagogik' implizit bezieht, aufzunehmen und einerseits zu problematisieren, in welchem Verhältnis sich eine Annahme der Gleichheit zu einer Sphäre des Gemeinsamen artikuliert. Hierzu wird in einem ersten Schritt auf zwei Perspektivierungen des Begriffs der Gleichheit bei Jacques Rancière Bezug genommen, da über seine Perspektive möglich wird, kritische Rückfragen an das 'Manifest' zu stellen. Hierbei wird zum einen a) unter Referenz auf 'Das Unvernehmen' (2002) herausgestellt werden, dass dieser Begriff der Gleichheit für Rancière zum Ausgangspunkt dafür wird, was er ,Politik' nennt. Er besteht in der Inanspruchnahme eines Anteils an einer ,Aufteilung des Sinnlichen', von der aber diejenigen, die jenen Anspruch der Zugehörigkeit stellen, ausgeschlossen sind. Eine solche Perspektivierung von ,Gleichheit' beruht damit auf der praktischen Problematisierung eines real erfahrenen Regimes ungleicher Verteilungen sozialer Positionen, dessen Infragestellung gerade erst die Frage aufwirft, was von welcher Subjektposition aus in welcher Weise als Gemeinsames hervorgebracht wird (vgl. Rancière 2002: 10). Zum anderen thematisiert Rancière b) die Gleichheit als Möglichkeit eines gemeinsamen Bezugspunktes in der Form der Beanspruchung einer "Gleichheit der Intelligenzen" (Rancière 2007, S. 52). Vor dem Hintergrund eines solchen höchst problematischen Gemeinsamen soll in einem zweiten Schritt gefragt werden, wie eine ,Verteidigung' desgleichen skizziert werden könnte.
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Harding, Dennis. "Defining Issues." In Iron Age Hillforts in Britain and Beyond. Oxford University Press, 2012. http://dx.doi.org/10.1093/oso/9780199695249.003.0005.

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‘Hillfort’ is a term of convenience. It is widely recognized that the monuments in question are not restricted topographically to hills, and that their role may not have been primarily, and certainly not exclusively, for military defence. Nor are they restricted chronologically to the Iron Age, though during that period they are particularly prominent. The term came into general currency following the publication in 1931 of Christopher Hawkes’ paper, simply entitled ‘Hillforts’, in Antiquity, which also established their predominantly Iron Age date in Britain. Prior to that, Christison (1898) in Scotland had discussed ‘fortifications’, and Hadrian Allcroft (1908) for England had classified ‘earthwork’, both extending their studies into the Medieval period. But ‘hillfort’ for all its limitations has remained in general usage in Britain. Chronologically, this study is concerned with the ‘long Iron Age’; that is, including the post-Roman Iron Age in northern Britain especially, and with later Bronze Age antecedents. Geographically it is concerned with regional groups throughout Britain, but with further reference to Ireland, and in the wider context of relevant sites and developments in continental Europe. The key element of the sites under consideration is enclosure, physically or conceptually demarcating an area to which access is restricted or controlled. This may be achieved by rampart and ditch, stockade or fence, or by the incorporation of topographical and natural features such as cliff-edge or marsh. The scale of enclosing works may range from a relatively modest barrier to massive earthworks that reshape the landscape, and in structural morphology, from single palisade or bank to multiple lines, variously disposed. Topographically they may be located around hilltop contours, on cliffedge, ridge, or promontory, on spurs or hill slopes, in wetlands or spanning river bends, or across variable terrain. In area enclosed they may range from well under a hectare to 20 ha and more, with the territorial or terrain oppida of the late pre-Roman Iron Age attaining 300 ha or more. From size alone, therefore, we may infer a great diversity in the practical, social, and symbolic purposes that they may have served. At the smaller end of the scale, the distinction between hillforts and other enclosed settlements is sometimes a matter of subjective assessment, but otherwise their size and scale suggests that they were community sites, serving a social unit larger than a single family or household.
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Apostolidis, Paul. "Desperate Responsibility." In The Fight For Time, 73–114. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780190459338.003.0003.

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The temporally inflected theme of “desperate responsibility” predominates when day laborers describe their incessant work searches and arbitrary treatment by employers. For day laborers, temporal uniformity fostered by anxiety about insufficient work mingles with extreme temporal discontinuity whenever jobs and employers’ demands shift. In a contradictory response, day laborers affirm a time-conscious work ethic of personal responsibility even while their self-avowed desperation precludes independent choice. This predicament reflects migrant workers’ exceptional exposure to neoliberal crises and the deportation regime. Yet desperate responsibility also references contradictions experienced by working people in general due to the postindustrial work ethic, affective labor, and digital work. As work bleeds into every waking moment while undergoing severe temporal fragmentation, workers are pressed to embrace responsibility freely under conditions that undermine capacities for free action. This critical-popular investigation thus spurs militant demands to end deportation and to reject the self-destructive temporalities of our contemporary work culture.
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Conference papers on the topic "Reference spurs"

1

Carmo, Joao Paulo, and Jose Higino Correia. "PLL at 2.4 GHz with reduced reference spurs." In 2011 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC). IEEE, 2011. http://dx.doi.org/10.1109/imoc.2011.6169258.

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Zhang, Jingzhi, Sherif S. Ahmed, and Amin Arbabian. "Effects of Reference Frequency Harmonic Spurs in FMCW Radar Systems." In 2021 IEEE Radar Conference (RadarConf21). IEEE, 2021. http://dx.doi.org/10.1109/radarconf2147009.2021.9455280.

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Sharma, Jahnavi, and Harish Krishnaswamy. "A dividerless reference-sampling RF PLL with −253.5dB jitter FOM and <-67dBc Reference Spurs." In 2018 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2018. http://dx.doi.org/10.1109/isscc.2018.8310282.

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Changhong Huan, Xiushan Wu, and Dan Wang. "A charge-pump circuit to restrain reference spurs in the PLL." In 2011 IEEE 9th International Conference on ASIC (ASICON 2011). IEEE, 2011. http://dx.doi.org/10.1109/asicon.2011.6157378.

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Zhuo, Gao, Divya Kesharwani, Patrick Chiang, and Hu Weiwu. "Measuring and compensating for process mismatch-induced, reference spurs in phase-locked loops using a sub-sampled DSP." In 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009. IEEE, 2009. http://dx.doi.org/10.1109/iscas.2009.5118073.

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Jiang, Junning, Tanwei Yan, Dadian Zhou, Aydin Ilker Karsilayan, and Jose Silva-Martinez. "A 2.3-3.9 GHz Fractional-N Frequency Synthesizer with Charge Pump and TDC Calibration for Reduced Reference and Fractional Spurs." In 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2021. http://dx.doi.org/10.1109/rfic51843.2021.9490444.

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Waheed, Khurram, Robert Bogdan Staszewski, and John Wallberg. "Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation." In 2007 IEEE International Symposium on Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/iscas.2007.378214.

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Nagam, Shravan S., and Peter R. Kinget. "A 0.008mm2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a −239.7dB FoM and −64dBc reference spurs." In 2018 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2018. http://dx.doi.org/10.1109/cicc.2018.8357091.

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Kooshkaki, Hossein Rahmanian, and Patrick P. Mercier. "A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT." In 2020 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2020. http://dx.doi.org/10.1109/cicc48029.2020.9075944.

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Hickle, Mark D., Kevin Grout, Curtis Grens, Gregory Flewelling, and Steven Eugene Turner. "A Single-Chip 25.3–28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs." In 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). IEEE, 2021. http://dx.doi.org/10.1109/bcicts50416.2021.9682458.

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