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Digvadekar, Ashish A. "A sub 1 V bandgap reference circuit /." Online version of thesis, 2005. https://ritdml.rit.edu/dspace/handle/1850/2595.
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Tran, Sung. "Development of a Sensor Readout Integrated Circuit Towards a Contact Lens for Wireless Intraocular Pressure Monitoring." DigitalCommons@CalPoly, 2017. https://digitalcommons.calpoly.edu/theses/1750.
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This design covers the design of an integrated circuit (IC) in support of the active contact lens project at Cal Poly. The project aims to monitor intraocular eye pressure (IOP) to help diagnose and treat glaucoma, which is expected affect 6.3 million Americans by 2050. The IC is designed using IBM’s 130 nm 8RF process, is powered by an on-lens thin film 3.8 V rechargeable battery, and will be fabricated at no cost through MOSIS. The IC features a low-power linear regulator that powers a current-starved voltage-controlled oscillator (CSVCO) used for establishing a backscatter communication link. Additional circuitry is included to regulate power to and from the battery. An undervoltage lockout circuit protects the battery from deep discharge damage. When recharging, a rectifier and a voltage regulator provides overvoltage protection. These circuit blocks are biased primarily using a 696 mV subthreshold voltage reference that consumes 110.5 nA.
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Bubla, Jiří. "Band Gap - přesná napěťová reference." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217808.
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This diploma thesis is specialized on a design of a high accuracy voltage reference Bandgap. A very low temperature coefficient and output voltage approx. 1,205V are the main features of this circuit. The paper contains a derivation of the Bandgap principle, examples of realizations of the circuits and methods of compensation temperature dependence and manufacture process, design of Brokaw and Gilbert reference, design of a testchip and measurement results.
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Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.
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The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.
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Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment.
Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques.
These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented
in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic
architecture.
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Gupta, Vishal. "An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.
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Gaddam, Ravi Shankar. "A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation." University of Akron / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=akron1349294825.
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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Castellanos, Juan José Carrillo. "Projeto de uma fonte de tensão de referência CMOS usando programação geométrica." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01032011-120430/.
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Nesta dissertação é apresentada a aplicação da programação geométrica no projeto de uma fonte de tensão de referência de baixa tensão de alimentação que pode ser integrada em tecnologias padrões CMOS. Também são apresentados os resultados experimentais de um projeto da fonte de bandgap feito por um método de projeto convencional, cuja experiência motivou e ajudou ao desenvolvimento da formulação do programa geométrico proposta neste trabalho. O programa geométrico desenvolvido nesta dissertação otimiza o desempenho da fonte de bandgap e agiliza seu tempo de projeto. As expressões matemáticas que descrevem o funcionamento e as principais especificações da fonte de bandgap foram geradas e adaptadas ao formato de um programa geométrico. A compensação da temperatura, o PSRR, o consumo de corrente, a área, a tensão de saída e a sua variação por causa da tensão de offset do OTA, e a estabilidade são as principais especificações deste tipo de fonte de tensão de referência e fazem parte do programa geométrico apresentado neste trabalho. Um exemplo do projeto usando o programa geométrico formulado neste trabalho, mostra a possibilidade de projetar a fonte de bandgap em alguns minutos com erros baixos entre os resultados do programa geométrico e de simulação.This work presents the application of geometric programming in the design of a CMOS low-voltage bandgap voltage reference source. Test results of a bandgap voltage reference designed via a conventional method are showed, this design experience motivated and helped to formulate the geometric program developed in this work. The geometric program developed in this work optimizes the bandgap source performance and speeds up the design time. The mathematical expressions that describe the bandgap source functioning and specifications were developed and adapted in the geometric program format. The temperature compensation, the PSRR, the current consumption, the area, the output voltage and its variations under the operational tranconductance amplifier offset voltage, and the stability are the main specifications of this type of bandgap reference source and they are included into the geometric program presented in this work. An example of the design using the geometric program formulated in this work, shows the possibility of designing the bandgap source in a few minutes with low errors between the geometric program results and the simulation results.
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Montjane, Raesibe Oniccah. "The influence of English on mother-tongue in learning and teaching in secondary schools (Fet Band) with specific reference to Sepedi in Mankweng Circuit in the Limpopo Province." Thesis, University of Limpopo, 2013. http://hdl.handle.net/10386/1287.
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Thesis (MA. (Translation Studies and Linguistics)) -- University of Limpopo, 2013The study sought to investigate the challenges that the learners and educators encountered in learning and teaching when they use English as a medium of instruction. The study reveals that African languages, along with their culture are being dominated by English. Most of Pedis’ learners cannot speak Sepedi without mixing it with English, and most of African people usually read English books and neglecting the Indigenous books. In addition, the study shows that learners performed better when they were taught in Sepedi than in English. The educators’ responses showed that learners have difficulties in understanding English as the medium of instruction and that they code-switch from English to Sepedi to enhance understanding.
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Holmberg, Pär. "Modelling the transient response of windings, laminated steel coresand electromagnetic power devices by means of lumped circuits : With special reference to windings with a coaxial insulation system." Doctoral thesis, Uppsala University, Department of High Voltage Research, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-548.
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Electromagnetic transients impinging on electromagnetic power devices - such as electric machines, transformers and reactors - can stress the design severely. Thus the magnitudes of the transients are often decisive for the design of the devices. Further, the operation of a device can be transient in itself. This is the case for the explosive magnetic flux compression generator (EMG) and a ferromagnetic actuator.
Models are presented that are mainly intended for transients in the millisecond range and faster. Hence, eddy currents and the related skin and proximity effect become significant in windings, magnetic cores and in the armatures of the devices. These effects are important for, e.g., the damping of the transients. Further, the displacement current in the insulation of the winding is significant. It changes the response of the windings dramatically, as it manifests the finite velocity of propagation of the electromagnetic fields. Under such circumstances, reflections and excited resonances can make the transient voltage and current distribution highly irregular.
Induced voltages are modelled with self and mutual inductances or reluctances combined with winding templates. The displacement currents are modelled with capacitances or coefficients of potential. Cauer circuits and their dual form are used to model eddy currents in laminated cores and in conductors. The Cauer circuit enables one to consider hysteresis and the non-linear response of a magnetic core. It is also used to model the eddy currents in the moving armature of an EMG.
A set-up is presented that can be used to study the transient voltage and the current distribution along a coil.
The transient response of coaxially insulated windings is analysed and modelled in detail. A lumped circuit model is developed for a coil, DryformerTM - the new high-voltage transformer - and PowerformerTM, the new high-voltage generator. An alternative model, a combined lumped circuit and FEM model, is presented for a coaxially insulated winding in two slot cores.
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Sanikommu, Ramanarayana Reddy. "Design and Implementation of Bandgap Reference Circuits." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-398.
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An important part in the design of analog integrated circuits is to create reference voltages and currents with well defined values. To accomplish this on-chip, so called bandgap reference circuits are commonly used. A typical application for reference voltages is in analog-to-digital conversion, where the input voltage is compared to several reference levels in order to determine the corresponding digital value. The emphasis in this thesis work lies on theoretical understanding of the performance limitations as well as the design of a bandgap reference circuit, BGR.
In this project, a comprehensive study of bandgap circuits is done in the first stage. Then investigations on parameter variations like Vdd, number of bipolars, W/L of PMOS, DC gain of Opamp, RL and CL are done for a PTAT current generator circuit. This PTAT current generator circuit is a part of the implemented BGR circuit based on [10], which is capable of producing an output reference voltage of 0.75 V when the supply voltage is 1 V. All of these circuits are implemented in a 0.35u CMOS technology.
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Sassi, Mariela Mayumi Franchini Sasaki. "Projeto de fontes de tensão de referência através de metaheurísticas." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-134021/.
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Geradores de referência, ou fontes de tensão de referência, são largamente empregados na composição de diversos circuitos eletrônicos, pois são responsáveis por gerar e manter uma tensão constante para o restante do circuito. Como se trata de um circuito analógico e que possui diversas condições a serem atendidas (baixo coeficiente de temperatura, baixa tensão de alimentação, baixa regulação de linha, dentre outras), sua complexidade é alta e isso se reflete no tempo/dificuldade de um projeto. Com a finalidade de aumentar a qualidade do circuito e diminuir o tempo de projeto, foi estudado o projeto de fontes de tensão de referência através da aplicação de metaheurísticas, que são métodos de otimização utilizados em problemas que não possuem solução analítica. As metaheurísticas aplicadas foram: algoritmos genéticos, simulated annealing e pattern search, todos disponíveis em uma toolbox de otimização do Matlab. A fonte projetada, utilizando uma topologia proposta neste trabalho, fornece uma tensão de referência de 0,302 V em 300 K a uma tensão mínima de operação de 1,01 V. O coeficiente de temperatura, no intervalo de -10°C a 90°C, é de 19 ppm/°C a 1,01 V e a regulação de linha, com tensão de alimentação no intervalo de 1,01 V a 2,5 V, é de 81 ppm/V a 300 K. O consumo de potência é de 4,2 \'mü\'W, também em 300 K e a 1,01 V e a área é de 0,061 \'MM POT.2\'. Como resultado, mostrou-se a eficiência da utilização destes métodos no dimensionamento de elementos do circuito escolhido e foi obtida uma fonte de tensão de referência que atende aos critérios estabelecidos e é superior quanto ao critério de regulação de linha, quando comparada a outras fontes da literatura. Neste trabalho, foi utilizada a tecnologia CMOS de 0,35 \'mü\'m da Austria Micro Systems (AMS).Voltage references are widely employed to compose electronic circuits, since they are responsible for generating and maintaining a constant voltage to the rest of the circuit. As it is an analog circuit and it has several conditions to fulfill (low temperature coefficient, low supply voltage, low line regulation, among others), its complexity is high, which reflects at the time/difficulties of a design. In order to increase the quality of the circuit and to minimize the design time, it was studied voltage references design using metaheuristics, which are optimization methods used in problems with no analytical solution. The applied metaheuristics were: genetic algorithms, simulated annealing and pattern search, they are all available in an optimization toolbox at Matlab. The designed voltage reference, applying a topology proposed in this work, provides a reference voltage of 0.302 V at 300 K at a minimum supply voltage of 1.01 V. The temperature coefficient, from -10°C to 90°C, is 19 ppm/°C at 1.01 V and the line regulation, using a supply voltage from 1.01 V to 2.5 V, is 81 ppm/V at 300 K. The power consumption is 4.2 W also at 300 K and 1.01 V and the area is 0.061 \'MM POT.2\'. As a result, it was shown that those methods are efficient in sizing the devices of the chosen topology and it was obtained a voltage reference that fulfills all established criteria and that is superior at the line regulation criterion, when compared to other voltage reference of the literature. In this work, the 0.35-\'mü\'m CMOS technology provided by Austria Micro Systems (AMS) was used.
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Boo, Hyun Ho. "Virtual ground reference buffer technique in switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99812.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 121-125).
The performance of switched-capacitor circuits depends highly on the op-amp specifications. In conventional designs, trade-offs in speed, noise, and settling accuracy make it difficult to implement power-efficient switched-capacitor circuits. The problem originates from the inverse relationship between the feedback factor and the signal gain. This thesis proposes the virtual ground reference buffer technique that enhances performance by improving the feedback factor of the op-amp without affecting signal gain. A key concept in the technique is the bootstrapping action of level-shifting buffers. It exploits op-amp-based circuits whose principles are very well understood and the design techniques are mature. The solution ultimately relaxes the required op-amp requirements including unity-gain bandwidth, noise, offset voltage and open-loop gain that would otherwise result in complex design and high power consumption. The concept is demonstrated in a 12-b 250MS/s pipelined ADC.
by Hyun Ho Boo.
Ph. D.
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Ishibe, Eder Issao. "Projeto de uma fonte de tensão de referência." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-24072014-165540/.
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Neste trabalho é apresentado o projeto de uma fonte de tensão de referência, um circuito capaz de prover uma tensão invariante com a temperatura, a tensão de alimentação e o processo de fabricação. São apresentadas: as equações de funcionamento, os passos para a elaboração da uma topologia final, o dimensionamento dos parâmetros de projeto com o uso de algoritmos metaheurísticos, o desenho do layout e os resultados e análises finais. O projeto emprega a tecnologia CMOS de 0,35 μm com quatro camadas de metal da Austria Micro Systems, em que os VTH0\'s dos transistores NMOS e PMOS, modelo típico, são, respectivamente, 0,5 V e -0,7 V. O circuito de fonte de referência é do tipo bandgap e faz a soma ponderada de correntes proporcionais a temperatura para atingir uma tensão de referência. Obteve-se um circuito típico com 0,5 V de tensão de referência, coeficiente de temperatura de 15 ppm/ºC em intervalo de temperatura de -10 a 90ºC em 1,0 V de tensão de alimentação, regulação de linha de 263 ppm/V em um intervalo de variação de 1,0 V a 2,5 V em 27ºC, 2,7 μA de corrente consumida e área de 0,11 mm². A introdução de um bloco de ajuste de coeficiente de temperatura, com ajuste digital, permite que mais que 90% dos circuitos produzidos tenham um coeficiente de temperatura de até 30 ppm/ºC. As medidas realizadas no trabalho são provenientes de simulações elétricas realizadas com o ELDO e modelos BSIM3v3.In this work is presented a design of a reference voltage source, circuits capable to provide an invariant voltage regardless of the temperature, power supply and fabrication process. It\'s presented: the operation equations, the steps to elaborate a final topology, the project parameter sizing using a metaheuristic algorithm, the drawing of the layout, and the final results and its analysis. The design employs an AMS-CMOS 0.35 μm technology with four metal levels, whose NMOS and PMOS VTH0\'s for a typical circuit is 0.5 V and -0.7 V. The reference voltage circuit is bandgap and performs a weighted summation of proportional temperature currents to achieve the voltage reference. A typical circuit was obtained with 0.5 V reference voltage, 15 ppm/ºC temperature coefficient in the temperature range of -10 to 90ºC under 1.0 V power supply, 263 ppm/V line regulation in the range of 1.0 V to 2.5 V under 27ºC, 2.7 μA power consumption in a 0.11 mm² area. For a projected circuit its also possible to ensure a temperate coefficient under 30 ppm/ºC, for more than 95% of the produced circuits, employing an adjustment block which ought to be digitally calibrated for each circuit.
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Holman, William Timothy. "A low noise CMOS voltage reference." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.
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Coimbra, Ricardo Pureza. "Geração de tensão de referencia e sinal de sensoriamento termico usando transistores MOS em forte inversão." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262029.
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Orientador: Carlos Alberto dos Reis FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-14T00:43:32Z (GMT). No. of bitstreams: 1 Coimbra_RicardoPureza_M.pdf: 4991793 bytes, checksum: 2b5fb9293ae9abe4c248964485ff74e3 (MD5) Previous issue date: 2009
Resumo: Fontes de referência de tensão e sensores de temperatura são blocos extensivamente utilizados em sistemas microeletrônicos. Como alternativa à aplicação de estruturas consolidadas, mas protegidas por acordos de propriedade intelectual, é permanente a demanda pelo desenvolvimento de novas técnicas e estruturas originais destes circuitos. Também se destaca o crescente interesse por soluções de baixa tensão, baixo consumo e compatíveis com processos convencionais de fabricação. Este trabalho descreve o desenvolvimento de um circuito que atende a estas exigências, fornecendo uma tensão de referência e um sinal de sensoriamento térmico, obtidos a partir de um arranjo adequado de transistores MOS, que operam em regime de forte inversão. O princípio de operação do circuito desenvolvido foi inspirado no conceito de que é possível empilhar n transistores MOS, polarizados com corrente adequada, de tal forma que a queda de tensão sobre a pilha de transistores, com amplitude nVGS, apresente a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Nesta condição, a diferença entre as duas tensões é constante em temperatura, constituindo-se em uma referência de tensão. No entanto, o empilhamento de dois ou mais transistores impossibilita a operação do circuito sob baixa tensão. Isto motivou a adaptação da técnica, obtendo a tensão nVGS com o auxílio de um arranjo de resistores, sem o empilhamento de transistores. Desta forma, o potencial limitante da tensão mínima de alimentação tornou-se a própria tensão de referência, cuja amplitude é próxima de um único VGS. A estrutura desenvolvida fornece também um sinal de tensão com dependência aproximadamente linear com a temperatura absoluta, que pode ser aplicado para sensoriamento térmico. Foram fabricados protótipos correspondentes a diversas versões de dimensionamento do circuito para comprovação experimental de seu princípio de operação. O melhor desempenho verificado corresponde à geração de uma tensão de referência com coeficiente térmico de 8,7ppm/ºC, no intervalo de -40ºC a 120ºC, operando com tensão de 1V. Embora o estado da arte seja representado por índices tão baixos quanto 1ppm/ºC, para a mesma faixa de temperatura, a característica compacta do circuito e seu potencial de aplicação sob as condições de baixa tensão e baixo consumo lhe conferem valor como contribuição para este campo de pesquisa e desenvolvimento.
Abstract: Voltage references and temperature sensors are blocks extensively used in microelectronic systems. As an alternative to the use of consolidated structures that are protected by intellectual property agreements, there is a permanent demand for the development of new techniques and structures for these circuits. It can be also highlighted the growing interest for low-voltage and low-power solutions, implemented in conventional IC technologies. This work describes the development of a circuit that meets these requirements by providing a voltage reference and temperature sensing signal obtained from a suitable arrangement of MOS transistors biased in strong inversion. The operation principle of the circuit developed is based on the concept that it is possible for a stack of n MOS transistors, biased by an appropriate current, to show a voltage drop, equal to nVGS, with the same thermal variation rate as a VGS voltage produced by a single transistor. Hence, the difference between the two voltage signals is temperature independent, characterizing a voltage reference. However, the stacking of two or more transistors prevents the operation of the circuit under low voltage. This fact motivated to adapt the technique by obtaining the voltage nVGS with the aid of an array of resistors and no stacked transistors. The minimum supply voltage becomes limited only by the reference voltage itself, whose amplitude is close to a single VGS. The circuit developed also provides a voltage signal almost linearly dependent with the absolute temperature, which can be applied for thermal sensing. Prototypes corresponding to various dimensional versions of the circuit were produced to experimentally verify the principle of operation. The best performance corresponds to the generation of a voltage reference signal with 8.7ppm/ºC thermal coefficient, from -40ºC to 120ºC, under a 1V supply voltage. Although the state of the art is represented by values as low as 1ppm/ºC, at the same temperature range, the circuit's compact aspect together with the possibility to attend low-voltage and low-power requirements grants it value as contribution to this field of research and development
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Toledo, Pedro Filipe Leite Correia de. "Modelamento e análise do efeito de coeficiente nulo de temperatura (ZTC) do Mosfet para aplicações análogicas de baixa sensibilidade têrmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/140814.
Full textAbstract:
A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C.Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.QC 20170905
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Cajueiro, João Paulo Cerquinho. "Fonte de tensão de referencia ajustavel implementada com transistores MOS." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260509.
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Orientador: Carlos Alberto dos Reis FilhoTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Uma nova técnica de compensação de temperatura para implementar tensões de referência em circuitos CMOS é descrita, desde o seu fundamento teórico até a comprovação experimental feita com amostras de circuitos integrados protótipos que a implementam. A ténica proposta se baseia no fato de que a tensão entre gate1, e fonte, VGS, de um transistor MOS pode tanto aumentar como diminuir com o aumento da temperatura, dependendo da corrente com que opera. Com base nisto, é possível empilhar n transistores, que estejam polarizados com uma corrente adequada de tal maneira que a queda de tensão sobre esta pilha de transistores, que tem amplitude nVGS, tenha, ao mesmo tempo, a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Em tais condições, a diferença entre estas duas tensões é constante, tornando-se uma referencia de tensão. Uma implementação alternativa à pilha de transistores para produzir a tensão nVGS consiste num único transistor de gate ?utuante no qual a tensão VGS equivalente tem amplitude ajustável em campo. Diversos circuitos que se baseiam nesta técnica foram projetados e alguns deles fabricados em tecnologia CMOS 0,35 µm.O desempenho do melhor circuito fabricado atingiu coe?ciente térmico de 100 ppm/°C na faixa térmica de -40 a 120 °C. Outras configurações foram simuladas mostrando que é possível atingir coeficientes térmicos menores que 10 ppm/°C. O estado da arte é representado por referências de tensão que têm coeficientes térmicos de 1 ppm/°C na mesma faixa térmica em que se caracterizam os circuitos desenvolvidos. Tais referências de tensão se baseiam principalmente nos circuitos chamados de bandgap. Há também, um produto recente da empresa Intersil que utiliza um transistor que opera como memória análoga fornecendo uma tensão referência memorizada com altíssima estabilidade térmica. O princípio em que este produto se baseia, entretanto, é diferente do que está sendo proposto neste trabalho apesar do uso comum de um transistor de gate ?utuante. A contribuição deste trabalho não está no desempenho que as fontes de referência que se baseiam no princípio atingiram. Sua contribuição reside na forma como pode ser implementada, utilizando somente transistores MOS e no fato de que tem amplitude ajustável em campo. 1A palavra gate está sendo usada em toda extensão do texto, em lugar da palavra ¿porta¿, para identi?car o terminal de alta resistência de um transistor MOS
Abstract: A new technique of temperature compensation to implement a voltage reference in CMOS circuits is described, from theoretical basis to experimental evidence made with samples of integrated circuits prototypes that implement it. The proposed technique is based on the fact that the voltage between gate and source, VGS, of a MOS transistor can either increase as diminish with the increase of temperature, depending on the current with that it operates. Based in this, it is possible to pile up n transistors, that are polarized with an adequate current in such way that the voltage on this stack of transistors, that has amplitude nVGS, has, at the same time, the same thermal variation than the VGS voltage produced in only one transistor. In such conditions, the difference between these two voltages is constant, becoming a voltage reference. An alternative implementation to the stack of transistors to produce the nVGS volage consists of a ?oating gate transistor in which equivalent VGS has adjustable amplitude in ?eld. Diverse circuits that are based on this technique had been projected and some of them manufactured in technology CMOS 0,35 µm. The performance of the best manufactured circuit reached 100 ppm/°C of thermal coefficient in the thermal band of -40 to 120 °C. Other con?gurations had been simulated showing that it is possible to reach thermal coe?cients lesser that 10 ppm/°C. The state of the art is represented by voltage references that have thermal coefficients of 1 ppm/°C in the same thermal band where the developed circuits had been characterized. Such voltage references are mainly based on the circuits called bandgap. There is, also, a recent product of the Intersil company who uses a transistor that operates as analogical memory supplying a voltage reference memorized with highest thermal stability. The base principle of this product is, however, different of that being considered in this work despite the use of a ?oating gate transistor. The contribution of this work is not in the performance that the reference sources that are based on the principle had reached. Its contribution inhabits in the form as it can be implemented, only using MOS transistors and in the fact that it has adjustable amplitude in ?eld
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Amaral, Wellington Avelino do. "Referencia de tensão CMOS com correção de curvatura." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260213.
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Orientador: Jose Antonio Siqueira DiasTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho teve como finalidade o projeto e prototipagem de uma referência de tensão CMOS (Complementary Metal Oxide Semiconductor) baseada na tensão de limiar do transistor MOS (Metal Oxide Semiconductor). A inovação apresentada neste trabalho é a utilização de uma arquitetura original e com alto desempenho. Nas medidas realizadas em laboratório o circuito apresentou uma variação de 11ppm/0C. Desempenho este comparável às referências do tipo bandgap. Também foi projetado um sensor de temperatura com coeficiente térmico igual a 1mV/0C. Portanto, dois circuitos foram enviados para fabricação (o circuito ceinv35 e o circuito ceinv66). O circuito ceinv35, utilizando suas estruturas de trimmer, pode operar como referência de tensão ou como sensor de temperatura. O circuito ceinv66 foi a principal configuração estudada. Ele utiliza um circuito extrator de Vth, um circuito de start-up e um amplificador operacional. O circuito extrator de Vth utiliza uma topologia inovadora. Nos dois circuitos (ceinv35 e ceinv66) foram utilizadas estruturas de trimmer para possibilitar ajustes externos. No capítulo de introdução é apresentado um "overview" dos circuitos utilizados como referência de tensão. São analisadas algumas referências do tipo bandgap e algumas técnicas usualmente utilizada para o projeto de referências de tensão CMOS. No capítulo 2 são analisados o princípio de funcionamento e todo o equacionamento do circuito proposto. No capítulo 3 são apresentados os resultados de simulação. O circuito ceinv35 apresentou um coeficiente térmico igual a 1mV/0C, funcionando ele como sensor de temperatura. Já operando como referência de tensão, a variação apresentada foi de 4:06ppm/0C. O circuito ceinv66 apresentou uma variação de apenas 3:14ppm/0C. O capítulo 4 cobre o projeto dos layouts dos circuitos. Eles foram projetados utilizando a tecnologia da AMS (Austria Microsystems) de comprimento mínimo de canal igual a 0:35_m. No capítulo 5 são apresentados os resultados da extração de parasitas dos circuitos. Após esta análise foi verificada a necessidade de reajuste dos circuitos, utilizando as estruturas de trimmer. No capítulo 6 são fornecidos os resultados experimentais dos dois circuitos. No capítulo 7 é apresentada uma alternativa para o projeto da referência de tensão sem a necessidade da utilização do circuito de start-up. Neste mesmo capítulo também é apresentada uma proposta de metodologia para projeto dos trimmers do circuito. No capítulo 8 são discutidas as inovações propostas neste trabalho e algumas conclusões sobre o projeto apresentado.
Abstract: The objective of this work is to design and prototype a CMOS voltage reference based on the threshold voltage of the MOS transistor. The innovation presented in this work is the use of an original architecture with high performance. In the laboratory measurements the circuit presented 11ppm/0C of variation. This performance is comparable to the bandgap references. A temperature sensor was also designed and presented a temperature coefficient of 1mV/0C. Therefore, two circuits were prototyped (the ceinv35 circuit and the ceinv66 circuit). The circuit ceinv35, using the trimmer structures, can operate as a voltage reference or a temperature sensor. The circuit ceinv66 was the main topology studied. It uses a Vth extractor circuit, a start-up circuit and an operational amplifier. The Vth extractor circuit uses an original topology. In both circuits (ceinv35 and ceinv66) were used trimmer structures to make possible off-chip adjusts. In the introduction chapter is presented an overview of the circuits used as voltage references. Some bandgap references and some techniques used to design CMOS voltage references are analyzed. In chapter 2 are shown the operation principles and the equations extracted of the proposed circuit. In chapter 3 are shown the simulation results. The circuit ceinv35 presented a temperature coefficient of 1mV/0C, working as a temperature sensor. On the other side, working as a voltage reference, the variation presented was 4:06ppm/0C. The circuit ceinv66 presented a variation of just 3:14ppm/0C. The chapter 4 covers the layout design of the circuits. The AMS (Austria Microsystems) technology with a minimum channel length of 0:35_m was used. In chapter 5 are presented the parasitic extraction simulations. After this analyses new adjusts were made in the circuits. The trimmers structures were used for this adjusts. In chapter 6 are provided the experimental results of both circuits. In chapter 7 is presented an alternative for the voltage reference design without using a start-up circuit. In this chapter is also presented a methodology for the trimmers design. In chapter 8 are discussed the proposed innovations and some conclusions about the design presented.
Universidade Estadual de Campi
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Colombo, Dalton Martini. "Design of analog integrated circuits aiming characterization of radiation and noise." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/133731.
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Esta tese de doutorado trata de dois desafios que projetistas de circuitos integrados analógicos enfrentam quando estimando a confiabilidade de transistores fabricados em modernos processos CMOS: radiação e ruído flicker. Em relação a radiação, o foco desde trabalho é a Dose Total Ionizante (TID): acumulação de dose ionizante (elétrons e prótons) durante um longo período de tempo nas camadas isolantes dos dispositivos, então resultando na degradação dos parâmetros elétricos (por exemplo, a tensão de limiar e as correntes de fuga). Este trabalho apresenta um caso de estudo composto por circuitos referência tensões de baseados na tensão de bandgap e na tensão de limiar dos transistores. Esses circuitos foram fabricados em uma tecnologia comercial CMOS de 130 nm. Um chip contendo os circuitos foi irradiado usando raio gama de uma fonte de cobalto (60 Co), e o impacto dos efeitos da radiação até uma dose de 490 krad nas tensões de saída é apresentado. Foi verificado que o impacto da radiação foi similar ou até mesmo mais severo que os efeitos causados pelo processo de fabricação para a maior parte dos circuitos projetados. Para as referências baseadas na tensão de bandgap implementadas com transistores de óxido fino e grosso, a variação na tensão de saída causada pela radiação foi de 5.5% e 15%, respectivamente. Para as referências baseadas na tensão de limiar, a variação da tensão de saída foi de 2% a 15% dependendo da topologia do circuito. Em relação ao ruído, o foco desta tese é no ruído flicker do transitor MOS quando este está em operação ciclo-estacionária. Nesta condição, a tensão no terminal da porta está constantemente variando durante a operação e o ruído flicker se torna uma função da tensão porta-fonte e não é precisamente estimado pelos tradicionais modelos de ruído flicker dos transistores MOS. Esta tese apresenta um caso de estudo composto por osciladores de tensão (topologia baseada em anel e no tanque LC) projetados em processos 45 e 130 nm. A frequência de oscilação e sua dependência em relação à polarização do substrato dos transistores foi investigada. Considerando o oscilador em anel, a média da variação da frequência de oscilação causada pela variação da tensão de alimentação e da polarização do substrato foi 495 kHz/mV e 81 kHz/mV, respectivamente. A média da frequência de oscilação é de 103,4 MHz e a média do jitter medido para 4 amostras é de 7.6 ps. Para o tanque LC, a frequência de oscilação medida é de 2,419 GHz e sua variação considerando 1 V de variação na tensão de substrato foi de aproximadamente 0,4 %.This thesis is focused on two challenges faced by analog integrated circuit designers when predicting the reliability of transistors implemented in modern CMOS processes: radiation and noise. Regarding radiation, the concern of this work is the Total Ionizing Dose (TID): accumulation of ionizing dose deposited (electrons and protons) over a long time in insulators leading to degradation of electrical parameters of transistors (e.g. threshold voltage and leakage). This work presents a case-study composed by bandgap-based and threshold voltagebased voltage reference circuits implemented in a commercial 130 nm CMOS process. A chip containing the designed circuits was irradiated through γ-ray Cobalt source (60 Co) and the impact of TID effects up to 490 krad on the output voltages is presented. It was found that the impact of radiation on the output voltage accuracy was similar or more severe than the variation caused by the process variability for most of the case-study circuits. For the bandgap-based reference implemented using thin-oxide and thick-oxide transistors, TID effects result in a variation of the output voltage of 5.5 % and 12%, respectively. For the threshold voltage references, the output variation was between 2% and 15% depending on the circuit topology. Regarding noise, the concern of this work is the transistor flicker noise under cyclostationary operation, that is, when the voltage at transistor gate terminal is constantly varying over time. Under these conditions, the flicker noise becomes a function of VGS; and its is not accurately predicted by traditional transistor flicker noise models. This thesis presents a case-study composed by voltage oscillators (inverter-based ring and LC-tank topologies) implemented in 45 and 130 nm CMOS processes. The oscillation frequency and its dependency on the bulk bias were investigated. Considering the ring-oscillator, the average oscillation frequency variation caused by supply voltage and bulk bias variation are 495 kHz/mV and 81 kHz/mV, respectively. The average oscillation frequency is 103.4 MHz for a supply voltage of 700 mV, and the measured averaged period jitter for 4 measured samples is 7.6 ps. For the LC-tank, the measured oscillation frequency was 2.419 GHz and the total frequency variation considering 1 V of bulk bias voltage was only ~ 0.4 %.
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Cardoso, Adilson Silva. "Design and characterization of BiCMOS mixed-signal circuits and devices for extreme environment applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53099.
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State-of-the-art SiGe BiCMOS technologies leverage the maturity of deep-submicron silicon CMOS processing with bandgap-engineered SiGe HBTs in a single platform that is suitable for a wide variety of high performance and highly-integrated applications (e.g., system-on-chip (SOC), system-in-package (SiP)). Due to their bandgap-engineered base, SiGe HBTs are also naturally suited for cryogenic electronics and have the potential to replace the costly de facto technologies of choice (e.g., Gallium-Arsenide (GaAs) and Indium-Phosphide (InP)) in many cryogenic applications such as radio astronomy. This work investigates the response of mixed-signal circuits (both RF and analog circuits) when operating in extreme environments, in particular, at cryogenic temperatures and in radiation-rich environments. The ultimate goal of this work is to attempt to fill the existing gap in knowledge on the cryogenic and radiation response (both single event transients (SETs) and total ionization dose (TID)) of specific RF and analog circuit blocks (i.e., RF switches and voltage references). The design approach for different RF switch topologies and voltage references circuits are presented. Standalone Field Effect Transistors (FET) and SiGe HBTs test structures were also characterized and the results are provided to aid in the analysis and understanding of the underlying mechanisms that impact the circuits' response. Radiation mitigation strategies to counterbalance the damaging effects are investigated. A comprehensive study on the impact of cryogenic temperatures on the RF linearity of SiGe HBTs fabricated in a new 4th-generation, 90 nm SiGe BiCMOS technology is also presented.
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Austwick, Michael Steven. "Algorithms to determine the positioning of built-in self-test structures in VLSI circuits with references to an economic model." Thesis, University of Hull, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.280838.
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Skalický, Pavel. "Referenční zdroje napětí a proudu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219331.
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The topic of the master´s thesis are voltage and current reference sources. There is detailed description of current and voltage references, which are basic building blocks of many analog circuits, in the theoretical part. Next part of the master´s thesis is the design of a voltage reference source, the design of a voltage reference generating two voltages and a current reference source. The correct function of all circuits have been verified using simulations, especially dependence of the output voltage or current on supply voltage or dependence of the output voltage or current when the ambient temperature is changed.
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Kenyon, Eleazar Walter. "Low-noise circuitry for extreme environment detection systems implemented in SiGe BiCMOS technology." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44873.
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This work evaluates two SiGe BiCMOS technology platforms as candidates for implementing extreme environment capable circuitry, with an emphasis on applications requiring high sensitivity and low noise.
In Chapter 1, applications requiring extreme environment sensing circuitry are briefly reviewed and the motivation for undertaking this study is outlined. A case is then presented for the use of SiGe BiCMOS technology to meet this need, documenting the benefits of operating SiGe HBTs at cryogenic temperatures. Chapter 1 concludes with a brief description of device radiation effects in bipolar and CMOS devices, and a basic overview of noise in semiconductor devices and electronic components.
Chapter 2 further elaborates on a specific application requiring low-noise circuitry capable of operating at cryogenic temperatures and proposes a number of variants of band-gap reference circuits for use in said system. Detailed simulation and theoretical analysis of the proposed circuits are presented and compared with measurements, validating the techniques used in the proposed designs and emphasizing the need for further understanding of device level low-temperature noise phenomena.
Chapter 3 evaluates the feasibility of using a SiGe BiCMOS process, whose response to ionizing radiation was previously uncharacterized, for use in unshielded electronic systems needed for exploration of deep space planets or moons, specifically targeting Europa mission requirements. Measured total ionizing dose (TID) responses for both CMOS and bipolar SiGe devices are presented and compared to similar technologies. The mechanisms responsible for device degradation are outlined, and an explanation of unexpected results is proposed.
Finally, Chapter 4 summarizes the work presented and understanding provided by this thesis, concluding by outlining future research needed to build upon this study and fully realize SiGe based extreme environment capable precision electronic systems.
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Najafizadeh, Laleh. "Design of analog circuits for extreme environment applications." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31796.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Cressler, John; Committee Member: Papapolymerou, John; Committee Member: Shen, Shyh-Chiang; Committee Member: Steffes, Paul; Committee Member: Zhou, Hao Min. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Thomas, Dylan Buxton. "Silicon-germanium devices and circuits for high temperature applications." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33949.
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Using bandgap engineering, silicon-germanium (SiGe) BiCMOS technology effectively combines III-V transistor performance with the cost and integration advantages associated with CMOS manufacturing. The suitability of SiGe technology for cryogenic and radiation-intense environments is well known, yet SiGe has been generally overlooked for applications involving extreme high temperature operation. This work is an investigation into the potential capabilities of SiGe technology for operation up to 300°C, including the development of packaging and testing procedures to enable the necessary measurements. At the device level, SiGe heterojunction bipolar transistors (HBTs), field-effect transistors (FETs), and resistors are verified to maintain acceptable functionality across the temperature range, laying the foundation for high temperature circuit design. This work also includes the characterization of existing bandgap references circuits, redesign for high temperature operation, validation, and further optimization recommendations. In addition, the performance of temperature sensor, operational amplifier, and output buffer circuits under extreme high temperature conditions is presented. To the author's knowledge, this work represents the first demonstration of functional circuits from a SiGe technology platform in ambient temperatures up to 300°C; furthermore, the optimized bandgap reference presented in this work is believed to show the best performance recorded across a 500°C range in a bulk-silicon technology platform.
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Klein, Eloísa Joseane Da Cunha. "Circuitos comunicacionais ativados pela autorreferência didática no jornalismo: o caso do profissão repórter." Universidade do Vale do Rio dos Sinos, 2012. http://www.repositorio.jesuita.org.br/handle/UNISINOS/4473.
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CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
CNPQ – Conselho Nacional de Desenvolvimento Científico e Tecnológico
A pesquisa define-se como um estudo de caso que toma como objeto central o programa televisivo Profissão Repórter, exibido semanalmente desde 2008 pela Rede Globo, às terças-feiras, na faixa de horário das 23h30min, antes do último telejornal de rede. Pelo estudo de caso do Profissão Repórter, a pesquisa efetua a problematização do jornalismo e as interações sociais através dele articuladas, em processo de transformação na sociedade em midiatização. A pesquisa realizada é de base empírica, com acionamento de uma multiplicidade de ângulos para iluminar aspectos específicos do caso estudado e aspectos transversais, que permitem a realização de inferências sobre o contexto social e a inserção na dinâmica televisiva. O Profissão Repórter se constrói como objeto pertinente para observar as transformações na caracterização dos gêneros jornalísticos, tendo em conta a imbricação com lógicas derivadas de gêneros não factuais e associados ao entretenimento. A singularidade de Profissão Repórter está num modelo estrutural organizado por processos autorreferenciais, que endereçam elementos didáticos sobre a atividade jornalística ao espectador.
This research is defined as a case study which takes as its central object the television programme “Profissão Repórter”, aired weekly since 2008 by Rede Globo, on Tuesdays, in the range of 11:30 hours PM, before the last television newscast. For the case study of “Profissão Repórter”, the research studies the journalism and the social interactions articulated in the process of transformation of society in mediatization. The research is empirically based, and highlights specific questions and transversal aspects, which allow inferences about the social context and the dynamic insertion in television. “Profissão Repórter” presents itself as appropriate to observe the changes in the characterization of journalistic genres, taking into account its overlapping with entertainment genres. The uniqueness of Profissão Repórter is a structural model of self-reference, addressing didactic elements on the journalistic activity to the viewer.
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Mothapo, Sentshuhleng Jacob. "Assessing the impact of school governance in the Limpopo Department of Education with specific reference to Mankweng and Polokwane circuits." Thesis, University of Fort Hare, 2011. http://hdl.handle.net/10353/d1007096.
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Education has been identified as a priority area by the South African government, in particular by the African National Congress as the ruling party. To this end, huge amounts of money are being spent on education as a service that has been approved by the legislators. Rules and regulations have been promulgated, and among others, the South African Schools Act, Act No. 84 of 1996, has been enacted. Rich research has also been funded with the sole intention of providing quality education to the people. Education of unacceptably poor quality has, however, been the result, as postulated by Peterson and Hassel (1998:55). The above are attested to by the findings that the political tensions emanating from the conduct of the South African Democratic Teachers’ Union and the Professional Educators’ Union, leading to class disruptions and general instability, erode the ethos of accountability on the part of educators and therefore impact negatively on service delivery. Furthermore, the Limpopo Department of Education is not immune to the challenges ranging from the elements of corrupt activities that often surface, teacher attrition which in the main is caused by lack of discipline. Winkler, Modise and Dawber (1998) indicate that teaching has never been easy, and many teachers are leaving their jobs because of the many problems with children in classrooms. Some of the problems cited are children who do not want to learn and learning that is becoming too difficult for the students because they do not want to listen. This study adopted sequential mixed methods namely, quantitative and qualitative research methods which are viewed as complementary rather than opposing approaches. Information was amassed from the subjects through interviews, observation, documentary survey and observation and the information has since been triangulated to validate the facts. All the methodologies employed proved to be useful in this study. The study sought to test the hypothesis “Good governance is informed by strong accountability and future-oriented organisation, continuously steering it towards its mission and vision, and thereby ensuring that the day-to-day management and administration are always linked with the organisation’s values and goals and thus eventually bringing about effectual and accelerated service delivery” to the South African populace without compromise. After empirically testing the hypothesis, showing mixed reaction informed by the findings of the study, five recommendations were made, based on the conclusions arrived at.
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Noval, Jorge Johanny Sáenz. "Metodologia para a otimização do rendimento e desempenho dos circuitos analógicos usando programação geométrica." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-13062013-114633/.
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Este trabalho propõe uma metodologia de projeto para fabricação ou Design Methodology for Manufacturing (DFM) utilizando a Programação Geométrica (PG) e os métodos tipo Newton para resolver problemas de otimização não-linear, os quais definem e assistem o projeto de circuitos analógicos. Depois, essa metodologia é aplicada e validada através do projeto de uma fonte de referência. Nos últimos anos, a tendência do aumento na densidade de transistores previsto pela lei de Moore tornou o problema do projeto dos circuitos dimensionalmente mais complexo. Além disso, uma maior densidade de transistores implica na diminuição das dimensões características do processo tornando-o mais sensível às variações de processo e as condições ambientais. As diferenças apresentadas entre o circuito projetado e aquele testado dão evidências de perdas de rendimento, as quais são atribuídas numa grande proporção ao processo de projeto. Devido à grande responsabilidade que o projetista tem neste problema, o projeto analógico deve ser focado para novas abordagens que levem em conta o desempenho e o rendimento conjuntamente. Em primeiro lugar, a metodologia proposta obtém um ponto inicial com um conjunto de especificações de desempenho adequadas, o qual vai ser usado na análise do impacto que tem o mismatch e as variações de processo sobre as especificações. Uma vez que o comportamento estatístico e determinístico do circuito foi caracterizado, uma nova estratégia de melhoria de rendimento foi implementada usando PG. A intenção de obter um projeto com um conjunto de especificações de bom desempenho envolve diretamente o rendimento do circuito, pois um conjunto de especificações ótimo obtido através da estrutura típica da PG não garante a obtenção de um projeto comercial e competitivo. Assim, este trabalho estabelece um método de projeto que combina a facilidade na obtenção do ótimo global da Programação Geométrica com uma nova análise de mismatch e de pior caso a qual permitiu uma redução nos tempos de computação mantendo semelhantes os valores de desempenho nominais. Usando a metodologia de projeto para fabricação proposta neste trabalho foi obtido um projeto de uma fonte de referência com um rendimento maior que 37% comparado com uma estratégia de projeto típica, sem nenhuma penalização significativa nas especificações de desempenho.This work proposed a Design Methodology for Manufacturing (DFM) using Geometric Programming (GP) and Newton-like methods to solve non-linear optimization problems, which define and aid the design of analog circuits. Afterwards, this methodology is applied and validated through the design of a voltage reference circuit. Over the last years, the tendency of the increasing on the transistor density predicted by the Moore Law has turned the circuit design problem dimensionally more complex. Additionally, a higher transistor density implies shrinkage on the feature dimensions of the process making it more sensitive to the process variations and environmental conditions. The differences between the designed circuit and the tested one give an evidence of yield losses, which are attributed in a great proportion to the design process. Due to the high responsibility of the designer on this problem, the analog design must be focused on new approaches that jointly manage performance and yield. In first place, the proposed methodology obtain a initial point with a suitable set of performance specifications, which will be used to analyze the impact of the mismatch and process variation over the design specifications. Once the statistical and deterministic behavior of the circuit was characterized, a new yield improvement strategy is implemented using Geometric Programming. Attempting to obtain a design with a set of high performance specifications directly involves the circuit yield, because an optimal performance set obtained by the traditional framework of GP does not assure the obtaining of a marketable and competitive design. So, this works establish a design method that combine the advantage of obtaining global optimum in Geometric Programming with a new mismatch and worst-case analysis that enabled a reduction in their computation time and maintain the initial nominal performance values. Using the design methodology for manufacturing proposed in this work, a voltage reference design with 37% better yield than one obtained with a typical design strategy without any significant penalty on their performance specs was achieved.
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Lobner, Matthew K. (Matthew Kneeland). "Enhancing SPICE model parameters to accurately design and simulate circuits with temperature dependence, with a special emphasis on bandgap references." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36567.
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Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.
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In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.
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Testa, Luca. "Contribution to the Built-In Self-Test for RF VCOs." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14011/document.
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Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/failThis work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC
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ISLAM, MOHAMMAD SAIFUL. "Reconfigurable RF and Wireless Architectures Using Ultra-Stable Micro- and Nano-Electromechanical Oscillators: Emerging Devices, Circuits, and Systems." Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1582167898995604.
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Štibraný, Miroslav. "Řízený laboratorní zdroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-240809.
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Master’s thesis deals with design of laboratory supply with precise voltage and current measuring. At the beginning it presents properties, advantages and disadvantages of linear and switching supplies, based on these facts it chooses a linear type of regulator. The design continues with detailed description of power and control analog and digital circuits. The thesis includes description of taking control over the supply from the front panel or through computer. The last part is devoted to measurement results and to presentation of some static and dynamic parameters of the designed supply.
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Samir, Anass. "Conception de solutions basses puissances et optimisation de la gestion d'énergie de circuits dédiés aux applications mixtes." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4700.
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Depuis trois décennies, la tendance du marché répond à la demande actuelle de miniaturisation et d'augmentation de performances des appareils multimédias. Or, toute réduction des dimensions d'un facteur donné impose une diminution des tensions (pour des raisons de fiabilité). Afin d'y répondre, la réduction de taille des circuits intégrés CMOS atteint des échelles d'intégration submicroniques entrainant une baisse importante de la fiabilité des composants et en particulier des transistors. La création de porteurs chauds, ainsi que la dissipation thermique à l'intérieur des circuits submicroniques, sont les deux phénomènes physiques principaux à l'origine de la baisse de fiabilité. La solution technique permettant de garder un bon degré de fiabilité, tout en réduisant la taille des composants, consiste à réduire la tension d'alimentation des circuits. Parallèlement aux contraintes de performances, les normes environnementales demandent une consommation la plus réduite possible. La difficulté consiste alors en la réalisation de circuits associant une alimentation basse puissance (tension et courant) d'où la notion de circuits " Low Power ". Ces circuits sont pour certains déjà utilisés dans le domaine du multimédia, du médical, avec des contraintes d'intégration différentes (possibilité de composants externes, stabilité, etc.). L'augmentation des performances en vitesse des circuits digitaux nécessite par ailleurs l'utilisation de technologies générant des fuites de plus en plus importantes qui sont incompatibles avec une réduction de la consommation dans des modes de veille sans la mise en place de nouvelles techniquesFor three decades, the market trend answers the current demand of miniaturization and performance increase of the multimedia devices. Yet, any reduction of the dimensions of a given factor imposes a decrease of the tensions (for reasons of reliability). To answer this question, the downsizing of CMOS integrated circuits reaches submicron scales of integration resulting in a significant decrease in the reliability of components and in particular transistors. The hot carriers creations, as well as heat dissipation within the submicron circuits, are the two main physical phenomena behind the reliability decline. The technical solution to maintain a good degree of reliability, while reducing component size, is to reduce the supply voltage of circuits. In parallel to performance constraints, environmental standards require consumption as small as possible. The challenge is then to build circuits combining low power supply (voltage and current) where the concept of circuits "Low Power". These circuits are used for some already in the field of multimedia, medical, integration with various constraints (possibility of external components, stability, etc..). The speed increase performance of digital circuits also requires the use of technologies that generate leaks increasingly important that are inconsistent with consumption reduction in standby modes without the introduction of new techniques
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CHIU, WEI-CHE, and 邱偉哲. "Bandgap reference circuit with digital switch." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/18295605098738865320.
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碩士樹德科技大學
電腦與通訊系碩士班
102
This paper proposes a bandgap reference circuit(BGR) with digital switch. The digital switch can control the current to compensate the mismatches that due to process and temperature vary. The output voltage of proposes BGR circuit is 1.2V and operate temperature form -20~80℃.The BGR circuit with digital switch is using TSMC 0.35μm 2P4M process. The operate voltage is 1.6V~2.8V.
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Chiang, Tzung-Yin, and 江宗殷. "Temperature-compensated CMOS voltage reference circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07003708814603618036.
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碩士國立清華大學
工程與系統科學系
93
Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exists. Another problem worthy of our concern is that spurious signals coming from the supply voltage cannot be adequately rejected and may couple into the circuit to degrade output signal in high frequency applications. This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A current mirror is designed for temperature compensation and large resistors are defeasible for reduction chip area. Besides, it has been implemented by a 0.18 μm CMOS process with a chip area of 0.023 mm2. Simulation shows that the variation of temperature coefficient is from 59.5 to 63.8 ppm/℃ under the temperature range from -40 to 100 ℃ and a supply voltage variation from 1.2 to 1.98 V. The power noise rejection ratio is -70 dB at 10 kHz with 1.2V supply voltage. In summary, the thesis adopts a current mirror to achieve low-temperature-drift reference voltage and abandons large resistances on design consideration. With this approach, power noise rejection ration is reduced.
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Wang, Zhi-Ming, and 王志明. "A Low Power OPless Bandgap Reference Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/60710948837248049085.
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Wang, Jyh-Ming, and 王志明. "A Low Power OPless Bandgap Reference Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/88951317953313398203.
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Wang, Tien-Hsin, and 汪天心. "Improved Low-Power Reference Voltage Circuit Design." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/82yvwp.
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碩士國立虎尾科技大學
電子工程系碩士班
105
In this thesis, four improved Low-Power Reference Voltage Circuits have been proposed. The first circuit used the positive and negative temperature coefficients of the BJT and MOSFET, respectively, to generate the required reference voltage. The second circuit used the positive and negative temperature coefficients of the MOSFET to reach the zero-temperature coefficient reference voltage. The third circuit generated the zero-temperature coefficient reference voltage first and then feedback to the bias circuit to provide the necessary bias currents. The last circuit kept all MOSFET in the circuit to be biased in the weak inversion region. In all the proposed circuits, MOS transistors are biased in the weak inversion region to achieve the low-power consumption characteristics. After that, with proper combination of the positive and the negative temperature coefficients of voltage, the low-power consumption with zero-temperature coefficient reference voltage can be realized. Detailed design principles have been disclosed in this thesis, and the HSPICE simulation program with 0.35-μm process parameters have been used to perform the pre/post-layout simulations. Also the proposed circuits have been taped-out with the same process parameters. The supply voltages of the proposed circuit are 1.7V and 1.8V, respectively. The temperature ranges from -20°C to 120°C. According to the simulation results, when the supply voltage is 1.7V and the temperature is 25°C, the output voltage of the proposed mixed-mode circuit is 448.5mV, the maximum output voltage variation is 0.57mV, the power dissipation is 24.18μW, the corresponding PSRR is -64.9dB, and the temperature coefficient is 8.34ppm/°C. As the supply voltage is 1.8V and the temperature is 25°C, the output voltage of the proposed low-power reference voltage circuit is 657mV, the maximum output voltage variation is 0.23mV, the power dissipation is 1.03μW, the corresponding PSRR is -81dB, and the temperature coefficient is 2.5ppm/°C. The simulation and measurement results are consistent with the theoretic analysis which can prove the validity of the proposed circuits. The proposed circuit can be further used in various analog circuit applications.
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LIN, YI-FANG, and 林毅芳. "Reference voltage circuit design suitable for portable devices." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4ef6eu.
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碩士國立虎尾科技大學
電子工程系碩士班
106
This paper has proposed four different reference voltage circuits which are suitable for portable devices. Without using BJT transistors to implement both negative temperature-coefficients and positive temperature- coefficient voltages, instead, MOS transistors have been applied to all the proposed circuits. Properly biased the MOSFET in weak-inversion region, both the positive and negative temperature-coefficients parameters can be obtained. After choosing appropriate weightings, a zero temperature-coefficient reference voltage can be realized. In the studies, all the proposed circuits use TSMC 0.18 m process parameters to make the layout and taped-out. HSPICE circuit simulation program has been used to perform pre- and post-layout simulations. The first two circuits are connected in series with a NMOS and/or PMOS transistor that is used for providing the negative temperature-coefficient voltage. For the latter two circuits, a P-type transistor and an N-type transistor is connected between the transistors that used to generates the positive temperature coefficient and ground, respectively. According to the pre-layout simulation results, when the supply voltage is 1.8V, the bias voltage varies from 0.39V to 0.45V, and the temperature changes from -20oC to 120oC, the variation of the output voltage of the N-type modified circuit is lower than the P-type one. The proposed circuit is simple, and the power consumption of all the four circuits is less than 10 mW. From the simulation results, it can be seen that the simulation results are consistent with the theoretical derivation, which also proves the feasibility of the design principle. The reference voltage circuits proposed in this paper can be applied to various related analog integrated circuits and other portable devices.
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Pai, Chia-Hung, and 白佳弘. "The curvature compensated Resistorless CMOS Voltage Reference Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/39164561216972109620.
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碩士國立彰化師範大學
電子工程學系
103
This thesis shows a CMOS bandgap reference without resistors, which is an application of PMOS voltage divider. The circuit is operated in 1.8 V. A translinear circuit is used to generate a second-order temperature compensation current, and this current component combined with reference current can decrease output reference voltage temperature coefficient further. The chip is fabricated with TSMC 0.18 µm CMOS technology. The TSMC 0.18 µm 1P6M CMOS models are used in the circuit simulation, and the post-layout simulation results show that: when the supply voltage VDD is 1.8 V and the temperature range is from -40 ℃ to 150 ℃, the average value of output voltage reference is about 484.8 mV, the deviation value is about 2.85 mV, the temperature coefficient is about 31.4 ppm/℃, the power consumption is about 448.9 µW. A 25 dB PSRR has been achieved up to 300 kHz. The measurement result when the supply voltage VDD is 1.8 V and the temperature range is from -40 ℃ to 150 ℃, the average value of output voltage reference is about 444.1 mV, the deviation value is about 57.5 mV, the power consumption is about 344.5 µW, and 20 dB PSRR has been achieved up to 300 kHz.
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黃全興. "CMOS circuit design for low reference voltage using bandgap." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/49468291675147213413.
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碩士國立中興大學
電機工程學系
91
Reference voltage generators are widely used in many applications from analog circuit to mixed-signal circuits such as ADC, DAC, DRAM and flash memories. These structures are required to provide a stable reference voltage with a low sensitivity to temperature and supply voltage. One of the most popular architectures is the band-gap reference. Due to the need of battery-operated systems for portability, low output reference voltage, low supply voltages and low power consumption will be the trends in the future VLSI products. Two new band-gap reference circuits operated at low supply voltages using 0.18m CMOS technology are presented in this thesis. These two circuits are designed by vertically parasitical BJTs in CMOS technology. The chip area of the new BGR circuit is small. The deviation of Vref is less than 12mV for the temperature ranging from —45 oC to 90 oC.
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Liu, Chzung-Tai, and 劉宗泰. "The study of low voltage bandgap voltage reference circuit." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/37524136168903290293.
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Luo, Jing-Yu, and 羅景煜. "Low Power Low Voltage Temperature-Compensation Bandgap Reference Circuit." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/63932569067195146542.
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碩士國立聯合大學
電子工程學系碩士班
95
Reference circuits are the basic building blocks in many analog and digital applications such as A/D and D/A converter, flash memory circuits, and many other circuits. The objective of reference generation is to establish a dc voltage or current that is independent of the supply and fabrication process and has a well-defined behavior with temperature. The properties of reference circuit will not the same with the different demand for characteristics. In this thesis, we will be aimed at the requirement that low power, low voltage and provide with temperature-compensation technique to design this reference circuit. Furthermore, the requirement of low power, low voltage and provide with temperature-compensation technique is especially application in the batter-operated mobile products, such as cellular phones, PDAs, camera recorders, and laptops. In this thesis, these three structures of 「A Low Output Voltage CMOS Bandgap Reference」, 「A Low Supply Voltage Temperature-Compensation CMOS Subbandgap Reference with Two Averaging Circuitry」 and 「A Low Supply Voltage CMOS Subbandgap Reference Using MOSFET Temperature-Compensation technique」 are proposed and implemented. The first and second structures are used of the bipolar transistor and the feedback of differential amplifier to achieve the requirement of temperature-compensation. On the basis of concept for the first and second structures, a new structure of bandgap reference is supported in third structure which difference between first and second structures. The third structure is used of the bias circuit to generate a positive temperature coefficient current and used of a negative temperature coefficient active load to achieve the requirement of temperature-compensation. In this structure, the low supply voltage, low power and low sensitivity with temperature is possibly implemented. This circuit will be implemented in standard TSMC CMOS 0.18um process.
48
Li, Meng Chiao, and 李孟橋. "Study of a high performance, small area reference voltage circuit design and integrating the circuit into power factor correction circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/05831199224524569113.
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碩士東海大學
電機工程學系
100
This paper proposed a simpler bandgap reference circuit and a power factor correction circuit by using TSMC 0.25um CMOS process and TSMC 0.35um CMOS process, which are provided from CIC. The simpler bandgap reference circuit, is different from the traditional structure and it uses a power factor correction circuit to reduce the process induced circuit variation. The output voltage error is within 2% between post-sim and pre-sim result. This circuit does have an excellent stability.
49
Wang, Wei-Shin, and 王惟昕. "Fully-MOSFET Bandgap Voltage Reference Circuit with Self-cascade Architecture." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/vhax89.
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碩士國立彰化師範大學
電子工程學系
107
This thesis presents a fully-MOSFET band-gap voltage reference circuit with low temperature coefficient. The circuit consists of a generator of PTAT, a generator of CTAT and a current source. The generator of PTAT utilize the self-cascade MOSFETs to generate the PTAT voltage, and the generator of CTAT is a MOSFET gate to source voltage, this voltage is a CTAT voltage when the MOSFET is operated in sub-threshold region. We use TSMC 0.18 μm CMOS technology to design the circuit in this thesis. The pre-simulation results are when VDD is at 1.8 V and temperature is ranging from -25 °C to 110 °C, the output voltage is 895 mV, the temperature coefficient is 9.7 ppm/°C, the power consumption is 280.9 nW, and the PSRR is -41.7 dB. Under the same condition, the post-simulation results are as follow: the output voltage is 881 mV, the temperature coefficient is 33 ppm/°C, the power consumption is 239.5 nW, and the PSRR is -41 dB.
50
Hsu, Chao-Hung, and 許肇宏. "A 1.5 ppm/℃ Wide-Temperature-Range CMOS Bandgap Reference Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/51807608514703549352.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
103
In this thesis, the designed circuit is based on the structure of first-order linear temperature compensation bandgap voltage reference circuit, and the circuit generates the current with nonlinear temperature term for curve compensation by using BJT’s current relationship with temperature, IPTAT and ICTAT. Finally, the circuit generates the bandgap reference voltage source which has wide-temperature operation range and low temperature coefficient. The TSMC 0.18 μm 1P6M CMOS models are used in the HSPICE simulation, and Virtuoso is used to implement the circuit layout. The pre-layout and post-layout simulation results are, when supply voltage VDD is 1.5 V and the operation temperature range is from -40 ℃ to 150 ℃. The average value of output reference voltage is 864.84 mV and 864.87 mV, the temperature coefficient is about 1.5 ppm/℃ and 2.3 ppm/℃, the power consumption is about 213.91 μW and 226.07 μW, and the Power Supply Rejection Ratio (PSRR) is about 58 dB and 42 dB at 10 kHz. The measured results of the chip are, when supply voltage VDD is 1.5 V and the operation temperature range is from -40 ℃ to 150 ℃. The temperature coefficient is about 30 ppm/℃, the power consumption is about 220 μW, and the average value of output reference voltage is 875.75 mV