Relevant bibliographies by topics / Reconfiguration Time

Academic literature on the topic 'Reconfiguration Time'

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Published: 14 March 2023

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Journal articles on the topic "Reconfiguration Time"

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Gharbi, Atef, Hamza Gharsellaoui, and Mohamed Khalgui. "Real-Time Reconfigurations of Embedded Control Systems." International Journal of System Dynamics Applications 5, no. 3 (July 2016): 71–93. http://dx.doi.org/10.4018/ijsda.2016070104.

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This paper deals with the study of the reconfiguration of embedded control systems with safety following component-based approaches from the functional level to the operational level. The authors define the architecture of the Reconfiguration Agent which is modelled by nested state machines to apply local reconfigurations. They propose in this journal paper technical solutions to implement the whole agent-based architecture, by defining UML meta-models for both Control Components and also agents. To guarantee safety reconfigurations of tasks at run-time, they define service and reconfiguration processes for tasks and use the semaphore concept to ensure safety mutual exclusions. As a method to ensure the scheduling between periodic tasks with precedence and mutual exclusion constraints, the authors apply the priority ceiling protocol.
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Gharsellaoui, Hamza, Mohamed Khalgui, and Samir Ben Ahmed. "Reconfiguration of Synchronous Real-Time Operating System." International Journal of System Dynamics Applications 2, no. 1 (January 2013): 114–32. http://dx.doi.org/10.4018/ijsda.2013010106.

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Real-time scheduling is the theoretical basis of real-time systems engineering. Earliest Deadline first (EDF) is an optimal scheduling algorithm for uniprocessor real-time systems. The paper deals with Reconfigurable Uniprocessor embedded Real-Time Systems classically implemented by different OS tasks that the authors suppose independent, synchronous and periodic to meet functional and temporal properties described in user requirements. They define two forms of automatic reconfigurations which are applied at run-time: Addition-Remove of tasks or just modifications of their temporal parameters: WCET and/or Periods. The authors define a new semantic of the reconfiguration where a crucial criterion to consider is the automatic improvement of the system’s feasibility at run-time by using an Intelligent Agent that automatically checks the system’s feasibility after any reconfiguration scenario to verify if all tasks meet the required deadlines. To handle all possible reconfiguration solutions, the authors propose an agent-based architecture that applies automatic reconfigurations to re-obtain the system’s feasibility and satisfy user requirements. Therefore, they developed the tool RT-Reconfiguration to support these contributions that they apply on the running example system and the authors apply the Real-Time Simulator, Cheddar to check the whole system behavior and evaluate the performance of the algorithm. They present simulations of this architecture where the agent that implemented is evaluated.
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Li, Ji, Huagang Xiong, Qiao Li, Feng Xiong, and Jiaying Feng. "Run-Time Reconfiguration Strategy and Implementation of Time-Triggered Networks." Electronics 11, no. 9 (May 5, 2022): 1477. http://dx.doi.org/10.3390/electronics11091477.

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Time-triggered networks are deployed in avionics and astronautics because they provide deterministic and low-latency communications. Remapping of partitions and the applications that reside in them that are executing on the failed core and the resulting re-routing and re-scheduling are conducted when a permanent end-system core failure occurs and local resources are insufficient. We present a network-wide reconfiguration strategy as well as an implementation scheme, and propose an Integer Linear Programming based joint mapping, routing, and scheduling reconfiguration method (JILP) for global reconfiguration. Based on scheduling compatibility, a novel heuristic algorithm (SCA) for mapping and routing is proposed to reduce the reconfiguration time. Experimentally, JILP achieved a higher success rate compared to mapping-then-routing-and-scheduling algorithms. In addition, relative to JILP, SCA/ILP was 50-fold faster and with a minimal impact on reconfiguration success rate. SCA achieved a higher reconfiguration success rate compared to shortest path routing and load-balanced routing. In addition, scheduling compatibility plays a guiding role in ILP-based optimization objectives and ‘reconfigurable depth’, which is a metric proposed in this paper for the determination of the reconfiguration potential of a TT network.
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Loukil, Sihem, Slim Kallel, and Mohamed Jmaiel. "Managing Architectural Reconfiguration at Runtime." International Journal of Web Portals 5, no. 1 (January 2013): 55–72. http://dx.doi.org/10.4018/jwp.2013010105.

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Managing dynamic reconfiguration of software systems is a tedious task in the software development because of the substantially increasing need for continuously available systems even at runtime. In particular, the software architecture of dynamically adaptive systems must continuously adapt to varying environmental conditions and user requirements. Therefore, they propose a wide range of possible configurations. The static enumeration of all the possible configurations is a difficult task. Moreover, not all dynamic reconfiguration operations can be foreseen at design time. Some reconfigurations may appear when the system is already deployed. In this context, we propose to combine the Architecture Description Languages and the Aspect-Oriented Software Development paradigm in order to make the dynamic reconfiguration process easier to design, understand and possible to validate. Also, this combination allows to easily evolving the reconfiguration policies even at runtime.
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Marx, Clare. "Time for service redesign?" Bulletin of the Royal College of Surgeons of England 98, no. 3 (March 2016): 101. http://dx.doi.org/10.1308/rcsbull.2016.101.

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Wanta, Damian, Waldemar T. Smolik, Jacek Kryszyn, Przemysław Wróblewski, and Mateusz Midura. "A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System." Electronics 11, no. 4 (February 11, 2022): 545. http://dx.doi.org/10.3390/electronics11040545.

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A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA partial reconfiguration is described, in which a PicoBlaze soft-core processor is used as a reconfiguration controller. Behavioral reconfiguration of the system is obtained by providing run-time access to the program code of a soft-core control processor. The tests using EVT4 hardware and different algorithms for tomographic scanning were performed. A test object was measured using 2D and 3D sensors. The time and resources required for the examined reconfiguration procedure are evaluated.
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Steinhauser, Marco, Martin E. Maier, and Benjamin Ernst. "Neural correlates of reconfiguration failure reveal the time course of task-set reconfiguration." Neuropsychologia 106 (November 2017): 100–111. http://dx.doi.org/10.1016/j.neuropsychologia.2017.09.018.

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Muhammad Ridzuan, Mohd, and Sasa Djokic. "Energy Regulator Supply Restoration Time." Energies 12, no. 6 (March 19, 2019): 1051. http://dx.doi.org/10.3390/en12061051.

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In conventional reliability analysis, the duration of interruptions relied on the input parameter of mean time to repair (MTTR) values in the network components. For certain criteria without network automation, reconfiguration functionalities and/or energy regulator requirements to protect customers from long excessive duration of interruptions, the use of MTTR input seems reasonable. Since modern distribution networks are shifting towards smart grid, some factors must be considered in the reliability assessment process. For networks that apply reconfiguration functionalities and/or network automation, the duration of interruptions experienced by a customer due to faulty network components should be addressed with an automation switch or manual action time that does not exceed the regulator supply restoration time. Hence, this paper introduces a comprehensive methodology of substituting MTTR with maximum action time required to replace/repair a network component and to restore customer duration of interruption with maximum network reconfiguration time based on energy regulator supply requirements. The Monte Carlo simulation (MCS) technique was applied to medium voltage (MV) suburban networks to estimate system-related reliability indices. In this analysis, the purposed method substitutes all MTTR values with time to supply (TTS), which correspond with the UK Guaranteed Standard of Performance (GSP-UK), by the condition of the MTTR value being higher than TTS value. It is nearly impossible for all components to have a quick repairing time, only components on the main feeder were selected for time substitution. Various scenarios were analysed, and the outcomes reflected the applicability of reconfiguration and the replace/repair time of network component. Theoretically, the network reconfiguration (option 1) and component replacement (option 2) with the same amount of repair time should produce exactly the same outputs. However, in simulation, these two options yield different outputs in terms of number and duration of interruptions. Each scenario has its advantages and disadvantages, in which the distribution network operators (DNOs) were selected based on their operating conditions and requirements. The regulator reliability-based network operation is more applicable than power loss-based network operation in counties that employed energy regulator requirements (e.g., GSP-UK) or areas with many factories that required a reliable continuous supply.
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Klimenko, A. B. "A Technique of the Distributed Information Systems Control Method Choice under the High Network Dynamics Conditions." Proceedings of the Southwest State University 26, no. 1 (June 28, 2022): 57–72. http://dx.doi.org/10.21869/2223-1560-2022-26-1-57-72.

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Purpose of research. The purpose of this study is to select a method for managing a distributed system, which, based on known parameters, would reduce the consumption of resources of computing devices. The resource of an information system is understood as the probability of failure-free operation (reliability function), which degrades over time for each node, the faster, the higher its workload.Methods. Considering that with high dynamics of the edge layer of the network, the frequency of system reconfigurations becomes relatively high, and the need for reconfigurations is unpredictable, reducing the total time spent on reconfigurations makes it possible to increase the time spent on solving functional computational problems of the system and thereby reduce the load of nodes. The reconfiguration time can be reduced both by reducing the time for detecting a failure in a distributed system, and by reducing the new configuration forming time. In this paper, a method for reducing the time of the failure detection is considered. The analysis of the applicability of system control methods (centralized, with a distributed leader, decentralized) is based on the obtained analytical estimates of the time the system detects a failure under control conditions using one method or another. A numerical experiment makes it possible to identify areas of system parameters, where it is preferable to use the method with a distributed leader.Results. The main result of this work is a methodology for choosing a method for managing distributed information systems in conditions of high dynamics of the network infrastructure, focused on reducing the consumption of resources of computing devices.Conclusion. System reconfiguration time can be shortened by choosing the most appropriate control method. Thus, the time allotted for solving the functional tasks of the application increases, the workload of the computational nodes decreases, and, therefore, the FBG values increase over the planning horizon.
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Grethlein, J. "The Narrative Reconfiguration of Time beyond Ricoeur." Poetics Today 31, no. 2 (May 25, 2010): 313–29. http://dx.doi.org/10.1215/03335372-2009-022.

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Dissertations / Theses on the topic "Reconfiguration Time"

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Thompson, Dean (Dean Barrie) 1974. "Dynamic reconfiguration under real-time constraints." Monash University, School of Computer Science and Software Engineering, 2002. http://arrow.monash.edu.au/hdl/1959.1/7991.

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Parrott, Curtis Alan. "Real-time reconfiguration of programmable logic controller communication paths." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Parrott_09007dcc806c2c91.pdf.

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Thesis (M.S.)--Missouri University of Science and Technology, 2009.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 17, 2009) Includes bibliographical references (p. 53).
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Bowen, John Kipp. "Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/31088.

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Modern Field Programmable Gate Arrays (FPGAs) can implement entire run-time reconfigurable systems using partial reconfiguration. Module-based run-time reconfiguration permits the construction of custom applications at run-time using pre-compiled Intellectual Property (IP) from a module library. The need for both flexible module placement and custom inter-module communication is mostly ignored by existing modular run-time reconfiguration approaches and few existing tool flows for module generation address the need for automation. This thesis introduces an automated compile-time tool flow for generating dynamic modules that allow flexible run-time placement and communication synthesis.
Master of Science
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Hansen, Sindre. "Self Reconfiguration of Clock Networks on FPGA : Methodology for partial reconfiguration of synchronous modules at run-time." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13641.

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In this thesis, methodology for partial self-reconfiguration of synchronous modules has been developed. A simple software-based scheduler has been built for scheduling synchronous modules on the FPGA. The motivation behind this was that partial reconfiguration of synchronous modules at run-time had not been performed earlier in the AHEAD-project. Also, the project report written by the same author as this thesis has shown that a synchronous module can be replaced in a bitfile. However, the project report did not perform this reconfiguration at run-time.Based on the project report, the problem has been decomposed and simple tests using clocked flip-flop designs have been performed on the FPGA. These tests forms a proof-of-concept for partial self-reconfiguration of synchronous modules on the Virtex-4 FPGA. However, the tests also showed that the reconfiguration time was quite high. It took several seconds to write one partial bitstream to the configuration memory.Vegard Endresen has previously made a backend module for data transfer between the HWOS and a reconfigurable module. Experiments were performed in this thesis to see if the clocking methodology could be integrated into this backend module. The module could be built with the methodology, but a running solution on the FPGA was not shown.The software part of the HWOS was rewritten from scratch as the previous version was not thoroughly analyzed. A round-robin scheduler using priority queues has been implemented. A test-driven development technique has been used for development, hopefully making the system more robust. The scheduler is a part of a daemon running on the embedded system, where a message server handles requests for new processes and a placer places new tasks on the FPGA. The complete system was initially based on ideas and code developed by Sverre Hamre and Vegard Endresen in previous AHEAD-projects.
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Guo, Guanghao. "Evaluation of FPGA Partial Reconfiguration : for real-time Vision applications." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279957.

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The usage of programmable logic resources in Field Programmable Gate Arrays, also known as FPGAs, has increased a lot recently due to the complexity of the algorithms, especially for some computer vision algorithms. Due to this reason, sometimes the hardware resources in the FPGA are not sufficient. Partial reconfiguration provides us with the possibility to solve this problem. Partial reconfiguration is a technique that can be used to reconfigure specific parts of the FPGA during run-time. By using this technique, we can reduce the need for programmable logic resources. This master thesis project aims to design a software framework for partial reconfiguration that can load a set of processing components/algorithms (e.g. object detection, optical flow, Harris-Corner detection etc) in the FPGA area without affecting real-time static components such as camera capture, basic image filtering and colour conversion which are continuously running. Partial reconfiguration has been applied to two different video processing pipelines, a direct streaming architecture and a frame buffer streaming architecture respectively. The result shows that reconfiguration time is predictable which depends on the partial bitstream size, and that partial reconfiguration can be used in real-time applications taking the partial bitstream size and the frequency to switch the partial bitstreams into account.
Användningen av programmerbara logiska resurser i Field Programmable Gate Arrayer, även känd som FPGA:er, har ökat mycket nyligen på grund av komplexiteten hos algoritmerna, speciellt för vissa datorvisningsalgoritmer. På grund av detta är det ibland inte tillräckligt med hårdvaruresurser i FPGA:n. Partiell omkonfiguration ger oss möjlighet att lösa detta problem. Partiell omkonfigurering är en teknik som kan användas för att omkonfigurera specifika delar av FPGA:n under körtid. Genom att använda denna teknik kan vi minska behovet av programmerbara logiska resurser. Det här mastersprojektet syftar till att utforma ett programvaru-ramverk för partiell omkonfiguration som kan ladda en uppsättning processkomponenter / algoritmer (t.ex. objektdetektering, optiskt flöde, Harris-Corner detection etc) i FPGA- området utan att påverka statiska realtids-komponenter såsom kamerafångst, grundläggande bildfiltrering och färgkonvertering som körs kontinuerligt. Partiell omkonfiguration har tillämpats på två olika videoprocessnings-pipelines, en direkt-strömmande respektive en rambuffert-strömmande arkitektur. Resultatet visar att omkonfigurationstiden är förutsägbar och att partiell omkonfiguration kan användas i realtids-tillämpningar.
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Khan, Asif H. "Analysis of time varying load for minimum loss distribution reconfiguration." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-06062008-171313/.

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Heron, Jean-Paul Stephen. "Design and implementation of reconfigurable DSP circuit architectures on FPGA." Thesis, Queen's University Belfast, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.266712.

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Puett, Ronnie Douglas. "Reconfiguration in robust distributed real-time systems based on global checkpoints." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26720.

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Mahmood, Waqar. "Intelligent modeling for control, reconfiguration and optimization of discrete event systems." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/15014.

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Ballagh, Jonathan Bartlett. "An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/33649.

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FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform. The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are presented, including speed of operation, resource consumption, and reconfiguration overhead times.
Master of Science
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Books on the topic "Reconfiguration Time"

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. Dynamic Reconfiguration in Real-Time Systems. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-0278-7.

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John, Rushby, and Langley Research Center, eds. Model-based reconfiguration: Diagnosis and recovery. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1994.

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Crow, Judy. Model-based reconfiguration: Diagnosis and recovery. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1994.

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Puett, Ronnie Douglas. Reconfiguration in robust distributed real-time systems based on global checkpoints. Monterey, Calif: Naval Postgraduate School, 1991.

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Wang, Weixun. Dynamic Reconfiguration in Real-Time Systems: Energy, Performance, and Thermal Perspectives. New York, NY: Springer New York, 2013.

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Model-based reconfiguration: Diagnosis and recovery. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1994.

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Dynamic Reconfiguration in RealTime Systems Embedded Systems. Springer, 2012.

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Mishra, Prabhat, Weixun Wang, and Sanjay Ranka. Dynamic Reconfiguration in Real-Time Systems: Energy, Performance, and Thermal Perspectives. Springer New York, 2014.

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Peterson, Derek R. The East African Revival. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780199643011.003.0010.

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The East African Revival was a Christian conversion movement that began in northern Rwanda and southern Uganda in the mid-1930s and spread throughout eastern Africa during the 1940s and 1950s. Learning from Bunyan’s Pilgrim’s Progress—which was foundational literature in Anglican mission stations—converts engaged in radical acts of self-editing. They disavowed kin relationships, disposed of their possessions, and confessed their sins without regard to propriety. Other Christians thought them a menace to the whole social order. This chapter studies the contentious process by which the Revival was domesticated. Through the reconfiguration of legal codes, by the operation of church discipline, heedless converts were, over time, made members of civil society. There was a great amount of disciplinary work that had to occur before the Revival could safely become a source of inspiration in the field of World Christianity.
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Hermann, Elfriede, and Jeannette Mageo. Mimesis and Pacific Transcultural Encounters: Making Likenesses in Time, Trade, and Ritual Reconfigurations. Berghahn Books, Incorporated, 2017.

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Book chapters on the topic "Reconfiguration Time"

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Sahlbach, Henning, Wolfram Putzke-Röming, Sean Whitty, and Rolf Ernst. "Real-Time Digital Film Processing." In Dynamic System Reconfiguration in Heterogeneous Platforms, 185–93. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-2427-5_14.

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Heyse, Karel, Brahim Al Farisi, Karel Bruneel, and Dirk Stroobandt. "Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration." In Lecture Notes in Computer Science, 1–12. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28365-9_1.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Dynamic Cache Reconfiguration in Real-Time Systems." In Dynamic Reconfiguration in Real-Time Systems, 23–61. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_3.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Modeling of Real-Time and Reconfigurable Systems." In Dynamic Reconfiguration in Real-Time Systems, 15–22. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_2.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Introduction." In Dynamic Reconfiguration in Real-Time Systems, 1–13. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_1.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Energy Optimization of Cache Hierarchy in Multicore Real-Time Systems." In Dynamic Reconfiguration in Real-Time Systems, 63–84. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_4.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Energy-Aware Scheduling with Dynamic Voltage Scaling." In Dynamic Reconfiguration in Real-Time Systems, 85–127. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_5.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "System-Wide Energy Optimization with DVS and DCR." In Dynamic Reconfiguration in Real-Time Systems, 129–63. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_6.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Temperature- and Energy-Constrained Scheduling." In Dynamic Reconfiguration in Real-Time Systems, 165–92. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_7.

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Wang, Weixun, Prabhat Mishra, and Sanjay Ranka. "Conclusions." In Dynamic Reconfiguration in Real-Time Systems, 193–95. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0278-7_8.

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Conference papers on the topic "Reconfiguration Time"

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Bittner, Ray, and Peter Athanas. "Wormhole run-time reconfiguration." In the 1997 ACM fifth international symposium. New York, New York, USA: ACM Press, 1997. http://dx.doi.org/10.1145/258305.258315.

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Ciobanu, Cătălin Bogdan, Dionisios N. Pnevmatikatos, Kyprianos D. Papadimitriou, and Georgi N. Gaydadjiev. "FASTER run-time reconfiguration management." In the 27th international ACM conference. New York, New York, USA: ACM Press, 2013. http://dx.doi.org/10.1145/2464996.2467283.

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Sadeghi, Misha, Seyyed Ahmad Razavi, and Morteza Saheb Zamani. "Reducing Reconfiguration Time in FPGAs." In 2019 27th Iranian Conference on Electrical Engineering (ICEE). IEEE, 2019. http://dx.doi.org/10.1109/iraniancee.2019.8786689.

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Abel, Norbert, Sebastian Manz, Frederik Grull, and Udo Kebschull. "Increasing design changeability using dynamical partial reconfiguration." In 2009 16th IEEE-NPSS Real Time Conference (RT). IEEE, 2009. http://dx.doi.org/10.1109/rtc.2009.5321694.

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Tseng, Shih-Hao, Chiun Lin Lim, Ning Wu, and Ao Tang. "Time-aware congestion-free routing reconfiguration." In 2016 IFIP Networking Conference (IFIP Networking) and Workshops. IEEE, 2016. http://dx.doi.org/10.1109/ifipnetworking.2016.7497252.

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Dittmann, Florian, and Stefan Frank. "Hard Real-Time Reconfiguration Port Scheduling." In Design, Automation & Test in Europe Conference. IEEE, 2007. http://dx.doi.org/10.1109/date.2007.364578.

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Nahas, Carlos, Ricardo Guevara, and Voicu Groza. "Temporal Placement for Run-Time Reconfiguration." In 2006 Canadian Conference on Electrical and Computer Engineering. IEEE, 2006. http://dx.doi.org/10.1109/ccece.2006.277750.

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Shariatzadeh, F., R. Zamora, and A. K. Srivastava. "Real time implementation of microgrid reconfiguration." In 2011 North American Power Symposium (NAPS 2011). IEEE, 2011. http://dx.doi.org/10.1109/naps.2011.6025181.

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"Self recovery and real time reconfiguration." In 2011 9th IEEE International Conference on Industrial Informatics (INDIN). IEEE, 2011. http://dx.doi.org/10.1109/indin.2011.6034927.

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Guccione, Steven A., and Delon Levi. "Design advantages of run-time reconfiguration." In Photonics East '99, edited by John Schewel, Peter M. Athanas, Steven A. Guccione, Stefan Ludwig, and John T. McHenry. SPIE, 1999. http://dx.doi.org/10.1117/12.359527.

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Reports on the topic "Reconfiguration Time"

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Shackleton, John. Adapters: A Domain-Specific Programming and Development Technology for Run-Time Reconfiguration at the System Level. Fort Belvoir, VA: Defense Technical Information Center, July 2001. http://dx.doi.org/10.21236/ada400168.

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Faltens, A. Time Delays, Bends, Acceleration and Array Reconfigurations. Office of Scientific and Technical Information (OSTI), June 2011. http://dx.doi.org/10.2172/1050721.

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Fernandez-Stark, Karina, Penny Bamber, and Vivian Couto. Analysis of the Textile and Clothing Industry Global Value Chains. Inter-American Development Bank, December 2022. http://dx.doi.org/10.18235/0004638.

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Abstract:
The textile and apparel industry is a highly globalized, multi-trillion-dollar sector. Today, production networks are dominated by low-cost Asian countries with very large labor-pools, which has made it increasingly difficult for other producers around the world to compete, including those in Latin America and the Caribbean (LAC). While the region has participated in the industry, there are currently no LAC countries amongst the leading ten exporters. The COVID-19 pandemic, together with rising geopolitical tensions between the US and China, however, has disrupted this well-established business model over the past two to three years. This creates the most significant opportunity of the past decade to reconfigure the geography of the supply chain; as a small, but long-term supplier, with proximity to the worlds largest single market, Central America is well-positioned to benefit from these changes. Nonetheless, the region needs to upgrade various aspects of their GVC participation in order to become a serious contender in the reconfiguration of the industry. Key policies should focus on developing human capital through industry-specific training initiatives; intensifying investment attraction efforts; and aggressively investing in both hard and soft infrastructure to reduce barriers to trade and enhance lead time responsiveness.
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Fernandez-Stark, Karina, Penny Bamber, and Vivian Couto. Analysis of the Textile and Clothing Industry Global Value Chains: Summary. Inter-American Development Bank, December 2022. http://dx.doi.org/10.18235/0004663.

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Abstract:
The textile and apparel industry is a highly globalized, multi-trillion-dollar sector. Today, production networks are dominated by low-cost Asian countries with very large labor-pools, which has made it increasingly difficult for other producers around the world to compete, including those in Latin America and the Caribbean (LAC). While the region has participated in the industry, there are currently no LAC countries amongst the leading ten exporters. The COVID-19 pandemic, together with rising geopolitical tensions between the US and China, however, has disrupted this well-established business model over the past two to three years. This creates the most significant opportunity of the past decade to reconfigure the geography of the supply chain; as a small, but long-term supplier, with proximity to the worlds largest single market, Central America is well-positioned to benefit from these changes. Nonetheless, the region needs to upgrade various aspects of their GVC participation in order to become a serious contender in the reconfiguration of the industry. Key policies should focus on developing human capital through industry-specific training initiatives; intensifying investment attraction efforts; and aggressively investing in both hard and soft infrastructure to reduce barriers to trade and enhance lead time responsiveness.
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