Journal articles: 'Reconfiguration overhead'

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Hoffman, John C., and Marios S. Pattichis. "A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback." International Journal of Reconfigurable Computing 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/439072.

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Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead. To minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the reconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively limits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the system can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of overclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and temperature are within nominal operating conditions. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5, consists of four different hardware platforms.

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JUNG, S., and T. G. KIM. "Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration." IEICE Transactions on Information and Systems E91-D, no. 11 (November 1, 2008): 2675–84. http://dx.doi.org/10.1093/ietisy/e91-d.11.2675.

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Sungjoon Jung and Tag Gon Kim. "An Operation and Interconnection Sharing Algorithm for Reconfiguration Overhead Reduction Using Static Partial Reconfiguration." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 12 (December 2008): 1589–95. http://dx.doi.org/10.1109/tvlsi.2008.2000973.

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CHOU, Kuan-Hung, and Woei LIN. "Performance Analysis of Optical Packet Switches with Reconfiguration Overhead." IEICE Transactions on Communications E94-B, no. 6 (2011): 1640–47. http://dx.doi.org/10.1587/transcom.e94.b.1640.

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KIM, J., J. CHO, and T. G. KIM. "Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures." IEICE Transactions on Information and Systems E90-D, no. 12 (December 1, 2007): 1977–85. http://dx.doi.org/10.1093/ietisy/e90-d.12.1977.

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BELAID, IKBEL, BASSEM OUNI, FABRICE MULLER, and MAHER BENJEMAA. "COMPLETE AND APPROXIMATE METHODS FOR OFF-LINE PLACEMENT OF HARDWARE TASKS ON RECONFIGURABLE DEVICES." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250080. http://dx.doi.org/10.1142/s0218126612500806.

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With the advent of run-time partial reconfiguration, the most recent reconfigurable devices support reconfiguring hardware tasks individually, without interrupting the remaining tasks running on the same device. While the concept of run-time partial reconfiguration increases performance and resource utilization, it also leads to resource wastage, high configuration overhead and complex allocation situations of hardware tasks on reconfigurable devices. Many on-line and off-line methods for hardware task placement have been proposed for such reconfigurable devices to enhance placement quality expressed by fragmentation rate, the amount of task rejection and a few of them also estimate configuration overhead. However, these works treat each criterion individually and therefore do not reflect the overall metrics of placement quality. Hardware task placement is a multi-objective combinatory optimization problem. In this paper, we investigate the problem of off-line placement of hardware tasks in partially reconfigurable devices and we present a new three-level resource management that is based on two methods, i.e., a complete analytic method: the formulation into mixed integer programming, and an approximate iterative method: the Bees algorithm. For both methods, the placement quality is measured by the rate of resource efficiency and by the amount of configuration overhead. Experiments demonstrate that the analytic method provides better resource efficiency than the Bees Algorithm by 33% and attains 15% of gain in configuration overhead.

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Koch, Dirk, Christian Beckhoff, and Jim Torresen. "Efficient Interfacing of Partially Reconfigurable Instruction Set Extensions for Softcore CPUs on FPGAs." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 35–42. http://dx.doi.org/10.29292/jics.v6i1.336.

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Swapping just small fractions of the configuration of an FPGA can be very beneficial in many applications. This is in particular useful for reconfiguring the instruction set of embedded soft core processors. In this paper, we will sketch that present design techniques include a substantial overhead for integrating reconfigurable parts into the rest of the system. This overhead can cost more logic resources than the actual module implementations. For removing this overhead, we propose a novel technique to constrain the communication resources between the static system and the partial regions.We will demonstrate for a reconfigurable soft core processor that instructions can be integrated into the system without causing any additional logic overhead for the communication. In addition, we reveal how such systems can be easily implemented with our tool ReCoBus-Builder. Furthermore, we will analyze the overhead in terms of reconfiguration time and present a metric helping to take design decisions.

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KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

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Feng, Xiao Jing, Xi Li, Wang Chao, Xue Hai Zhou, and Jun Neng Zhang. "A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration." Advanced Materials Research 433-440 (January 2012): 5172–77. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5172.

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The strict requirements on both performance and flexibility lead us to apply Dynamic Partial Reconfiguration (DPR) technology in embedded systems. However, existing DPR design flows are still immature, since previous works mainly focus on hardware designs while ignore software designs for DPR. To remedy this weakness, this paper proposes a hardware/software (HW/SW) co-design flow for DPR. The co-design flow aims at accelerating the process of DPR designs, and it merges software and hardware design flows to make them operate in parallel. Besides, in order to validate the effectiveness of our co-design flow, we implement a partial self-reconfigurable prototype system on Xilinx Virtex-5 platform and perform a set of experiments. Experimental results present that the reconfiguration overhead for partial reconfiguration is only 4.66% against global reconfiguration in our prototype. It’s also presented that our prototype can achieve a 23.6 × speedup over software algorithm solutions.

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Lallet, Julien, Sébastien Pillement, and Olivier Sentieys. "Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures." Journal of Integrated Circuits and Systems 4, no. 1 (November 21, 2009): 36–44. http://dx.doi.org/10.29292/jics.v4i1.295.

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Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.

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Jamali, Vahid, George C. Alexandropoulos, Robert Schober, and H. Vincent Poor. "Low-to-Zero-Overhead IRS Reconfiguration: Decoupling Illumination and Channel Estimation." IEEE Communications Letters 26, no. 4 (April 2022): 932–36. http://dx.doi.org/10.1109/lcomm.2022.3141206.

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He, Xiangyue, Haiyang Li, Luyi Yang, and Jian Zhao. "Reconfigurable Satellite Constellation Design for Disaster Monitoring Using Physical Programming." International Journal of Aerospace Engineering 2020 (September 1, 2020): 1–15. http://dx.doi.org/10.1155/2020/8813685.

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Data collection by satellites during and after a natural disaster is of great significance. In this work, a reconfigurable satellite constellation is designed for disaster monitoring, and satellites in the constellation are made to fly directly overhead of the disaster site through orbital transfer. By analyzing the space geometry relations between satellite orbit and an arbitrary disaster site, a mathematical model for orbital transfer and overhead monitoring is established. Due to the unpredictability of disasters, target sites evenly spaced on the Earth are considered as all possible disaster scenarios, and the optimal reconfigurable constellation is designed with the intention to minimize total velocity increment, maximum and mean reconfiguration time, and standard deviation of reconfiguration times for all target sites. To deal with this multiobjective optimization, a physical programming method together with a genetic algorithm is employed. Numerical results are obtained through the optimization, and different observation modes of the reconfigurable constellation are analyzed by a specific case. Superiority of our design is demonstrated by comparing with the existing literature, and excellent observation performance of the reconfigurable constellation is demonstrated.

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Chou, Kuan-Hung, and Woei Lin. "An analytical model for input-buffered optical packet switches with reconfiguration overhead." Photonic Network Communications 22, no. 3 (July 7, 2011): 209–20. http://dx.doi.org/10.1007/s11107-011-0320-4.

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Tomovic, Slavica, and Igor Radusinovic. "Dynamic optimization of load-balancing and reconfiguration overhead in SD-ISP networks." Telfor Journal 11, no. 1 (2019): 8–13. http://dx.doi.org/10.5937/telfor1901008t.

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Tomovic, Slavica, and Igor Radusinovic. "RO-RO: Routing Optimality - Reconfiguration Overhead Balance in Software-Defined ISP Networks." IEEE Journal on Selected Areas in Communications 37, no. 5 (May 2019): 997–1011. http://dx.doi.org/10.1109/jsac.2019.2906762.

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Duhem, F., F. Muller, and P. Lorenzini. "Reconfiguration time overhead on field programmable gate arrays: reduction and cost model." IET Computers & Digital Techniques 6, no. 2 (2012): 105. http://dx.doi.org/10.1049/iet-cdt.2011.0033.

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He, Pan, Gang Liu, and Yue Yuan. "An Adaptive Reconfiguration Mechanism for Periodic Software Rejuvenation based on Transient Reliability Analysis." MATEC Web of Conferences 232 (2018): 03045. http://dx.doi.org/10.1051/matecconf/201823203045.

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While software rejuvenation is used to prevent severe software failures, existing researches generally choose the constant-value periodic policy through steady-state reliability optimization. Since the software reliability declines with the execution time, a steady policy either introduces extra overhead or could not guarantee the reliability constraints. So an adaptive mechanism is proposed to reconfigure the software rejuvenation in the runtime. The transient reliability analysis is used to choose an optimal rejuvenation policy which maintains the software reliability for a certain period of time. A dynamic time series is generated for the reconfiguration process and the optimal rejuvenation policy is re-calculated according to the reconfiguration intervals during the software execution. Experimental studies results show that as the execution time increases, the software reliability drops continuously and the optimal rejuvenation interval should be decreased to maintain the same reliability constraints. This mechanism guarantees the software reliability constraint by resetting the optimal rejuvenation policy dynamically according to a reconfiguration interval time series.

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Soumya, J., K. Niranjan Babu, and Santanu Chattopadhyay. "Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture." Journal of Circuits, Systems and Computers 26, no. 11 (April 27, 2017): 1750174. http://dx.doi.org/10.1142/s0218126617501742.

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This paper presents a reconfigurable architecture for Network-on-Chip (NoC) design based on configuration switches. Reconfiguration is achieved by varying connection pattern between routers, depending on the currently running application. Mapping and reconfiguration strategies have been developed for the proposed architecture. In the mapping phase, cores in the combined application set are mapped to individual routers, minimizing the overall communication cost. In the second phase, for each application, configuration information for the switches (between the routers) are generated to optimize the communication cost further to suit the corresponding application. Exact methods, based on Integer Linear Programming (ILP), have been proposed for both the phases. Since ILP takes a large amount of CPU time, Particle Swarm Optimization (PSO)-based approaches have also been developed. The architecture and mapping strategies have been evaluated against benchmarks, considering communication cost, throughput, latency and network energy before and after reconfiguration. Significant improvements could be achieved via reconfiguration. Compared to the approaches reported in the literature, communication cost, throughput, latency and energy consumption values improve by 23.4%, 4%, 3% and 7%, respectively. These improvements come at a nominal increase in area overhead of 0.07%.

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Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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Schuck, Christian, Bastian Haetzer, and Jürgen Becker. "Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/671546.

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Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.

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VADHIYAR, SATHISH S., and JACK J. DONGARRA. "SRS: A FRAMEWORK FOR DEVELOPING MALLEABLE AND MIGRATABLE PARALLEL APPLICATIONS FOR DISTRIBUTED SYSTEMS." Parallel Processing Letters 13, no. 02 (June 2003): 291–312. http://dx.doi.org/10.1142/s0129626403001288.

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The ability to produce malleable parallel applications that can be stopped and reconfigured during the execution can offer attractive benefits for both the system and the applications. The reconfiguration can be in terms of varying the parallelism for the applications, changing the data distributions during the executions or dynamically changing the software components involved in the application execution. In distributed and Grid computing systems, migration and reconfiguration of such malleable applications across distributed heterogeneous sites which do not share common file systems provides flexibility for scheduling and resource management in such distributed environments. The present reconfiguration systems do not support migration of parallel applications to distributed locations. In this paper, we discuss a framework for developing malleable and migratable MPI message-passing parallel applications for distributed systems. The framework includes a user-level checkpointing library called SRS and a runtime support system that manages the checkpointed data for distribution to distributed locations. Our experiments and results indicate that the parallel applications, with instrumentation to SRS library, were able to achieve reconfigurability incurring about 15-35% overhead.

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Rantala, Ville, Teijo Lehtonen, Pasi Liljeberg, and Juha Plosila. "Analysis of Monitoring Structures for Network-on-Chip." International Journal of Embedded and Real-Time Communication Systems 2, no. 1 (January 2011): 49–67. http://dx.doi.org/10.4018/jertcs.2011010103.

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Monitoring services are essential for advanced, reliable NoC systems. They should support traffic management, system reconfiguration and fault detection to enable optimal performance and reliability of the system. The paper presents a thorough description of NoC monitoring structures and studies earlier works. A distributed monitoring structure is proposed and compared against the structures presented in previous works. The proposed distributed network monitoring system does not require centralized control, is fully scalable and does not cause significant traffic overhead to the network. The distributed structure is in line with the scalability and flexibility of the NoC paradigm. The paper studies the monitoring structure features and analyzes traffic overhead, monitoring data diffusion, cost and performance. The advantages of distributed monitoring are found evident and the limitations of the structure are discussed.

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Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. "Dynamic Reliability Management for FPGA-Based Systems." International Journal of Reconfigurable Computing 2020 (June 13, 2020): 1–19. http://dx.doi.org/10.1155/2020/2808710.

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Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.

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Haller, Stefan, Muhammad Farhan Alam, and Kent Bertilsson. "Reconfigurable Battery for Charging 48 V EVs in High-Voltage Infrastructure." Electronics 11, no. 3 (January 24, 2022): 353. http://dx.doi.org/10.3390/electronics11030353.

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48 V is emerging as a safe-to-touch alternative voltage level for electric vehicles (EVs). Using a low- instead of a high-voltage drive train reduces isolation efforts, eliminates the risk of electric shock, and thus increases the system safety. In contrast, fast charging of a 48 V battery would require very high currents and is incompatible with the widely established high-voltage electric vehicle charging infrastructure. Instead of employing additional on board power converters for fast charging, the concept of a reconfigurable battery is presented. A small-scale prototype system is designed consisting of eight 48 V lithium iron phosphate battery modules. In series configuration, they can be charged at 460 V with up to 25 A. In 48 V parallel configuration, the peak discharge current is up to 800 A. The MOSFET-based reconfiguration system also operates as a module charge balancer during high-voltage charging. The cost overhead for the reconfiguration system is estimated to 3% for a scaled-up full size EV. Due to the additional reconfiguration switch resistances, the simulation of a 48 V 75 kW electric vehicle in the World harmonized Light-duty vehicles Test Procedure showed a performance reduction of 0.24%.

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Farshadjam, Farshid, Mehdi Dehghan, Mahmood Fathy, and Majid Ahmadi. "A new compression based approach for reconfiguration overhead reduction in virtex based RTR systems." Computers & Electrical Engineering 32, no. 4 (July 2006): 322–47. http://dx.doi.org/10.1016/j.compeleceng.2005.09.007.

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Fu, Shu, Bin Wu, Xiaohong Jiang, Achille Pattavina, Hong Wen, and Hongfang Yu. "Switch cost and packet delay tradeoff in data center networks with switch reconfiguration overhead." Computer Networks 87 (July 2015): 33–43. http://dx.doi.org/10.1016/j.comnet.2015.05.010.

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Agrawal, Praveen, Neeraj Kanwar, Nikhil Gupta, Khaleequr Rehman Niazi, Anil Swarnkar, Nand K. Meena, and Jin Yang. "Reliability and Network Performance Enhancement by Reconfiguring Underground Distribution Systems." Energies 13, no. 18 (September 10, 2020): 4719. http://dx.doi.org/10.3390/en13184719.

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Contemporary distributions are now going to underground their overhead distribution lines due to techno-social reasons. Reliability and loss reduction are the two prime objectives for distribution system operation. Since failure rates of ungrounded cables are the function of Joules heating besides their physical lengths, the reliability evaluation of undergrounded distribution systems needs to be reviewed. This paper suggested a suitable modification in existing reliability indices in order to make them more appropriate for underground distribution systems. A multi-objective network reconfiguration problem is formulated to enhance the reliability and performance of distribution systems while duly addressing the variability and uncertainty in load demand and power generation from renewables. The application results on a standard test bench shift the paradigm of the well-known conflicting nature of reliability and network performance indices defined for overhead distribution systems.

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Saeed, Ahmed, Ali Ahmadinia, and Mike Just. "Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650089. http://dx.doi.org/10.1142/s0218126616500894.

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Security is becoming the primary concern in today’s embedded systems. Network-on-chip (NoC)-based communication architectures have emerged as an alternative to shared bus mechanism in multi-core system-on-chip (SoC) devices and the increasing number and functionality of processing cores have made such systems vulnerable to security attacks. In this paper, a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in an NoC-based multi-core shared memory architecture. Our IAV module is implemented on an FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyze the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.

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Deng, Li, Yang Li, Li Yao, Yu Jin, and Jinguang Gu. "Power-Aware Resource Reconfiguration Using Genetic Algorithm in Cloud Computing." Mobile Information Systems 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/4859862.

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Cloud computing enables scalable computation based on virtualization technology. However, current resource reallocation solution seldom considers the stability of virtual machine (VM) placement pattern. Varied workloads of applications would lead to frequent resource reconfiguration requirements due to repeated appearance of hot nodes. In this paper, several algorithms for VM placement (multiobjective genetic algorithm (MOGA), power-aware multiobjective genetic algorithm (pMOGA), and enhanced power-aware multiobjective genetic algorithm (EpMOGA)) are presented to improve stability of VM placement pattern with less migration overhead. The energy consumption is also considered. A type-matching controller is designed to improve evolution process. Nondominated sorting genetic algorithm II (NSGAII) is used to select new generations during evolution process. Our simulation results demonstrate that these algorithms all provide resource reallocation solutions with long stabilization time of nodes. pMOGA and EpMOGA also better balance the relationship of stabilization and energy efficiency by adding number of active nodes as one of optimal objectives. Type-matching controller makes EpMOGA superior to pMOGA.

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Mon Myint, Su, and Soe Win Naing. "Network Reconfiguration for Loss Reduction and Voltage Profile Improvement of 110-Bus Radial Distribution System Using Exhaustive Search Techniques." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 4 (August 1, 2015): 788. http://dx.doi.org/10.11591/ijece.v5i4.pp788-797.

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Nowadays, the electricity demand is increasing day by day and hence it is very important not only to extract electrical energy from all possible new power resources but also to reduce power losses to an acceptable minimum level in the existing distribution networks where a large amount of power dissipation occurred. In Myanmar, a lot of power is remarkably dissipated in distribution system. Among methods in reducing power losses, network reconfiguration method is employed for loss minimization and exhaustive technique is also applied to achieve the minimal loss switching scheme. Network reconfiguration in distribution systems is performed by opening sectionalizing switches and closing tie switches of the network for loss reduction and voltage profile improvement. The distribution network for existing and reconfiguration conditions are modelled and simulated by Electrical Transient Analyzer Program (ETAP) 7.5 version software. The inputs are given based on the real time data collected from 33/11kV substations under Yangon Electricity Supply Board (YESB). The proposed method is tested on 110-Bus, overhead AC radial distribution network of Dagon Seikkan Township since it is long-length, overloaded lines and high level of power dissipation is occurred in this system. According to simulation results of load flow analysis, voltage profile enhancement and power loss reduction for proposed system are revealed in this paper.

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Kamran, Arezoo, and Zainalabedin Navabi. "Self-Healing Many-Core Architecture: Analysis and Evaluation." VLSI Design 2016 (July 25, 2016): 1–17. http://dx.doi.org/10.1155/2016/9767139.

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More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-core architecture possible. Several test components are incorporated in the many-core architecture that distribute test stimuli, suspend normal operation of individual processing cores, apply test, and detect faulty cores. Test is performed concurrently with the system normal operation without any noticeable downtime at the application level. Experimental results show that the proposed test architecture is extensively scalable in terms of hardware overhead and performance overhead that makes it applicable to many-cores with more than a thousand processing cores.

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Resano, Javier, Diederik Verkest, Daniel Mozos, Serge Vernalde, and Francky Catthoor. "A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs." Microprocessors and Microsystems 28, no. 5-6 (August 2004): 291–301. http://dx.doi.org/10.1016/j.micpro.2004.03.015.

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Yoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India." Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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Meloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

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Prasad Acharya, G., and M. Asha Rani. "Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 3 (May 28, 2018): 160. http://dx.doi.org/10.11591/ijres.v6.i3.pp160-168.

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<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>

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KIA, REZA, NIKBAKHSH JAVADIAN, MOHAMMAD MAHDI PAYDAR, and MOHAMMAD SAIDI-MEHRABAD. "A SIMULATED ANNEALING FOR INTRA-CELL LAYOUT DESIGN OF DYNAMIC CELLULAR MANUFACTURING SYSTEMS WITH ROUTE SELECTION, PURCHASING MACHINES AND CELL RECONFIGURATION." Asia-Pacific Journal of Operational Research 30, no. 04 (August 2013): 1350004. http://dx.doi.org/10.1142/s0217595913500048.

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This paper develops a novel mixed integer nonlinear programming model for the intra-cell layout design of dynamic cellular manufacturing systems. In dynamic environment, the product mix and part demand are varying during a multi-period planning horizon. As a result, the cell configuration for one period may not be efficient for successive periods and thus necessitates reconfigurations. The proposed model incorporates several design features including intra-cell layout, operation sequence, operation time, alternative process routings, duplicate machines, purchase machine, machine capacity, route selection, production volume of parts, part movements in batch and cell reconfiguration. By considering intra-cell layout and operation sequence, the material handling volume and related cost is calculated more exactly. The objective is to minimize the total costs of inter-cell material handling, forward and backward intra-cell material handling, setting up route, machine relocation, purchasing new machines, machine overhead and machine processing. The main constraints are route selection among flexible routings, machine availability, cell size, machine time-capacity and machine location. The proposed model cannot be solved for large-sized problems optimally within a reasonable amount of computational time. Therefore, an efficient simulated annealing algorithm is developed to overcome NP-hardness of the proposed model.

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Lopes Ferreira, Mário, and João Canas Ferreira. "An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios." Electronics 8, no. 1 (December 20, 2018): 2. http://dx.doi.org/10.3390/electronics8010002.

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The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.

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Portilla, J., A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, and P. Langendörfer. "Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors." International Journal of Distributed Sensor Networks 6, no. 1 (January 1, 2010): 740823. http://dx.doi.org/10.1155/2010/740823.

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Specific features of Wireless Sensor Networks (WSNs) like the open accessibility to nodes, or the easy observability of radio communications, lead to severe security challenges. The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate. In order to avoid dependencies on a compromised level of security, a WSN node with a microcontroller and a Field Programmable Gate Array (FPGA) is used along this work to implement a state-of-the art solution based on ECC (Elliptic Curve Cryptography). In this paper it is described how the reconfiguration possibilities of the system can be used to adapt ECC parameters in order to increase or reduce the security level depending on the application scenario or the energy budget. Two setups have been created to compare the software- and hardware-supported approaches. According to the results, the FPGA-based ECC implementation requires three orders of magnitude less energy, compared with a low power microcontroller implementation, even considering the power consumption overhead introduced by the hardware reconfiguration.

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Zhang, Xueji, Goele Pipeleers, Kristian Hengster-Movrić, and Cassio Faria. "Vibration reduction for structures: distributed schemes over directed graphs." Journal of Vibration and Control 25, no. 14 (May 13, 2019): 2025–42. http://dx.doi.org/10.1177/1077546319844856.

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This paper aims to bridge the gap between control engineering and vibration engineering. We developed three distributed schemes over directed communication graph topology, specifically for vibration reduction of flexible structures. Under the distributed schemes, vibrations are attenuated through agents consisting of distributed observers and controllers. Compared to traditional methods, the developed approaches can reduce the communication overhead and the computational complexity when a large number of actuators and sensors are deployed. Moreover, two of the developed schemes enjoy the flexibility in reconfiguration of communication graph topology and integration of redundant agents. Furthermore, numerical simulations are presented to demonstrate the effectiveness of the developed schemes in vibration reduction of flexible structures.

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GUPTA, VIPUL, and EUGEN SCHENFELD. "TASK GRAPH PARTITIONING AND MAPPING IN A RECONFIGURABLE PARALLEL ARCHITECTURE." Parallel Processing Letters 05, no. 04 (December 1995): 563–74. http://dx.doi.org/10.1142/s0129626495000503.

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The goal of a task graph partitioning and mapping strategy is to reduce the communication overhead in a parallel application. Much of the past work in this area has been in the context of a static network topology. Here we show that the flexibility provided by a reconfigurable network can help lower the overhead and provide additional performance gains. However, since a reconfigurable network can be set to many different topologies, a new approach for the mapping problem must be formulated. Our research is based on the Interconnection Cached Network (ICN) a prototype of which is currently under development. The ICN is a reconfigurable network suited for exploiting switching locality in applications. "Switching locality" refers to the phenomenon in parallel applications of having each task mostly communicating (switching) between a small set of other tasks. As evidenced by the sparse nature of most task graphs, this phenomenon is common to many parallel applications. We describe the ICN architecture, the problem of mapping task graphs in the ICN, and the performance advantages of complementing clever partitioning strategies with topology reconfiguration.

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Do Nascimento, Paulo Sérgio Brandão, Stelita M. Da Silva, Jordana L. Seixas, Remy E. Sant’Anna, and Manoel E. De Lima. "Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration." Journal of Integrated Circuits and Systems 2, no. 1 (September 9, 2007): 45–54. http://dx.doi.org/10.29292/jics.v2i1.235.

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High parallelism degree is fundamental for high speed massive data processing systems. Modern FPGA devices can provide such parallelism plus flexibility. However, these devices are still limited by their logic block size, memory size, memory bandwidth and configuration time. Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. This approach can increase the effective area for system implementation, allowing increase of parallelism in each task that composes the application. However, the necessary reconfiguration time between contexts can cause performance decrease. A possible solution for this is an intensive parallelism exploration of massive data application to compensate for this overhead and improve global performance. This is true for modern FPGA with relatively high reconfiguration speed. In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the application task scheduling. A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. Experiments demonstrate the efficiency of this approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration. A design flow is shown based on library components that implements typical tasks used in the domain of applications.

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Aziz, Israa, Hai Jin, Ihsan Abdulqadder, Zaid Hussien, Zaid Abduljabbar, and Firas Flaih. "A Lightweight Scheme to Authenticate and Secure the Communication in Smart Grids." Applied Sciences 8, no. 9 (September 1, 2018): 1508. http://dx.doi.org/10.3390/app8091508.

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Self-reconfiguration in electrical power grids is a significant tool for their planning and operation during both normal and abnormal conditions. The increasing in employment of Intelligent Electronic Devices (IEDs), as well as the rapid growth of the new communication technologies have increased the application of Feeder Automation (FA) in Distribution Networks (DNs). In a Smart Grid (SG), automation equipment, such as a Smart Breaker (SB), is used. Using either a wired or a wireless network or even a combination of both, communication between the Control Center (CC) and SBs can be made. Nowadays, wireless technology is widely used in the communication of DNs. This may cause several security vulnerabilities in the power system, such as remote attacks, with the goal of cutting off the electrical power provided to significant consumers. Therefore, to preserve the cybersecurity of the system, there is a need for a secure scheme. The available literature investments proposed a heavyweight level in security schemes, while the overhead was not considered. To overcome this drawback, this paper presents an efficient lightweight authentication mechanism with the necessary steps to ensure real-time automatic reconfiguration during a fault. As a first stage, authentication will be made between CC and SB, SB then sends the information about its status. To ensure the integrity of the authentication exchange, a hash function is used, while the symmetric algorithm is used to ensure privacy. The applicability of the suggested scheme has been proved by conducting security performance and analysis. The proposed scheme will be injected on ABB medium voltage breaker with the REF 542plus controller. Therefore, the probable benefit of the suggested scheme is the contribution to provide more flexibility for electrical utilities in terms of reducing the overall computational overhead and withstanding to various types of attacks, while also opening new prospects in FA of SGs.

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Zhang, Dan, Rong Cai Zhao, Lin Han, and Jin Qu. "A Parallelization Cost Model for FPGA." Advanced Materials Research 181-182 (January 2011): 623–28. http://dx.doi.org/10.4028/www.scientific.net/amr.181-182.623.

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Using FPGA for general-purpose computing has become an important research direction in high performance computing technology. However, it is not a lossless optimization method. Due to the impact of hardware reconfiguration overhead, data transmission cost, specific characteristics of programs, and other factors, the speedup of general-purpose computing on FPGA has visible difference. On the basis of in-depth analysis of FPGA architecture and development process, the main factors affecting FPGA implementation performance are pointed out, and a parallel cost model for FPGA based on static program analysis is proposed to provide judgment basis for using FPGA in general-purpose computing. The experiment results show that the algorithm estimates accurately FPGA execution performance.

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Mahesh, R., and A. P. Vinod. "An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers." Journal of Signal Processing Systems 64, no. 3 (June 22, 2010): 413–28. http://dx.doi.org/10.1007/s11265-010-0502-9.

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Zeng, Shulin, Guohao Dai, Hanbo Sun, Jun Liu, Shiyao Li, Guangjun Ge, Kai Zhong, Kaiyuan Guo, Yu Wang, and Huazhong Yang. "A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (September 30, 2022): 1–31. http://dx.doi.org/10.1145/3480170.

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INFerence-as-a-Service (INFaaS) has become a primary workload in the cloud. However, existing FPGA-based Deep Neural Network (DNN) accelerators are mainly optimized for the fastest speed of a single task, while the multi-tenancy of INFaaS has not been explored yet. As the demand for INFaaS keeps growing, simply increasing the number of FPGA-based DNN accelerators is not cost-effective, while merely sharing these single-task optimized DNN accelerators in a time-division multiplexing way could lead to poor isolation and high-performance loss for INFaaS. On the other hand, current cloud-based DNN accelerators have excessive compilation overhead, especially when scaling out to multi-FPGA systems for multi-tenant sharing, leading to unacceptable compilation costs for both offline deployment and online reconfiguration. Therefore, it is far from providing efficient and flexible FPGA virtualization for public and private cloud scenarios. Aiming to solve these problems, we propose a unified virtualization framework for general-purpose deep neural networks in the cloud, enabling multi-tenant sharing for both the Convolution Neural Network (CNN), and the Recurrent Neural Network (RNN) accelerators on a single FPGA. The isolation is enabled by introducing a two-level instruction dispatch module and a multi-core based hardware resources pool. Such designs provide isolated and runtime-programmable hardware resources, which further leads to performance isolation for multi-tenant sharing. On the other hand, to overcome the heavy re-compilation overheads, a tiling-based instruction frame package design and a two-stage static-dynamic compilation, are proposed. Only the lightweight runtime information is re-compiled with ∼1 ms overhead, thus guaranteeing the private cloud’s performance. Finally, the extensive experimental results show that the proposed virtualized solutions achieve up to 3.12× and 6.18× higher throughput in the private cloud compared with the static CNN and RNN baseline designs, respectively.

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Saldaña, Manuel, Arun Patel, Hao Jun Liu, and Paul Chow. "Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms." International Journal of Reconfigurable Computing 2012 (2012): 1–10. http://dx.doi.org/10.1155/2012/127302.

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Partial reconfiguration (PR) is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to createtemplate bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

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Fujioka, Yoshichika, and Nobuhiro Tomabechi. "Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length." Journal of Robotics and Mechatronics 8, no. 6 (December 20, 1996): 524–30. http://dx.doi.org/10.20965/jrm.1996.p0524.

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In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multioperand multiply-additions. To reduce the delay time for the multiply-additions, switch circuit is used to change the direct connection between the multipliers and adders, so that the overhead in data transfer is reduced. To change the word-length of the multi-operand multiply-adders, in addition, the switches are also provided in multipliers and adders. By changing to the short wordlength, the numbers of multiplier and adders can be increased. The performance evaluation shows that the delay time for visual feedback control becomes about 6 times faster than that of a parallel processor approach using conventional digital signal processor (DSPs).

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Moon, Hyeongyun, and Daejin Park. "An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications." Electronics 10, no. 17 (August 28, 2021): 2088. http://dx.doi.org/10.3390/electronics10172088.

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The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server computing capacity, and the security issues that occur in the data communication process. However, edge-based IoT systems performance was insufficient to process large numbers of data due to limited power supply, fixed hardware functions, and limited hardware resources. To improve their performance, application-specific hardware can be installed in edge devices, but performance cannot be improved except for specific applications due to a fixed function of an application-specific hardware. This paper introduces an edge-centric metamorphic IoT (mIoT) platform that can use various hardware modules through on-demand partial reconfiguration, despite the limited hardware resources of edge devices. In addition, this paper introduces an RISC-V based metamorphic IoT processor (mIoTP) with reconfigurable peripheral modules. We experimented to prove that the proposed structure can reduce the server access of edges and can be applied to a large-scale IoT system. Experiments were conducted in a single-edge environment and a large-scale environment combining one physical edge and 99 virtual edges. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration prediction algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to our previous study in which the prediction process was executed at the server. Furthermore, we confirmed that there is no additional reconfiguration time overhead even for the large IoT systems.

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Jozwik, Krzysztof, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada. "Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs." International Journal of Reconfigurable Computing 2013 (2013): 1–40. http://dx.doi.org/10.1155/2013/789134.

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Dynamic Partial Reconfiguration technology coupled with an Operating System for Reconfigurable Systems (OS4RS) allows for implementation of a hardware task concept, that is, an active computing object which can contend for reconfigurable computing resources and request OS services in a way software task does in a conventional OS. In this work, we show a complete model and implementation of a lightweight OS4RS supporting preemptable and clock-scalable hardware tasks. We also propose a novel, lightweight scheduling mechanism allowing for timely and priority-based reservation of reconfigurable resources, which aims at usage of preemption only at the time it brings benefits to the performance of a system. The architecture of the scheduler and the way it schedules allocations of the hardware tasks result in shorter latency of system calls, thereby reducing the overall OS overhead. Finally, we present a novel model and implementation of a channel-based intertask communication and synchronization suitable for software-hardware multitasking with preemptable and clock-scalable hardware tasks. It allows for optimizations of the communication on per task basis and utilizes point-to-point message passing rather than shared-memory communication, whenever it is possible. Extensive overhead tests of the OS4RS services as well as application speedup tests show efficiency of our approach.

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KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm profiles memory access pattern of the application, produces the access conflict graph, relocates decomposed memory sub-pages based on the access conflict graph, and finally generates a synthesizable code of the address shuffler. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler removes 80% of access conflicts on average for benchmarks where the hardware overhead of the shuffler is 1592 LUTs which is 14% of LUT size of the processor core.

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Journal articles on the topic 'Reconfiguration overhead'

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