Relevant bibliographies by topics / Reconfiguration overhead

Academic literature on the topic 'Reconfiguration overhead'

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Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "Reconfiguration overhead"

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Hoffman, John C., and Marios S. Pattichis. "A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback." International Journal of Reconfigurable Computing 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/439072.

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Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead. To minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the reconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively limits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the system can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of overclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and temperature are within nominal operating conditions. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5, consists of four different hardware platforms.
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JUNG, S., and T. G. KIM. "Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration." IEICE Transactions on Information and Systems E91-D, no. 11 (November 1, 2008): 2675–84. http://dx.doi.org/10.1093/ietisy/e91-d.11.2675.

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Sungjoon Jung and Tag Gon Kim. "An Operation and Interconnection Sharing Algorithm for Reconfiguration Overhead Reduction Using Static Partial Reconfiguration." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 12 (December 2008): 1589–95. http://dx.doi.org/10.1109/tvlsi.2008.2000973.

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CHOU, Kuan-Hung, and Woei LIN. "Performance Analysis of Optical Packet Switches with Reconfiguration Overhead." IEICE Transactions on Communications E94-B, no. 6 (2011): 1640–47. http://dx.doi.org/10.1587/transcom.e94.b.1640.

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KIM, J., J. CHO, and T. G. KIM. "Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures." IEICE Transactions on Information and Systems E90-D, no. 12 (December 1, 2007): 1977–85. http://dx.doi.org/10.1093/ietisy/e90-d.12.1977.

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BELAID, IKBEL, BASSEM OUNI, FABRICE MULLER, and MAHER BENJEMAA. "COMPLETE AND APPROXIMATE METHODS FOR OFF-LINE PLACEMENT OF HARDWARE TASKS ON RECONFIGURABLE DEVICES." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250080. http://dx.doi.org/10.1142/s0218126612500806.

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With the advent of run-time partial reconfiguration, the most recent reconfigurable devices support reconfiguring hardware tasks individually, without interrupting the remaining tasks running on the same device. While the concept of run-time partial reconfiguration increases performance and resource utilization, it also leads to resource wastage, high configuration overhead and complex allocation situations of hardware tasks on reconfigurable devices. Many on-line and off-line methods for hardware task placement have been proposed for such reconfigurable devices to enhance placement quality expressed by fragmentation rate, the amount of task rejection and a few of them also estimate configuration overhead. However, these works treat each criterion individually and therefore do not reflect the overall metrics of placement quality. Hardware task placement is a multi-objective combinatory optimization problem. In this paper, we investigate the problem of off-line placement of hardware tasks in partially reconfigurable devices and we present a new three-level resource management that is based on two methods, i.e., a complete analytic method: the formulation into mixed integer programming, and an approximate iterative method: the Bees algorithm. For both methods, the placement quality is measured by the rate of resource efficiency and by the amount of configuration overhead. Experiments demonstrate that the analytic method provides better resource efficiency than the Bees Algorithm by 33% and attains 15% of gain in configuration overhead.
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Koch, Dirk, Christian Beckhoff, and Jim Torresen. "Efficient Interfacing of Partially Reconfigurable Instruction Set Extensions for Softcore CPUs on FPGAs." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 35–42. http://dx.doi.org/10.29292/jics.v6i1.336.

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Swapping just small fractions of the configuration of an FPGA can be very beneficial in many applications. This is in particular useful for reconfiguring the instruction set of embedded soft core processors. In this paper, we will sketch that present design techniques include a substantial overhead for integrating reconfigurable parts into the rest of the system. This overhead can cost more logic resources than the actual module implementations. For removing this overhead, we propose a novel technique to constrain the communication resources between the static system and the partial regions.We will demonstrate for a reconfigurable soft core processor that instructions can be integrated into the system without causing any additional logic overhead for the communication. In addition, we reveal how such systems can be easily implemented with our tool ReCoBus-Builder. Furthermore, we will analyze the overhead in terms of reconfiguration time and present a metric helping to take design decisions.
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KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.
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Feng, Xiao Jing, Xi Li, Wang Chao, Xue Hai Zhou, and Jun Neng Zhang. "A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration." Advanced Materials Research 433-440 (January 2012): 5172–77. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5172.

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The strict requirements on both performance and flexibility lead us to apply Dynamic Partial Reconfiguration (DPR) technology in embedded systems. However, existing DPR design flows are still immature, since previous works mainly focus on hardware designs while ignore software designs for DPR. To remedy this weakness, this paper proposes a hardware/software (HW/SW) co-design flow for DPR. The co-design flow aims at accelerating the process of DPR designs, and it merges software and hardware design flows to make them operate in parallel. Besides, in order to validate the effectiveness of our co-design flow, we implement a partial self-reconfigurable prototype system on Xilinx Virtex-5 platform and perform a set of experiments. Experimental results present that the reconfiguration overhead for partial reconfiguration is only 4.66% against global reconfiguration in our prototype. It’s also presented that our prototype can achieve a 23.6 × speedup over software algorithm solutions.
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Lallet, Julien, Sébastien Pillement, and Olivier Sentieys. "Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures." Journal of Integrated Circuits and Systems 4, no. 1 (November 21, 2009): 36–44. http://dx.doi.org/10.29292/jics.v4i1.295.

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Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.
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Dissertations / Theses on the topic "Reconfiguration overhead"

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Клименко, Ірина Анатоліївна. "Методи та засоби підвищення ефективності обробки інформації в реконфігуровних комп’ютерних системах на базі ПЛІС." Doctoral thesis, Київ, 2017. https://ela.kpi.ua/handle/123456789/19095.

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У дисертації наведено теоретичне узагальнення і нове вирішення наукової проблеми, що полягає в розвитку теорії організації обробки інформації в комп’ютерних системах на ПЛІС з урахуванням їх функціональних та апаратурних обмежень. Запропоновані методи та засоби включають в себе взаємозв’язані вирішення завдань оптимізації процесу обробки інформації шляхом визначення оптимальної зернистості обчислень, а також зменшення накладних витрат процесу відображення задач на реконфігуровне обчислювальне середовище, що в цілому забезпечує підвищення ефективності обробки інформації в реконфігуровних обчислювальних системах на ПЛІС. Запропоновано нову стратегію взаємної адаптації розв’язуваних задач і обчислювального середовища на ПЛІС, що ґрунтується на варіюванні зернистістю обчислень під час розв’язання задач великої розмірності, та вдосконалено концепцію реалізації локальних розподілених засобів керування відображенням задач на реконфігуровне обчислювальне середовище, що підвищує ефективність врахування фізичних параметрів кристалів ПЛІС на всіх рівнях реалізації реконфігуровних комп’ютерних систем.
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Tseng, Chi-Hua, and 曾啟華. "Reconfiguration Overhead Reduction and Hiding of Run-Time Reconfigurable System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/72639710189266801319.

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碩士
國立交通大學
資訊工程系
92
In run-time reconfigurable system, the whole partial reconfigurable hardware is viewed as a reconfiguration and execution unit traditionally. Therefore, execution cannot start until the finish reconfiguration of the whole partial reconfigurable hardware. We virtually divide the partial reconfigurable hardware into several equal-size blocks. The reconfiguration and execution unit is smaller. This can make reconfiguration of one block overlap with execution of other blocks. And this can hide some reconfiguration overhead. Doing so will bring a new problem which is partitions-to-blocks scheduling. We design a two phases scheduler. Phase I will generate one highest priority partition from un-scheduled partitions. There are three considerations of the partition’s priority. One is the partition is on current critical path or not. Another is the number of outgoing edges and released partitions of the partition. The other is the execution time of the partition. We have two partition selection policies including of critical first and utilization first. Phase II will assign one block to the highest priority partition generated from Phase I. If the partition is the latest partition, we will assign one block to the partition so that the partition can finish execution earliest. If the partition is not the latest partition, we will look ahead one next future partition into consideration together. Choose one block to the primary partition so that these two partitions can release maximal resource with time. The result shows that utilization first is better than critical first. And view a part of the whole partial reconfigurable hardware as a reconfiguration and execution unit can improve completion time of run-time reconfigurable system.
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Jen, Hsung, and 任軒. "Reconfiguration Overhead Reduction Using Prefetch and Merge Techniques in Run-Time Reconfigurable System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/21085391635759437079.

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Book chapters on the topic "Reconfiguration overhead"

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Duhem, François, Fabrice Muller, and Philippe Lorenzini. "FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA." In Lecture Notes in Computer Science, 253–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19475-7_26.

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Farzaneh, Masoud, and William A. Chisholm. "Power System Reconfiguration Options for Anti- and De-Icing." In Techniques for Protecting Overhead Lines in Winter Conditions, 311–34. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-87455-1_7.

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Resano, Javier, Daniel Mozos, Diederik Verkest, Serge Vernalde, and Francky Catthoor. "Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems." In Field Programmable Logic and Application, 585–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_57.

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Patel, Ravi, Anil Gojiya, and Dipankar Deb. "Failure Reconfiguration of Pumps in Two Reservoirs Connected to Overhead Tank." In Advances in Intelligent Systems and Computing, 81–92. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1966-2_7.

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Li, Bingbing, and Young-Chon Kim. "Logical Topology Design with Low Power Consumption and Reconfiguration Overhead in IP-over-WDM Networks." In Lecture Notes in Electrical Engineering, 375–86. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07674-4_38.

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Malik, Usama. "Minimising Reconfiguration Overheads in Embedded Applications (Abstract)." In Field Programmable Logic and Application, 1189. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_175.

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Vanderbauwhede, Wim. "High-Level Programming of Dynamically Reconfigurable NoC-Based Heterogeneous Multicore SoCs." In Dynamic Reconfigurable Network-on-Chip Design, 186–219. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch008.

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With the increase in System-on-Chip (SoC) complexity and CMOS technology capabilities, the SoC design community has recently observed a convergence of a number of critical trends, all of them aimed at addressing the design gap: the advent of heterogeneous multicore SoCs and Networks-on-Chip and the recognition of the need for design reuse through Intellectual Property (IP) cores, for dynamic reconfigurability and for high abstraction-level design. In this chapter, we present a solution for High-level Programming of Dynamically Reconfigurable NoC-based Heterogeneous Multicore SoCs. Our solution, the Gannet framework, allows IP core-based Heterogeneous Multicore SoCs to be programmed using a high-level language whilst preserving the full potential for parallelism and dynamic reconfigurability inherent in such a system. The required hardware infrastructure is small and low-latency, thus adding full dynamic reconfiguration capabilities with a small overhead both in area and performance.
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Lin, Wei-Wen, Jih-Sheng Shen, and Pao-Ann Hsiung. "An Efficient Hardware/Software Communication Mechanism for Reconfigurable NoC." In Dynamic Reconfigurable Network-on-Chip Design, 84–109. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch004.

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With the progress of technology, more and more intellectual properties (IPs) can be integrated into one single chip. The performance bottleneck has shifted from the computation in individual IPs to the communication among IPs. A Network-on-Chip (NoC) was proposed to provide high scalability and parallel communication. An ASIC-implemented NoC lacks flexibility and has a high non-recurring engineering (NRE) cost. As an alternative, we can implement an NoC in a Field Programmable Gate Arrays (FPGA). In addition, FPGA devices can support dynamic partial reconfiguration such that the hardware circuits can be configured into an FPGA at run time when necessary, without interfering hardware circuits that are already running. Such an FPGA-based NoC, namely reconfigurable NoC (RNoC), is more flexible and the NRE cost of FPGA-based NoC is also much lower than that of an ASIC-based NoC. Because of dynamic partial reconfiguration, there are several issues in the RNoC design. We focus on how communication between hardware and software can be made efficient for RNoC. We implement three communication architectures for RNoC namely single output FIFO-based architecture, multiple output FIFO-based architecture, and shared memory-based architecture. The average communication memory overhead is less on the single output FIFO-based architecture and the shared memory-based architecture than on the multiple output FIFO-based architecture when the lifetime interval is smaller than 0.5. In the performance analysis, some real applications are applied. Real application examples show that performance of the multiple output FIFO-based architecture is more efficient by as much as 1.789 times than the performance of the single output FIFO-based architecture. The performance of the shared memory-based architecture is more efficient by as much as 1.748 times than the performance of the single output FIFO-based architecture.
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Conference papers on the topic "Reconfiguration overhead"

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Yang Qu, J. P. Soininen, and J. Nurmi. "Using multiple configuration controllers to reduce the reconfiguration overhead." In 2005 NORCHIP. IEEE, 2005. http://dx.doi.org/10.1109/norchp.2005.1596995.

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Cugola, Gianpaolo, Davide Frey, Amy L. Murphy, and Gian Pietro Picco. "Minimizing the reconfiguration overhead in content-based publish-subscribe." In the 2004 ACM symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/967900.968130.

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Aslanidis, Timotheos, and Marios-Evangelos Kogias. "Algorithms for Packet Routing in Switching Networks with Reconfiguration Overhead." In Second International Conference on Computational Science and Engineering. Academy & Industry Research Collaboration Center (AIRCC), 2014. http://dx.doi.org/10.5121/csit.2014.4416.

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Wolinski, Christophe, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig. "Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.1.

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Ferrandi, Fabrizio, Marco Novati, Massimo Morandi, Marco Santambrogio, and Donatella Sciuto. "Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead." In 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.322008.

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Wolinski, Christophe, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig. "Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures." In 2008 16th International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2008. http://dx.doi.org/10.1109/fccm.2008.16.

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Wu, Binbin, Like Yan, Yuan Wen, and Tianzhou Chen. "Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration." In 2010 IEEE International SOC Conference (SOCC). IEEE, 2010. http://dx.doi.org/10.1109/socc.2010.5784651.

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Yang Qu, J. P. Soininen, and J. Nurmi. "A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead." In 2006 Design, Automation and Test in Europe. IEEE, 2006. http://dx.doi.org/10.1109/date.2006.243864.

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Nafkha, Amor, and Yves Louet. "Accurate measurement of power consumption overhead during FPGA dynamic partial reconfiguration." In 2016 International Symposium on Wireless Communication Systems (ISWCS). IEEE, 2016. http://dx.doi.org/10.1109/iswcs.2016.7600972.

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Tan, Heng, and Ronald DeMara. "A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead." In 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006). IEEE, 2006. http://dx.doi.org/10.1109/reconf.2006.307757.

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