Journal articles: 'Reconfigurable Hardware Architecture'

1

Thomas, Alexander, Michael Rückauer, and Jürgen Becker. "HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture." International Journal of Reconfigurable Computing 2012 (2012): 1–17. http://dx.doi.org/10.1155/2012/832531.

Full text

Abstract:

Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.

APA, Harvard, Vancouver, ISO, and other styles

2

Siddiqui, Ali Shuja, Yutian Gui, and Fareena Saqib. "Secure Boot for Reconfigurable Architectures." Cryptography 4, no. 4 (September 25, 2020): 26. http://dx.doi.org/10.3390/cryptography4040026.

Full text

Abstract:

Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements a secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.

APA, Harvard, Vancouver, ISO, and other styles

3

Fabiani, Erwan. "Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/923415.

Full text

Abstract:

This paper presents the “reconfigurable computing” teaching part of a computer science master course (first year) on parallel architectures. The practical work sessions of this course rely on active pedagogy using problem-based learning, focused on designing a reconfigurable architecture for the implementation of an application class of image processing algorithms. We show how the successive steps of this project permit the student to experiment with several fundamental concepts of reconfigurable computing at different levels. Specific experiments include exploitation of architectural parallelism, dataflow and communicating component-based design, and configurability-specificity tradeoffs.

APA, Harvard, Vancouver, ISO, and other styles

4

Pionteck, Thilo, Roman Koch, Carsten Albrecht, and Erik Maehle. "A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime." International Journal of Reconfigurable Computing 2009 (2009): 1–10. http://dx.doi.org/10.1155/2009/942930.

Full text

Abstract:

Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.

APA, Harvard, Vancouver, ISO, and other styles

5

Göhringer, Diana, Thomas Perschke, Michael Hübner, and Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.

Full text

Abstract:

Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.

APA, Harvard, Vancouver, ISO, and other styles

6

Wijtvliet, Mark, Henk Corporaal, and Akash Kumar. "CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures." ACM Transactions on Reconfigurable Technology and Systems 14, no. 4 (December 31, 2021): 1–28. http://dx.doi.org/10.1145/3468874.

Full text

Abstract:

Reconfigurable architectures are quickly gaining in popularity due to their flexibility and ability to provide high energy efficiency. However, reconfigurable systems allow for a huge design space. Iterative design space exploration (DSE) is often required to achieve good Pareto points with respect to some combination of performance, area, and/or energy. DSE tools depend on information about hardware characteristics in these aspects. These characteristics can be obtained from hardware synthesis and net-list simulation, but this is very time-consuming. Therefore, architecture models are common. This work introduces CGRA-EAM (Coarse-Grained Reconfigurable Architecture - Energy & Area Model), a model for energy and area estimation framework for coarse-grained reconfigurable architectures. The model is evaluated for the Blocks CGRA. The results demonstrate that the mean absolute percentage error is 15.5% and 2.1% for energy and area, respectively, while the model achieves a speedup of close to three orders of magnitude compared to synthesis.

APA, Harvard, Vancouver, ISO, and other styles

7

Voss, Nils, Bastiaan Kwaadgras, Oskar Mencer, Wayne Luk, and Georgi Gaydadjiev. "On Predictable Reconfigurable System Design." ACM Transactions on Architecture and Code Optimization 18, no. 2 (March 2021): 1–28. http://dx.doi.org/10.1145/3436995.

Full text

Abstract:

We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.

APA, Harvard, Vancouver, ISO, and other styles

8

Craven, Stephen, and Peter Athanas. "Dynamic Hardware Development." International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/901328.

Full text

Abstract:

Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them. While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design requires developers to work at a low level and contend with many poorly documented architecture-specific aspects. This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high-level synthesis tool to enable the design, simulation, and implementation of dynamically reconfigurable hardware solely from a specification written in C. Unlike previous attempts, this approach encompasses the entirety of design and implementation, enables self-re-configuration through an embedded controller, and inherently handles partial reconfiguration. Benchmarking numbers are provided, which validate the productivity enhancements this approach provides.

APA, Harvard, Vancouver, ISO, and other styles

9

NAKANO, KOJI. "A BIBLIOGRAPHY OF PUBLISHED PAPERS ON DYNAMICALLY RECONFIGURABLE ARCHITECTURES." Parallel Processing Letters 05, no. 01 (March 1995): 111–24. http://dx.doi.org/10.1142/s0129626495000102.

Full text

Abstract:

A dynamically reconfigurable architecture is a parallel computer architecture that supports a physical switching of communication patterns during a computation. Basically, the dynamically reconfigurable architecture consists of locally controllable switches, which enables flexible-connection patterns of the network. The bibliography attempts to classify published papers on dynamically reconfigurable architectures according to the problems that are dealt with.

APA, Harvard, Vancouver, ISO, and other styles

10

Purohit, Gaurav, Kota Solomon Raju, and Vinod Kumar Chaubey. "XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware." International Journal of Reconfigurable Computing 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/9128683.

Full text

Abstract:

This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

APA, Harvard, Vancouver, ISO, and other styles

11

DUAN, Tong, Julong LAN, Yuxiang HU, and Shiran LIU. "A Reconfigurable Hardware Architecture for Packet Processing." Chinese Journal of Electronics 27, no. 2 (March 1, 2018): 428–32. http://dx.doi.org/10.1049/cje.2017.08.018.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Irmak, Hasan, Federico Corradi, Paul Detterer, Nikolaos Alachiotis, and Daniel Ziener. "A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs." Journal of Low Power Electronics and Applications 11, no. 3 (August 17, 2021): 32. http://dx.doi.org/10.3390/jlpea11030032.

Full text

Abstract:

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

APA, Harvard, Vancouver, ISO, and other styles

13

MAJZOUB, S., and H. DIAB. "INSTRUCTION-SET EXTENSION FOR CRYPTOGRAPHIC APPLICATIONS ON RECONFIGURABLE PLATFORM." Journal of Circuits, Systems and Computers 16, no. 06 (December 2007): 911–27. http://dx.doi.org/10.1142/s0218126607004076.

Full text

Abstract:

Reconfigurable Systems represent a middle trade-off between speed and flexibility in the processor design world. It provides performance close to the custom-hardware and yet preserves some of the general-purpose processor flexibility. Recently, the area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse-grain hardware. Since the field is still in its developing stage, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndael and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. We present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology we used can be utilized in other systems.

APA, Harvard, Vancouver, ISO, and other styles

14

Das, Nitish, and Aruna Priya P. "FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach." International Journal of Reconfigurable Computing 2019 (April 1, 2019): 1–17. http://dx.doi.org/10.1155/2019/3727254.

Full text

Abstract:

Recently, the Reconfigurable FSM has drawn the attention of the researchers for multistage signal processing applications. The optimal synthesis of Reconfigurable finite state machine with input multiplexing (Reconfigurable FSMIM) architecture is done by the iterative greedy heuristic based Hungarian algorithm (IGHA). The major problem concerning IGHA is the disintegration of a state encoding technique. This paper proposes the integration of IGHA with the state assignment using logarithmic barrier function based gradient descent approach to reduce the hardware consumption of Reconfigurable FSMIM. Experiments have been performed using MCNC FSM benchmarks which illustrate a significant area and speed improvement over other architectures during field programmable gate array (FPGA) implementation.

APA, Harvard, Vancouver, ISO, and other styles

15

Le, Shu Ping, Zhi Wen Xiong, and Hong Zeng. "Design and Implement of the Reconfigurable Algorithm Based on uC/OS-II." Applied Mechanics and Materials 198-199 (September 2012): 1372–77. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1372.

Full text

Abstract:

More and more applications need The ability to customize the architecture to match the computation and the data flow of the application, so increasingly new system implementations based on reconfigurable computing are being considered. Reconfigurable computing has potential to accelerate a wide variety of applications; its main feature is the ability to perform computations in hardware to improve performance, while retaining the flexibility of software solutions. An operating system (OS) for reconfigurable computing uses new versions of algorithms for the scheduling, the operating system must decide how to allocate the hardware at run-time based on the status of the system. This paper discusses the scheduling algorithm for reconfigurable computing platform, covers two aspects of reconfigurable computing: architectures and design methods. The tasks are divided into two categories in this survey, consider the issues involved in reusing the configurable hardware during program execution. And improve μC/OS-II to manage the use of reconfigurable resources, responsible for task scheduling, helping the programmer to concentrate more on application development.

APA, Harvard, Vancouver, ISO, and other styles

16

Sandres, Paulo Renato de Souza Silva, Nadia Nedjah, and Luiza de Macedo Mourelle. "Reconfigurable hardware for fuzzy controller." International Journal of High Performance Systems Architecture 4, no. 3 (2013): 144. http://dx.doi.org/10.1504/ijhpsa.2013.055225.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Vranjković, Vuk S., Rastislav J. R. Struharik, and Ladislav A. Novak. "Reconfigurable Hardware for Machine Learning Applications." Journal of Circuits, Systems and Computers 24, no. 05 (April 8, 2015): 1550064. http://dx.doi.org/10.1142/s0218126615500644.

Full text

Abstract:

This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1–2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project.

APA, Harvard, Vancouver, ISO, and other styles

18

Perin, Guilherme, Daniel Gomes Mesquita, and João Baptista Martins. "Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation." International Journal of Reconfigurable Computing 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/127147.

Full text

Abstract:

This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. We compare thetime×areaefficiency for both architectures as well as an RSA application. The systolic implementation can run the 1024 bits RSA decryption process in just 3.23 ms, and the multiplexed architecture executes the same operation in 4.36 ms, but the second approach saves up to 28% of logical resources. These results are competitive with the state-of-the-art performance.

APA, Harvard, Vancouver, ISO, and other styles

19

Garzia, Fabio, Roberto Airoldi, and Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 24–43. http://dx.doi.org/10.4018/jertcs.2010070102.

Full text

Abstract:

This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.

APA, Harvard, Vancouver, ISO, and other styles

20

Belaid, Ikbel, Fabrice Muller, and Maher Benjemaa. "Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices." International Journal of Reconfigurable Computing 2011 (2011): 1–28. http://dx.doi.org/10.1155/2011/591983.

Full text

Abstract:

Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

APA, Harvard, Vancouver, ISO, and other styles

21

Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

Full text

Abstract:

Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

APA, Harvard, Vancouver, ISO, and other styles

22

Reza. "Reconfigurable Hardware Architecture for Network Intrusion Detection System." American Journal of Applied Sciences 9, no. 10 (October 1, 2012): 1618–24. http://dx.doi.org/10.3844/ajassp.2012.1618.1624.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Korat, Uday A., and Amirhossein Alimohammad. "A Reconfigurable Hardware Architecture for Principal Component Analysis." Circuits, Systems, and Signal Processing 38, no. 5 (October 11, 2018): 2097–113. http://dx.doi.org/10.1007/s00034-018-0953-y.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Hwang, Wen-Jyi, Wei-Hao Lee, Shiow-Jyu Lin, and Sheng-Ying Lai. "Efficient Architecture for Spike Sorting in Reconfigurable Hardware." Sensors 13, no. 11 (November 1, 2013): 14860–87. http://dx.doi.org/10.3390/s131114860.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Redif, Soydan, and Server Kasap. "Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 3 (March 2015): 454–65. http://dx.doi.org/10.1109/tvlsi.2014.2312997.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Kaufmann, Paul, Kyrre Glette, Marco Platzner, and Jim Torresen. "Compensating Resource Fluctuations by Means of Evolvable Hardware." International Journal of Adaptive, Resilient and Autonomic Systems 3, no. 4 (October 2012): 17–31. http://dx.doi.org/10.4018/jaras.2012100102.

Full text

Abstract:

The evolvable hardware (EHW) paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degradation of the computational resources. Extending the EHW principle to architectural adaptation, the authors study the capability of evolvable hardware classifiers to adapt to intentional run-time fluctuations in the available resources, i.e., chip area, in this work. To that end, the authors leverage the Functional Unit Row (FUR) architecture, a coarse-grained reconfigurable classifier, and apply it to two medical benchmarks, the Pima and Thyroid data sets from the UCI Machine Learning Repository. While quick recovery from architectural changes was already demonstrated for the FUR architecture, the authors also introduce two reconfiguration schemes helping to reduce the magnitude of degradation after architectural reconfiguration.

APA, Harvard, Vancouver, ISO, and other styles

27

Li, Peng, Hongyi Jin, Wei Xi, Changbao Xu, Hao Yao, and Kai Huang. "A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions." Electronics 12, no. 1 (January 3, 2023): 233. http://dx.doi.org/10.3390/electronics12010233.

Full text

Abstract:

Transcendental functions are an important part of algorithms in many fields. However, the hardware accelerators available today for transcendental functions typically only support one such function. Hardware accelerators that can support miscellaneous transcendent functions are a waste of hardware resources. In order to solve these problems, this paper proposes a reconfigurable hardware architecture for miscellaneous floating-point transcendental functions. The hardware architecture supports a variety of transcendental functions, including floating-point sine, cosine, arctangent, exponential and logarithmic functions. It adopts the method of a lookup table combined with a polynomial computation and reconfigurable technology to achieve the accuracy of two units of least precision (ulp) with 3.75 KB lookup tables and one core computing module. In addition, the hardware architecture uses retiming technology to realize the different operation times of each function. Experiments show that the hardware accelerators proposed can operate at a maximum frequency of 220 MHz. The full-load power consumption and areas are only 0.923 mW and 1.40×104μm2, which are reduced by 47.99% and 38.91%, respectively, compared with five separate superfunction hardware accelerators.

APA, Harvard, Vancouver, ISO, and other styles

28

Uchevler, Bahram N., and Kjetil Svarstad. "Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions." International Journal of Reconfigurable Computing 2018 (July 10, 2018): 1–25. http://dx.doi.org/10.1155/2018/3276159.

Full text

Abstract:

With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

APA, Harvard, Vancouver, ISO, and other styles

29

Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. "Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification." International Journal of Reconfigurable Computing 2010 (2010): 1–11. http://dx.doi.org/10.1155/2010/180242.

Full text

Abstract:

Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes a key concept from software security, known as proof-carrying code, into the reconfigurable hardware domain. We outline the PCH concept and discuss runtime combinational equivalence checking as a first online verification problem applying the concept. We present a prototype tool flow and experimental results demonstrating the feasibility and potential of the PCH approach.

APA, Harvard, Vancouver, ISO, and other styles

30

Bobda, Christophe, Kevin Cheng, Felix Mühlbauer, Klaus Drechsler, Jan Schulte, Dominik Murr, and Camel Tanougast. "Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware." International Journal of Reconfigurable Computing 2009 (2009): 1–9. http://dx.doi.org/10.1155/2009/161458.

Full text

Abstract:

We present a methodology based on self-organization to manage resources in networked embedded systems based on reconfigurable hardware. Two points are detailed in this paper, the monitoring system used to analyse the system and the Local Marketplaces Global Symbiosis (LMGS) concept defined for self-organization of dynamically reconfigurable nodes.

APA, Harvard, Vancouver, ISO, and other styles

31

DEL CAMPO, INÉS, JAVIER ECHANOBE, KOLDO BASTERRETXEA, and GUILLERMO BOSQUE. "SCALABLE ARCHITECTURE FOR HIGH-SPEED MULTIDIMENSIONAL FUZZY INFERENCE SYSTEMS." Journal of Circuits, Systems and Computers 20, no. 03 (May 2011): 375–400. http://dx.doi.org/10.1142/s0218126611007359.

Full text

Abstract:

This paper presents a scalable architecture suitable for the implementation of high-speed fuzzy inference systems on reconfigurable hardware. The main features of the proposed architecture, based on the Takagi–Sugeno inference model, are scalability, high performance, and flexibility. A scalable fuzzy inference system (FIS) must be efficient and practical when applied to complex situations, such as multidimensional problems with a large number of membership functions and a large rule base. Several current application areas of fuzzy computation require such enhanced capabilities to deal with real-time problems (e.g., robotics, automotive control, etc.). Scalability and high performance of the proposed solution have been achieved by exploiting the inherent parallelism of the inference model, while flexibility has been obtained by applying hardware/software codesign techniques to reconfigurable hardware. Last generation reconfigurable technologies, particularly field programmable gate arrays (FPGAs), make it possible to implement the whole embedded FIS (e.g., processor core, memory blocks, peripherals, and specific hardware for fuzzy inference) on a single chip with the consequent savings in size, cost, and power consumption. As a prototyping example, we implemented a complex fuzzy controller for a vehicle semi-active suspension system composed of four three-input FIS on a single FPGA of the Xilinx's Virtex 5 device family.

APA, Harvard, Vancouver, ISO, and other styles

32

Al-Wattar, A., S. Areibi, and G. Grewal. "An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems." International Journal of Reconfigurable Computing 2016 (2016): 1–24. http://dx.doi.org/10.1155/2016/9012909.

Full text

Abstract:

Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing, and network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a reconfigurable operating system (ROS). In this paper, an efficient ROS framework that aids the designer from the early design stages all the way to the actual hardware implementation is proposed and implemented. An efficient reconfigurable platform is implemented along with novel placement/scheduling algorithms. The proposed algorithms tend to reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software and hardware to efficiently utilize resources, and reduce computation time. A supporting framework for efficient mapping of execution units to task graphs in a run-time reconfigurable system is also designed. The framework utilizes an Island Based Genetic Algorithm flow that optimizes several objectives including performance, area, and power consumption. The proposed Island Based GA framework achieves on average 55.2% improvement over a single-GA implementation and an 80.7% improvement over a baseline random allocation and binding approach.

APA, Harvard, Vancouver, ISO, and other styles

33

S, Suji, and Radhika P. "Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 826. http://dx.doi.org/10.14419/ijet.v7i3.12.16511.

Full text

Abstract:

In this paper, a reconfigurable block FIR filter which supports variable filter length is proposed. This recon-figurable block FIR filter uses block based design. Hence, this is an algorithm free architecture. This proposed filter can be used for 5G air interface.The proposed filter produces more efficient power reduction than that of the other filter.The number of LUTs and registers are also reduced in the reconfigurable block FIR filter. The designed filter has been implemented in the ZYNQ xc7020 hardware device using the vivado 2015.4.The technique used for hardware implementation is the IP creation and debug-ging.The debugging helps in the monitoring and triggering the hardware device.

APA, Harvard, Vancouver, ISO, and other styles

34

OU, CHIEN-MIN. "EFFICIENT MUSIC RETRIEVAL SYSTEMS DESIGN BASED ON RECONFIGURABLE HARDWARE." Journal of Circuits, Systems and Computers 20, no. 05 (August 2011): 927–42. http://dx.doi.org/10.1142/s0218126611007694.

Full text

Abstract:

A novel field programmable gate array implementation of content-based music retrieval system is presented in this paper. The system adopts a novel hardware architecture for approximate string matching. The architecture is based on a simple shift-and-or algorithm. It has the advantages of low area cost and high throughput. Numerical results show that the proposed architecture has significantly lower CPU time over its software counterpart running on Pentium IV for large database and/or edit distances.

APA, Harvard, Vancouver, ISO, and other styles

35

SO, K., J. KIM, W. K. CHO, Y. S. KIM, and D. Y. SUH. "Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems." IEICE Transactions on Communications E89-B, no. 12 (December 1, 2006): 3242–49. http://dx.doi.org/10.1093/ietcom/e89-b.12.3242.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Sankara Phani, T. Siva, M. Sujatha, K. Hari Kishore, and M. Durga Prakash. "Implementation of FPGA based MRPMA for high performance applications." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 158. http://dx.doi.org/10.14419/ijet.v7i1.5.9139.

Full text

Abstract:

In the last few decay, Network on Chip’s (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE’s) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.

APA, Harvard, Vancouver, ISO, and other styles

37

An, Fubang, Lingli Wang, and Xuegong Zhou. "A High Performance Reconfigurable Hardware Architecture for Lightweight Convolutional Neural Network." Electronics 12, no. 13 (June 27, 2023): 2847. http://dx.doi.org/10.3390/electronics12132847.

Full text

Abstract:

Since the lightweight convolutional neural network EfficientNet was proposed by Google in 2019, the series of models have quickly become very popular due to their superior performance with a small number of parameters. However, the existing convolutional neural network hardware accelerators for EfficientNet still have much room to improve the performance of the depthwise convolution, squeeze-and-excitation module and nonlinear activation functions. In this paper, we first design a reconfigurable register array and computational kernel to accelerate the depthwise convolution. Next, we propose a vector unit to implement the nonlinear activation functions and the scale operation. An exchangeable-sequence dual-computational kernel architecture is proposed to improve the performance and the utilization. In addition, the memory architectures are designed to complete the hardware accelerator for the above computing architecture. Finally, in order to evaluate the performance of the hardware accelerator, the accelerator is implemented based on Xilinx XCVU37P. The results show that the proposed accelerator can work at the main system clock frequency of 300 MHz with the DSP kernel at 600 MHz. The performance of EfficientNet-B3 in our architecture can reach 69.50 FPS and 255.22 GOPS. Compared with the latest EfficientNet-B3 accelerator, which uses the same FPGA development board, the accelerator proposed in this paper can achieve a 1.28-fold improvement of single-core performance and 1.38-fold improvement of performance of each DSP.

APA, Harvard, Vancouver, ISO, and other styles

38

Ou, Chien-Min, Tsung-Yi yu, Wen-Jyi Hwang, and Tsung-Che Chiang. "Efficient Architecture For Island Genetic Algorithm in Reconfigurable Hardware." Intelligent Automation & Soft Computing 18, no. 4 (January 2012): 413–30. http://dx.doi.org/10.1080/10798587.2012.10643252.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Kim, Y., and H. Jung. "Reconfigurable hardware architecture for faster descriptor extraction in SURF." Electronics Letters 54, no. 4 (February 2018): 210–12. http://dx.doi.org/10.1049/el.2017.3133.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

José Garcia Neto Segundo, Edgar, Nadia Nedjah, and Luiza de Macedo Mourelle. "A scalable parallel reconfigurable hardware architecture for DNA matching." Integration 46, no. 3 (June 2013): 240–46. http://dx.doi.org/10.1016/j.vlsi.2013.01.002.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Le Ly, Daniel, and Paul Chow. "High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines." IEEE Transactions on Neural Networks 21, no. 11 (November 2010): 1780–92. http://dx.doi.org/10.1109/tnn.2010.2073481.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Ravi, Aadithya, Easwara E. A. Moorthy, D. Vidya, and G. Mahesh Kumar. "Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing." Applied Mechanics and Materials 110-116 (October 2011): 5057–62. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5057.

Full text

Abstract:

Specific hardware solutions are always faster than programmable architectures. But dedicated architectures have the inherent disadvantage of inflexibility. Changes in the algorithm or extensions of the application are handled easily by programmable architectures. The approach discussed here involves a hardware-software co-design to optimize on performance and programmability. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired. The functional memory would consist of pre-designs (FPGA based) of certain objects, each of which could be used to configure an FPGA to perform a particular function.

APA, Harvard, Vancouver, ISO, and other styles

43

Eddine, Khamlich Salah, Khamlich Fathallah, Issam Atouf, and Benrabh Mohamed. "Parallel Implementation of Nios Ii Multiprocessors, Cepstral Coefficients of Mel Frequency and MLP Architecture in Fpga: the Application of Speech Recognition." WSEAS TRANSACTIONS ON SIGNAL PROCESSING 16 (January 13, 2021): 146–54. http://dx.doi.org/10.37394/232014.2020.16.16.

Full text

Abstract:

Speech processing in real time requires the use of fast, reconfigurable electronic circuits capable of handling large amounts of information generated by the audio source. This article presents hardware implementations of a multilayer perceptron (MLP) and the MFCC algorithm for speech recognition. These algorithms have been implemented in hardware and tested in an on-board electronic card based on a reconfigurable circuit (FPGA). We also present a comparative study between several architectures of MLP and with the literature on the level of costs with regard to the surface of silicon, the speed and the computing resources required. Following the FPGA circuit modification, we created NIOSII processors to physically implement the architecture of ANN-type MLPs and MFCC speech recognition algorithms and perform real-time speech recognition functions.

APA, Harvard, Vancouver, ISO, and other styles

44

Jameil, Ahmed K., Yassir A. Ahmed, and Saad Albawi. "Efficient FIR Filter Architecture using FPGA." Recent Advances in Computer Science and Communications 13, no. 1 (March 13, 2020): 91–98. http://dx.doi.org/10.2174/2213275912666190603115506.

Full text

Abstract:

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

APA, Harvard, Vancouver, ISO, and other styles

45

Belaid, Ikbel, Fabrice Muller, and Maher Benjemaa. "New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA." International Journal of Reconfigurable Computing 2010 (2010): 1–20. http://dx.doi.org/10.1155/2010/980762.

Full text

Abstract:

Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36% of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%.

APA, Harvard, Vancouver, ISO, and other styles

46

Dalbouchi, Roukaya, Salah Dhahri, Majdi Elhajji, and Abdelkrim Zitouni. "New Hardware Static and Reconfigurable Architectures for Video Watermarking System." Journal of Circuits, Systems and Computers 29, no. 10 (December 20, 2019): 2050168. http://dx.doi.org/10.1142/s0218126620501686.

Full text

Abstract:

The watermarking technique is an active subject in current research used as a solution for copyright protection in multimedia documents. In this paper, we propose the first hardware invisible robust video watermarking application based on motion estimation. Since the designers of this application face many challenges, two types of architecture are performed: static and dynamic/partial reconfigurable architecture. The proposed architecture is adapted to HEVC encoded video. Two protection techniques are linked up: the digital watermarking to insert a watermark in the video, and the scrambling technique for overall video protection. The watermark embedding is treated in the horizontal and vertical components of even motion vectors. Eventually, the entire vectors are scrambled. The used watermark is a binary sequence where only one bit is inserted into the horizontal and the vertical components of motion vectors. The recommended architecture applies for slow and fast video sequence, where we use a motion estimator reconfigured according to the macro-block video movement. We also utilize a pipeline structure and a clock gating module to increase computing power and reduce power consumption. Experimental results show that the suggested static and dynamic/partial reconfigurable architecture guarantees material efficiency and superior performance in terms of frequency and power consumption.

APA, Harvard, Vancouver, ISO, and other styles

47

Xiong, Hao, Kelin Sun, Bing Zhang, Jingchuan Yang, and Huiping Xu. "Deep-Sea: A Reconfigurable Accelerator for Classic CNN." Wireless Communications and Mobile Computing 2022 (February 2, 2022): 1–23. http://dx.doi.org/10.1155/2022/4726652.

Full text

Abstract:

To meet the changing real-time edge engineering application requirements of CNN, aiming at the lack of universality and flexibility of CNN hardware acceleration architecture based on ARM+FPGA, a general low-power all pipelined CNN hardware acceleration architecture is proposed to cope with the continuously updated CNN algorithm and accelerate in hardware platforms with different resource constraints. In the framework of the general hardware architecture, a basic instruction set belonging to the architecture is proposed, which can be used to calculate and configure different versions of CNN algorithms. Based on the instruction set, the configurable computing subsystem, memory management subsystem, on-chip cache subsystem, and instruction execution subsystem are designed and implemented. In addition, in the processing of convolution results, the on-chip storage unit is used to preprocess the convolution results, to speed up the activation and pooling calculation process in parallel. Finally, the accelerator is modeled at the RTL level and deployed on the XC7Z100 heterogeneous device. The lightweight networks YOLOv2-tiny and YOLOv3-tiny commonly used in engineering applications are verified on the accelerator. The results show that the peak performance of the accelerator reaches 198.37 GOP/s, the clock frequency reaches 210 MHz, and the power consumption is 4.52 w under 16-bit width.

APA, Harvard, Vancouver, ISO, and other styles

48

QIAO, CHUNMING. "ON DESIGNING COMMUNICATION-INTENSIVE ALGORITHMS FOR A SPANNING OPTICAL BUS BASED ARRAY." Parallel Processing Letters 05, no. 03 (September 1995): 499–511. http://dx.doi.org/10.1142/s012962649500045x.

Full text

Abstract:

The Reconfigurable Array with Spanning Optical Buses (or RASOB) architecture provides flexible reconfiguration and strong connectivities with low hardware and control complexities. We use a parallel implementation of the matrix transposition as well as multiplication algorithms as an example to show how the architectural capabilities can be taken advantage of in designing efficient parallel algorithms.

APA, Harvard, Vancouver, ISO, and other styles

49

Seo, Jungwon, Jamie Paik, and Mark Yim. "Modular Reconfigurable Robotics." Annual Review of Control, Robotics, and Autonomous Systems 2, no. 1 (May 3, 2019): 63–88. http://dx.doi.org/10.1146/annurev-control-053018-023834.

Full text

Abstract:

This article reviews the current state of the art in the development of modular reconfigurable robot (MRR) systems and suggests promising future research directions. A wide variety of MRR systems have been presented to date, and these robots promise to be versatile, robust, and low cost compared with other conventional robot systems. MRR systems thus have the potential to outperform traditional systems with a fixed morphology when carrying out tasks that require a high level of flexibility. We begin by introducing the taxonomy of MRRs based on their hardware architecture. We then examine recent progress in the hardware and the software technologies for MRRs, along with remaining technical issues. We conclude with a discussion of open challenges and future research directions.

APA, Harvard, Vancouver, ISO, and other styles

50

Melnyk, Viktor A., and Vladyslav V. Hamolia. "Investigation of reconfigurable hardware platforms for 5G protocol stack functions acceleration." Applied Aspects of Information Technology 6, no. 1 (April 10, 2023): 84–99. http://dx.doi.org/10.15276/aait.06.2023.7.

Full text

Abstract:

Open RAN and 5G are two key technologies designed to qualitatively improve network infrastructure and provide greater flexibility and efficiency to mobile operators and users. 5G creates new capabilities for high-speed Internet, Internet of Things, telemedicine and many other applications, while Open RAN enables open and standardized network architectures, which reduces cost and risk for operators and promotes innovations. Given the growing number of users and data volumes, the purely software implementation of certain functions of the 5G protocol, and especially computationally complex ones, requires significant computer resources and energy. These, for example, are low-density parity-check (LDPC) coding, FFT and iFFT algorithms on physical (PHY) layer, and NEA and NIA security algorithms on Packet Data Convergence Protocol (PDCP) layer. Therefore, one of the activity areas in the development of means for 5G systems is the hardware acceleration of such functions execution, which provides the possibility of processing large volumes of data in real time and with high efficiency. The high-performance hardware basis for implementing these functions today is field-programmable gate array (FPGA) integrated circuits. Along with this, the efficiency of the 5G protocol stack functions hardware acceleration depends significantly on the size of the data packets transmitted to the hardware accelerator. As experience shows, for certain types of architecture of computer systems with accelerators, the acceleration value can take even a negative value. This necessitates the search for alternative architectural solutions for the implementation of such systems. In this article the approaches for hardware acceleration using reconfigurable FPGA-based computing components are explored, their comparative analysis is performed, and architectural alternatives are evaluated for the implementation of a computing platform to perform the functions of the 5G protocol stack with hardware acceleration of PHY and medium access control (MAC) layers functions.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Reconfigurable Hardware Architecture'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles