Journal articles: 'Reconfigurable computer systems'

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Brebner, G., and B. Hutchings. "Editorial: Reconfigurable systems." IEE Proceedings - Computers and Digital Techniques 147, no. 3 (2000): 133. http://dx.doi.org/10.1049/ip-cdt:20000664.

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Insaurralde, Carlos. "Reconfigurable computer architectures for dynamically adaptable avionics systems." IEEE Aerospace and Electronic Systems Magazine 30, no. 9 (September 2015): 46–53. http://dx.doi.org/10.1109/maes.2015.140077.

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Feiler, P., and J. Li. "Managing inconsistency in reconfigurable systems." IEE Proceedings - Software 145, no. 5 (1998): 172. http://dx.doi.org/10.1049/ip-sen:19982300.

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Lienen, Christian, and Marco Platzner. "Design of Distributed Reconfigurable Robotics Systems with ReconROS." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (September 30, 2022): 1–20. http://dx.doi.org/10.1145/3494571.

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Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS , a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.

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Tredennick, Nick, and Brion Shimamoto. "The Inevitability of Reconfigurable Systems." Queue 1, no. 7 (October 2003): 34–43. http://dx.doi.org/10.1145/957717.957767.

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Kindratenko, Volodymyr, and Duncan Buell. "Reconfigurable Systems Summer Institute 2007." Parallel Computing 34, no. 4-5 (May 2008): 199–200. http://dx.doi.org/10.1016/j.parco.2008.03.006.

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Etherington, Carole J., Matthew W. Anderson, Eric Bach, Jon T. Butler, and Pantelimon Stănică. "A Parallel Approach in Computing Correlation Immunity up to Six Variables." International Journal of Foundations of Computer Science 27, no. 04 (June 2016): 511–28. http://dx.doi.org/10.1142/s0129054116500131.

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We show the use of a reconfigurable computer in computing the correlation immunity of Boolean functions of up to 6 variables. Boolean functions with high correlation immunity are desired in cryptographic systems because they are immune to correlation attacks. The SRC-6 reconfigurable computer was programmed in Verilog to compute the correlation immunity of functions. This computation is performed at a rate that is 190 times faster than a conventional computer. Our analysis of the correlation immunity is across all n-variable Boolean functions, for 2 ≤ n ≤ 6, thus obtaining, for the first time, a complete distribution of such functions. We also compare correlation immunity with two other cryptographic properties, nonlinearity and degree.

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Schevelev, S. S. "Reconfigurable Modular Computing System." Proceedings of the Southwest State University 23, no. 2 (July 9, 2019): 137–52. http://dx.doi.org/10.21869/2223-1560-2019-23-2-137-152.

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Purpose of research. A reconfigurable computer system consists of a computing system and special-purpose computers that are used to solve the tasks of vector and matrix algebra, pattern recognition. There are distinctions between matrix and associative systems, neural networks. Matrix computing systems comprise a set of processor units connected through a switching device with multi-module memory. They are designed to solve vector, matrix and data array problems. Associative systems contain a large number of operating devices that can simultaneously process multiple data streams. Neural networks and neurocomputers have high performance when solving problems of expert systems, pattern recognition due to parallel processing of a neural network.Methods. An information graph of the computational process of a reconfigurable modular system was plotted. Structural and functional schemes, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words were developed. Software for modelling the operation of the arithmetic-symbol processor, specialized computing modules, and switching systems was developed.Results. A block diagram of a reconfigurable computing modular system was developed. The system consists of compatible functional modules and is capable of static and dynamic reconfiguration, has a parallel connection structure of the processor and computing modules through the use of interface channels. It consists of an arithmeticsymbol processor, specialized computing modules and switching systems; it performs specific tasks of symbolic information processing, arithmetic and logical operations.Conclusion. Systems with a reconfigurable structure are high-performance and highly reliable computing systems that consist of integrated processors in multi-machine and multiprocessor systems. Reconfigurability of the structure provides high system performance due to its adaptation to computational processes and the composition of the processed tasks.

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Levin, Il’ya, Aleksey Dordopulo, Yuriy Doronchenko, Maksim Raskladkin, and Aleksandr Fedorov. "Immersion cooling system for FPGA-based reconfigurable computer systems." Program Systems: Theory and Applications 7, no. 4 (2016): 65–81. http://dx.doi.org/10.25209/2079-3316-2016-7-4-65-81.

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LASKOWSKI, W., and I. J. JÓŹWIAK. "Reconfigurable hardware and safety and reliability of computer systems." Risk, Decision and Policy 8, no. 2-3 (May 2003): 143–50. http://dx.doi.org/10.1080/713926643.

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Fragner, Heinrich. "Usage of a reconfigurable computer to simulate multiparticle systems." Computer Physics Communications 176, no. 5 (March 2007): 327–33. http://dx.doi.org/10.1016/j.cpc.2006.11.005.

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Kozov, Aleksei V. "MODELS AND DESIGNING METHODS FOR THE DYNAMICALLY RECONFIGURABLE GROUP CONTROL SYSTEM FOR MOBILE ROBOTS." АВТОМАТИЗАЦИЯ ПРОЦЕССОВ УПРАВЛЕНИЯ 63, no. 1 (2021): 130–39. http://dx.doi.org/10.35752/1991-2927-2021-1-63-130-139.

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High adaptability is an important requirement for the control system over a group of mobile robots operating in a nondeterministic changing environment. The group control system must ensure that the group task is completed when the structure of the group or the environment changes. Such adaptability can be achieved through dynamic reconfiguration of the control system. The article discusses the mathematical models of a dynamically reconfigurable system from the standpoint of computer-aided design. A review of mathematical models of variable structure system, reconfigurable control systems and their design methods is presented. The paper deals with set-theoretic, analytical, discrete-event models of variable structure systems and methodologies of designing reconfigurable systems. It is shown that the existing design methods do not fully provide the required adaptability of designed group control system. The paper compares the group control system and the reconfigurable multiprocessor computing system and shows how to increase adaptability and autonomy of designed control system using principles of reconfigurable computing systems designing.

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Bruni, Roberto, Ugo Montanari, and Vladimiro Sassone. "Observational congruences for dynamically reconfigurable tile systems." Theoretical Computer Science 335, no. 2-3 (May 2005): 331–72. http://dx.doi.org/10.1016/j.tcs.2004.10.044.

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Ramamoorthy and Ma. "Optimal Reconfiguration Strategies for Reconfigurable Computer Systems with no Repair." IEEE Transactions on Computers C-35, no. 3 (March 1986): 278–80. http://dx.doi.org/10.1109/tc.1986.1676751.

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Siegel, H. J., J. B. Armstrong, and D. W. Watson. "Mapping computer-vision-related tasks onto reconfigurable parallel-processing systems." Computer 25, no. 2 (February 1992): 54–63. http://dx.doi.org/10.1109/2.121475.

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Varela, Carlos, and Gul Agha. "Programming dynamically reconfigurable open systems with SALSA." ACM SIGPLAN Notices 36, no. 12 (December 2001): 20–34. http://dx.doi.org/10.1145/583960.583964.

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Dordopulo, A. I. "APPLICATION OF PERFORMANCE REDUCTION METHODS FOR MINIMIZATION OF ANALYZED NUMBER OF PARALLEL PROGRAM VARIANTS." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 183 (September 2019): 43–49. http://dx.doi.org/10.14489/vkit.2019.09.pp.043-049.

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In this paper, we review and compare the methods of parallel applications’ development based on the automatic program parallelizing for computer systems with shared and distributed memory and on the information graph’s hardware costs and performance reduction for reconfigurable computer systems. The increase in the number of computer system’s units or in the problem’s dimension leads to the significant growth of the automatic parallelization complexity for a procedural program. As a result, the obtainment of parallelizing results in acceptable time using state-of-the-art computer systems is very problematic. In reconfigurable computer systems, the reduction of absolutely parallel information graph of a problem is applied for the parallel program creation. The information graph illustrates the parallelizing and pipelining of computations. In addition to the traditionally practiced reduction of basic subgraphs’ number, the reductions of computational operations’ quantity and of data digit capacity can be utilized for the performance or hardware costs’ scaling. We have proved that the methods of information graph hardware costs and performance reduction provide a considerable decrease in the number of steps needed for adaptation of parallel application to reconfigurable computer systems’ architectures in comparison with automatic parallelizing. We have proved the theorem of coefficient value at sequential reduction, the theorem of increase in reduction coefficient at custom value and the theorem of commutativity of various reduction transformations. The proved theorems help to find a rational sequence of reduction transformations.

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Yasudo, Ryota, José G. F. Coutinho, Ana-Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, and Ce Guo. "Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms." ACM Transactions on Reconfigurable Technology and Systems 14, no. 3 (September 30, 2021): 1–21. http://dx.doi.org/10.1145/3452742.

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Next-generation high-performance computing platforms will handle extreme data- and compute-intensive problems that are intractable with today’s technology. A promising path in achieving the next leap in high-performance computing is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators such as FPGAs, which have been shown to speed up compute-intensive tasks with reduced power consumption. However, assessing the feasibility of large-scale heterogeneous systems requires fast and accurate performance prediction. This article proposes Performance Estimation for Reconfigurable Kernels and Systems (PERKS), a novel performance estimation framework for reconfigurable dataflow platforms. PERKS makes use of an analytical model with machine and application parameters for predicting the performance of multi-accelerator systems and detecting their bottlenecks. Model calibration is automatic, making the model flexible and usable for different machine configurations and applications, including hypothetical ones. Our experimental results show that PERKS can predict the performance of current workloads on reconfigurable dataflow platforms with an accuracy above 91%. The results also illustrate how the modelling scales to large workloads, and how performance impact of architectural features can be estimated in seconds.

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DeGaspari, John. "All in the Family." Mechanical Engineering 124, no. 02 (February 1, 2002): 56–58. http://dx.doi.org/10.1115/1.2002-feb-5.

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This article focuses on reconfigurable machining systems. These systems have lately caught the attention of some manufacturers who need something that is more flexible than a dedicated line and produces goods faster than a shop of CNC machines. The lines are called reconfigurable because they consist of modules and, once they are programmed, can be switched quickly to turn out different, but similar pieces from a family of products. Proponents say that reconfigurable machining systems have carved out a niche between two other alternatives—dedicated transfer lines, which are optimized for producing large volumes of specific parts, and computer numerical control machine tools, which have a high degree of flexibility but are slower to finish products. Reconfigurable machining systems have been developed for the automotive industry, for instance, as car companies have increasingly outsourced their production to tier-one suppliers and demanded price reductions.

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Huffmire, Ted, Timothy Levin, Thuy Nguyen, Cynthia Irvine, Brett Brotherton, Gang Wang, Timothy Sherwood, and Ryan Kastner. "Security Primitives for Reconfigurable Hardware-Based Systems." ACM Transactions on Reconfigurable Technology and Systems 3, no. 2 (May 2010): 1–35. http://dx.doi.org/10.1145/1754386.1754391.

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Göhringer, Diana, Thomas Perschke, Michael Hübner, and Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.

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Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.

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Левин, И. И., А. И. Дордопуло, Ю. И. Доронченко, М. К. Раскладкин, and А. М. Федоров. "A reconfigurable computer system based on FPGAs with liquid cooling." Numerical Methods and Programming (Vychislitel'nye Metody i Programmirovanie), no. 1 (March 29, 2016): 111–20. http://dx.doi.org/10.26089/nummet.v17r111.

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Статья посвящена проблемам построения перспективных реконфигурируемых вычислительных систем c жидкостным охлаждением для программируемых логических интегральных схем семейства Xilinx Virtex UltraScale. Рассматриваются архитектура, компоновка и сравнительные технические характеристики систем погружного жидкостного охлаждения. Приводятся результаты расчетов, макетирования и экспериментальной проверки основных технических решений созданного вычислительного модуля нового поколения для построения высокопроизводительных вычислительных систем с жидкостным охлаждением с производительностью 1 Пфлопс в стандартном вычислительном шкафу высотой 47U при потребляемой мощности 150 кВт. Реконфигурируемая вычислительная система с жидкостным охлаждением обеспечивает существенное преимущество по таким технико-экономическим параметрам, как реальная и удельная производительность, энергоэффективность, массогабаритные характеристики и другим по сравнению с аналогичными системами. The paper deals with problems of design of promising reconfigurable computer systems with liquid cooling for Xilinx Virtex UltraScale FPGAs. Architecture, placement and comparative technical parameters of systems with immersion liquid cooling are considered. Results of design, prototyping and experimental testing of the principal technical solutions of the designed computational module of the next generation are discussed. The computational module is intended for the creation of high-performance computer systems with liquid cooling with performance of 1 PFlops in a standard 47U computer rack with power of 150 kWatt. The reconfigurable computer system with liquid cooling provides considerable advantage in such technical and economical parameters as the real performance and the specific performance, power efficiency, mass and dimension parameters, etc. in comparison with similar systems.

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Sueyoshi, T. "Special Section on Reconfigurable Systems." IEICE Transactions on Information and Systems E90-D, no. 12 (December 1, 2007): 1903–4. http://dx.doi.org/10.1093/ietisy/e90-d.12.1903.

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Aris, Mohd Aziz, Mohd Tarmizi Ali, Nurulhuda Abd Rahman, and Idnin Pasya Ibrahim. "Frequency Reconfigurable Antenna Array Using Defected Ground Structure for Outdoor Wireless Communication Systems." International Journal of Electrical & Electronic Systems Research (IEESR) 9, no. 1 (June 24, 2019): 33. http://dx.doi.org/10.24191/ieesr.v9i1.1372.

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This paper proposes frequency reconfigurable antenna for outdoor wireless communication systems, the 4 x 4 array antenna has designed at two resonant frequencies 7.5 GHz and 8.85 GHz. The periodic dumbbell geometry etched on the ground layer newly proposed with dual functionality, to control desired frequency and to couple radiating patches at the top substrate with feeding line at the bottom substrate. The reconfigurability of the patch antenna is controlled by utilizing the copper pad of the feeding network with OPEN and SHORT states. The reconfigurable antenna has been simulated and optimized using Computer Simulation Technology (CST) to get the desired responds. The good agreement between simulation and measured results indicates that the frequency reconfigurable patch array antenna using Periodic Dumbbell Slotted Aperture Structure (FRPDSA) is feasible to support outdoor wireless communication systems.

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Barnard, M., and S. McLaughlin. "Reconfigurable terminals for mobile communication systems." Electronics & Communication Engineering Journal 12, no. 6 (December 1, 2000): 281–92. http://dx.doi.org/10.1049/ecej:20000607.

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Halstead, Robert J., Jason Villarreal, and Walid A. Najjar. "Compiling irregular applications for reconfigurable systems." International Journal of High Performance Computing and Networking 7, no. 4 (2014): 258. http://dx.doi.org/10.1504/ijhpcn.2014.062725.

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Landers, Thomas L., Melinda K. Beavers, Malik Sadiq, and Don E. Stuart. "Software for dynamic reconfigurable order picking systems." Computers & Industrial Engineering 27, no. 1-4 (September 1994): 245–48. http://dx.doi.org/10.1016/0360-8352(94)90281-x.

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Kalyaev, I. A., I. I. Levin, and L. M. Slasten. "High Performance Reconfigurable Computer Systems on the base of FPGA technology." IFAC Proceedings Volumes 44, no. 1 (January 2011): 9170–75. http://dx.doi.org/10.3182/20110828-6-it-1002.00275.

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Alekseev, K. N., I. I. Levin, and D. A. Sorokin. "Implementation of Surface-Related Multiple Prediction Problem on Reconfigurable Computer Systems." Bulletin of the South Ural State University. Series "Mathematical Modelling, Programming and Computer Software" 13, no. 1 (2020): 81–94. http://dx.doi.org/10.14529/mmp200106.

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Kocherga, M. S., and V. I. Shmoylov. "THE DESIGN OF RECONFIGURABLE COMPUTER SYSTEMS BASED ON HOMOGENEOUS COMPUTING ENVIRONMENTS." Vestnik Yuzhnogo nauchnogo tsentra 4, no. 2 (2008): 18–26. http://dx.doi.org/10.23885/1813-4289-2008-4-2-18-26.

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Kalyaev, I. A., I. I. Levin, A. I. Dordopulo, and L. M. Slasten. "Reconfigurable Computer Systems Based on Virtex-6 and Virtex-7 FPGAs." IFAC Proceedings Volumes 46, no. 28 (2013): 210–14. http://dx.doi.org/10.3182/20130925-3-cz-3023.00009.

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Levin, I. I., V. A. Gudkov, G. A. Еvstafiev, A. I. Dordopulo, A. A. Gulenok, and A. V. Bovkun. "TECHNIQUE OF C PROGRAM TRANSLATION FOR RECONFIGURABLE AND HYBRID COMPUTER SYSTEMS BASED ON FIELD-PROGRAMMABLE GATE ARRAYS." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 186 (December 2019): 54–60. http://dx.doi.org/10.14489/vkit.2019.12.pp.054-060.

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In this paper, we thoroughly consider the technique of conversion of procedural programs in C to configuration files for field-programmable gate arrays used in the toolkit for programming of reconfigurable and hybrid computer systems. The creation of parallel program in the COLAMO (Common Oriented Language for Architecture of Multi Objects) language using the analysis results of information dependences in the initial procedural program and its further conversion to a parallel and pipeline form are the distinctive characteristics of the technique. We addressed the methods of scalar splitting and array extension by iterations, which are applied for the fulfillment of the single assignment and unique substitution rules in parallel program and the saving of information communications of the initial procedural program. The technique of conversion of automatically created parallel program to the scalable parallel and pipeline form is presented. The “Procrustes” preprocessor adapts the form for different architectures and configurations of reconfigurable and hybrid computer systems. Owing to the described methodology, it is possible to synthesize a resource-independent scalable COLAMO-application, which can adapt to available computational resource by changing of several constants in automatic mode without any considerable modification of the program source code. Then, the scalable COLAMO-applicationis translated by the COLAMO-translator into field-programmable gate arrays configuration files for the specified reconfigurable computer resource.

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Weinhardt, M., and W. Luk. "Memory access optimisation for reconfigurable systems." IEE Proceedings - Computers and Digital Techniques 148, no. 3 (May 1, 2001): 105–12. http://dx.doi.org/10.1049/ip-cdt:20010514.

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Daneshgaran, Fred, and Josef Noll. "Special issue: Reconfigurable wireless communication systems." Wireless Communications and Mobile Computing 2, no. 8 (2002): 785–87. http://dx.doi.org/10.1002/wcm.117.

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Fukuda, Toshio, and Seiya Nakagawa. "Dynamically Reconfigurable Robotic System." Journal of Robotics and Mechatronics 6, no. 5 (October 20, 1994): 351–55. http://dx.doi.org/10.20965/jrm.1994.p0351.

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This paper deals with experimental aspects of a practical realization method for the cellular robotic system (CEBOT). CEBOT is a dynamically reconfigurable robotic systems which can reconfigure robots in an optimal structure, depending on working purposes and environments This is one of the autonomous distributed, cooperative systems, which are capable of carrying out communication, connection, and separation between functional units, called ""cells"" in this paper. Such a hardware construction has long been desired for the new generation of robotic systems. In this paper, it is shown that the modified CEBOT does not require the precise positioning accuracy in the cell connections, unlike the series I in a previous report. With the on-board photosensors and ultrasonic sensors, the newly built robotic system can perform the automatic approach, connection and separation successfully.

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Melnyk, Anatoliy, Viktor Melnyk, and Liubomyr Tsyhylyk. "Tasks Scaling with Chameleon© C2HDL Design Tool in Self-Configurable Computer Systems Based on Partially Reconfigurable FPGAs." Advances in Cyber-Physical Systems 1, no. 1 (February 23, 2016): 34–44. http://dx.doi.org/10.23939/acps2016.01.034.

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Chau, Thomas C. P., Xinyu Niu, Alison Eele, Jan Maciejowski, Peter Y. K. Cheung, and Wayne Luk. "Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems." ACM Transactions on Reconfigurable Technology and Systems 7, no. 4 (January 23, 2015): 1–17. http://dx.doi.org/10.1145/2629469.

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Mahram, Atabak, and Martin C. Herbordt. "NCBI BLASTP on High-Performance Reconfigurable Computing Systems." ACM Transactions on Reconfigurable Technology and Systems 7, no. 4 (January 23, 2015): 1–20. http://dx.doi.org/10.1145/2629691.

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PAN, TIEN-TAI, and SHUN-SHII LIN. "THE TRANSITIVE CLOSURE AND RELATED ALGORITHMS OF DIGRAPH ON THE RECONFIGURABLE ARCHITECTURE." Parallel Processing Letters 21, no. 01 (March 2011): 27–43. http://dx.doi.org/10.1142/s0129626411000059.

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The reconfigurable architecture is a parallel computation model that consists of many processor elements (PEs) and a reconfigurable bus system. There are many variant proposed reconfigurable architectures, for example, reconfigurable mesh (R-Mesh), directional reconfigurable mesh (DR-Mesh), processor arrays with reconfigurable bus systems (PARBS), complete directional processor arrays with reconfigurable bus systems (CD-PARBS), reconfigurable multiple bus machine (RMBM), directional reconfigurable multiple bus machine (directional RMBM), and etc. In this paper, a transitive closure (TC) algorithm of digraph is proposed on the models without the directional capability (non-directional). Some related digraph problems, such as strongly connected digraph, strongly connected component (SCC), cyclic checking, and tree construction, can also be resolved by modifying our transitive closure algorithm. All the proposed algorithms are designed on a three-dimensional (3-D) n×n×n non-directional reconfigurable mesh, n is the number of vertices in a digraph D, and can resolve the respective problems in O(log d(D)) time, d(D) is the diameter of the digraph D. The cyclic checking problem can be further reduced to O(log c(D)) time, c(D) is the minimum distance of cycles in the digraph D. There exist two different approaches: the matrix multiplication approach on the non-directional models for algebraic path problems (APP) and s-t connectivity approach on the directional models. In this paper, we will use the tree construction algorithm to prove those two approaches are insufficient to resolve all digraph problems and demonstrate why our approach is so important and innovative for digraph problems on the reconfigurable models.

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Monien, Burkhard, Ralf Diekmann, and Reinhard Lüling. "The Construction of Large Scale Reconfigurable Parallel Computing Systems (The Architecture of the SC320)." International Journal of Foundations of Computer Science 08, no. 03 (September 1997): 347–61. http://dx.doi.org/10.1142/s0129054197000227.

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Reconfigurable communication networks for massively parallel multiprocessor systems offer the possibility to realize a number of application demands like special communication patterns or real-time requirements. This paper presents the design principle of a reconfigurable network which is able to realize any graph of maximal degree four. The architecture is based on a special multistage Clos network, constructed out of a number of static routing switches of equal size. Upper bounds on the cut size of 4-regular graphs, if split into a number of clusters, allow minimizing the number of switches and connections while still offering the desired reconfiguration capabilities as well as large scalability and flexible multi-user access. Efficient algorithms configuring the architecture are based on an old result by Petersen27 about the decomposition of regular graphs. The concept presented here is the basis for the Parsytec SC series of reconfigurable MPP-systems. The currently largest realization with 320 processors is presented in greater detail.

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Pfundt, Benjamin, Marc Reichenbach, and Dietmar Fey. "Comprehensive curriculum for reconfigurable heterogeneous computer architecture education." IET Circuits, Devices & Systems 11, no. 4 (July 2017): 292–98. http://dx.doi.org/10.1049/iet-cds.2016.0399.

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Chatzikonstantinou, George, and Kostas Kontogiannis. "Run-time requirements verification for reconfigurable systems." Information and Software Technology 75 (July 2016): 105–21. http://dx.doi.org/10.1016/j.infsof.2016.04.005.

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Wallner, Sebastian. "Micro-Task Processing in Heterogeneous Reconfigurable Systems." Journal of Computer Science and Technology 20, no. 5 (September 2005): 624–34. http://dx.doi.org/10.1007/s11390-005-0624-x.

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THANGAVEL, P., and V. P. MUTHUSWAMY. "A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM." Parallel Processing Letters 03, no. 02 (June 1993): 157–64. http://dx.doi.org/10.1142/s0129626493000198.

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A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

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Levin, I. I., and M. D. Chekina. "THE PARALLEL-PIPELINED IMPLEMENTATION OF THE FRACTAL IMAGE COMPRESSION FOR RECONFIGURABLE COMPUTING SYSTEMS." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 202 (April 2021): 37–44. http://dx.doi.org/10.14489/vkit.2021.04.pp.037-044.

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The developed fractal image compression method, implemented for reconfigurable computing systems is described. The main idea parallel fractal image compression based on parallel execution pairwise comparison of domain and rank blocks. Achievement high performance occurs at the expense of simultaneously comparing maximum number of pairs. Implementation fractal image compression for reconfigurable computing systems has two critical resources, as number of input channels and FPGA Look-up Table (LUT). The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel, preliminarily produced performance reduction parallel computational structure. The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel computations organiation. For using parallel-pipeline computations organization, preliminarily have produce performance reduction parallel computational structure. Each operator has routed to computational structure sequentially (bit by bit) to save computational resources and reduces equipment downtime. Storing iterated functions system coefficients for image encoding has been introduced in data structure, which correlates between corresponding parameters the numbers of rank and domain blocks. Applying this approach for parallel-pipeline programs allows scaling computing structure to plurality programmable logic arrays (FPGAs). Task implementation on the reconfigurable computer system Tertius-2 containing eight FPGAs 15 000 times provides performed acceleration relatively with universal multi-core processor, and 18 – 25 times whit to existing solutions for FPGAs.

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Del Re, E., S. Morosi, D. Marabissi, L. Mucchi, L. Pierucci, and L. S. Ronga. "Reconfigurable Antenna for Future Wireless Communication Systems." Wireless Personal Communications 42, no. 3 (January 23, 2007): 405–30. http://dx.doi.org/10.1007/s11277-006-9185-8.

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Sklyarov, Valery, Iouliia Skliarova, and João Silva. "On-Chip Reconfigurable Hardware Accelerators for Popcount Computations." International Journal of Reconfigurable Computing 2016 (2016): 1–11. http://dx.doi.org/10.1155/2016/8972065.

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Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1) designed in FPGAs and (2) implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads (in experiments with PCI express) are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking into account all the involved communication overheads between the programmable logic and the processing systems).

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Aguirre, Nazareno, and Tom Maibaum. "Hierarchical Temporal Specifications of Dynamically Reconfigurable Component Based Systems." Electronic Notes in Theoretical Computer Science 108 (December 2004): 69–81. http://dx.doi.org/10.1016/j.entcs.2004.01.013.

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Rösiö, Carin, and Jessica Bruch. "Exploring the design process of reconfigurable industrial production systems." Journal of Manufacturing Technology Management 29, no. 1 (January 15, 2018): 85–103. http://dx.doi.org/10.1108/jmtm-06-2016-0090.

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Purpose The purpose of this paper is to explore activities, challenges, and suggest tactics for the design of industrial reconfigurable production systems that can easily adapt to changing market opportunities. Design/methodology/approach The paper synthesizes the empirical findings of seven case studies including 47 in-depth interviews at four manufacturing companies. Findings A conceptual production system design process and including activities that enables a long-term perspective considering reconfigurability is proposed. Additionally, critical challenges indicating that reconfigurable production system design is not a trivial issue but one that requires separate control and coordination are identified and tactics to overcome the challenges described. Research limitations/implications The authors propose a process for designing reconfigurable production systems that are better suited to adjust to future needs. The knowledge of reconfigurability from the reconfigurable manufacturing system literature is applied in the general production system literature field. This study contributes to a clearer picture of managerial challenges that need to be dealt with when designing a reconfigurable production system. Practical implications By clarifying key activities facilitating a long-term perspective in the design process and highlighting challenges and tactics for improvement, the findings are particularly relevant to production engineers and plant managers interested in increasing the ability to adapt to future changes through reconfigurability and improve the efficiency of their production system design process. Originality/value Although reconfigurable production systems are critical for the success of manufacturing companies, the process of designing such systems is not clear. This paper stretches this by giving a comprehensive picture of the production system design process and the activities that need to be considered to meet these challenges.

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Unver, H. Ozgur. "System Architectures Enabling Reconfigurable Laboratory-Automation Systems." IEEE Transactions on Systems, Man, and Cybernetics, Part C (Applications and Reviews) 41, no. 6 (November 2011): 909–22. http://dx.doi.org/10.1109/tsmcc.2011.2107552.

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Journal articles on the topic 'Reconfigurable computer systems'

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