Dissertations / Theses on the topic 'Project Templates'

Thesis (M.S.)--West Virginia University, 1999.
Title from document title page. Document formatted into pages; contains viii, 107 p. : ill. (some col.) Vita. Includes abstract. Includes bibliographical references (p. 79-80).

The internet is a major communication channel for universities. It makes sense to insure that a Web presence of a university is representative of the university's brand and is consistent throughout all Web sites within the university. This project researches and develops Web design tools that can provice standarized resources to Web designers, specifically for California State University, San Bernardino (CSUSB).

Thesis (Ph. D.)--West Virginia University, 2000.
Title from document title page. Document formatted into pages; contains xii, 210 p. : ill. (some col.). Vita. Includes abstract. Includes bibliographical references (p. 205-209).

Thesis (M.S.)--West Virginia University, 2000.
Title from document title page. Document formatted into pages; contains viii, 47 p. Vita. Includes abstract. Includes bibliographical references (p. 35-36).

Thesis (Ed. D.)--West Virginia University, 1999.
Title from document title page. Document formatted into pages; contains iv, 152 p. Vita. Includes abstract. Includes bibliographical references (p. 140-147).

Programinės įrangos kūrimo projektų dokumentacijos kūrimas dažnai vykdomas neefektyviai – dokumentai kuriami lėtai, esama dokumentavimo metodika būna perteklinė, nėra vieningos dokumentacijos kūrimo strategijos. Vienas iš būdų paspartinti dokumentų ruošimo procesą – panaudoti šiame darbe suformuluotus nurodymus bei principus. Taikant sukurtus dokumentų šablonus, dokumentaciją galima generuoti tiesiai iš projektavimo įrankio. Šiuose šablonuose realizuotas papildomas funkcionalumas – projekto kūrimo ir testavimo darbų apimčių skaičiavimas bei elementų ryšių vientisumo nustatymas, o tai svarbu vertinant projekto kokybę ir planuojant kūrimo darbus. Sukūrus projektą, dokumentacija automatiškai sugeneruojama panaudojant projektavimo įrankio, pavyzdžiui, MagicDraw UML, teikiamas dokumentų generavimo priemones, todėl nereikia atskirai kurti dokumentacijos teksto redagavimo priemonėmis. Sukurtąjį dokumento šabloną galima pakartotinai panaudoti kituose projektuose.
Creation of documentation usually is inefficient - documents are being created slowly, the methodology of documentation is usually redundant, there is no common strategy for this. The paper proposes a way to boost the process of creating documentation by using documentation templates that give an opportunity to generate documentation directly from a CASE tool. The created template implements additional functionality - the estimation of a size of programming and testing tasks of a project and tracing the dependencies between project's elements. The implemented template of a document may be applied in more than one project.

The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.

Thesis (M.A.)--West Virginia University, 1999.
Title from document title page. Document formatted into pages; contains ix, 133 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 88-94).

Made available in DSpace on 2016-05-04T12:04:25Z (GMT). No. of bitstreams: 1 000478386-Texto+Completo-0.pdf: 12630678 bytes, checksum: 24f95d03626ea6a376f29220bb4e1177 (MD5) Previous issue date: 2016
For decades now, the synchronous paradigm has been the major choice of the industry for building integrated circuits. Unfortunately, with the development of semiconductor industry, power budgets got tighter and delay uncertainties increased, making synchronous design a complex task. Some of the reasons behind that are the increase in process variability, the losses in wire performance and the uncertainties in the operating condition of devices. These and other factors significantly impact transistor electrical characteristics, making it more complicated to meet timing closure in synchronous systems and compromising power efficiency. The asynchronous paradigm emerges as an efficient alternative to current design approaches, given its inherent high robustness against delay variations and suitability to low-power and high-performance design. However, while a major segment of the design automation industry was developed to support synchronous design, currently, design automation for asynchronous circuits is limited, to say the least. Furthermore, basic components for semi-custom design approaches, typically available in standard cell libraries were optimized to target synchronous implementations and those necessary to support asynchronous design were also left behind. This Thesis proposes new techniques to optimize asynchronous design, from cell to system level. We start by analyzing and optimizing basic components for asynchronous design and then propose new manners of implementing them at the transistor level. The proposed optimizations and novel components allow better exploring power, delay and area trade-offs, providing a guideline for asynchronous designers. We then explore how to design these components as cells for building a library to support semi-custom design. To that extent, we propose a completely automated flow for designing such libraries.This flow comprises transistors sizing and electrical characterization tools, developed in this Thesis, and a layout generation tool, developed by a fellow research group. We also provide a freely available library, designed with the flow, with hundreds of components that were extensively validated with post-layout simulations. Using this library we devised new templates for designing asynchronous circuits at the system level, exploring an automated synthesis solution and expanding design space exploration. Compared to a similar state-of-the-art solution, our latest template provides almost twice better energy efficiency and comprises an original automated method for technology mapping and synthesis optimizations. The contributions of this Thesis allowed the construction of an infrastructure for building asynchronous designs, paving the way to explore their usage to solve contemporary and future challenges in integrated circuit design.
O paradigma síncrono foi, por décadas, a principal escolha da indústria para o projeto de circuitos integrados. Infelizmente, com o desenvolvimento da indústria de semicondutores, restrições de projeto relativas à potência de um circuito e incertezas de atrasos aumentaram, dificultando o projeto síncrono. Alguns dos motivos para isso são o aumento na variabilidade dos processos de fabricação de dispositivo, as perdas de desempenho relativas em fios e as incertezas temporais causadas por variabilidades nas condições operacionais de dispositivos. Dessa forma, o paradigma assíncrono surge como uma alternativa, devido à sua robustez contra variações temporais e suporte ao projeto de circuitos de alto desepenho e baixo consumo. Entretanto, grande parte da indústria de ferramentas de automação de projeto eletrônico foi desenvolvida visando o projeto de circuitos síncronos e atualmente o suporte a circuitos assíncronos é consideravelmente limitado. Esta Tese propõe novas técnicas de projeto para otimizar circuitos assíncronos, desde o nível de células ao nível de sistema. Começamos analisando e otimizando componentes básicos para o projeto desses circuitos e depois apresentamos novas soluções para implementá-los no nível de transistores. As otimizações propostas permitem uma melhor exploração dos parâmetros desses circuitos, incluindo potência, atraso e área. Em um segundo momento, exploramos o uso desses componentes como células para a geração de uma biblioteca de suporte ao projeto semi-dedicado de circuitos assíncronos.Nesse contexto, propomos um fluxo completamente automatizado para projetar tais bibliotecas. O fluxo compreende ferramentas de dimensionamento de transistores e caracterização elétrica, desenvolvidas nesta Tese, e uma ferramenta de projeto de leiaute, desenvolvida por um grupo de pesquisa parceiro. Esse trabalho também apresenta uma biblioteca aberta, com centenas de componentes validados extensivamente através de simulações pós-leiaute. Além disso, usando essa biblioteca desenvolvemos novos templates para o projeto de circuitos assíncronos no nível de sistema, propondo um fluxo automático para síntese e mapeamento tecnológico. Comparado a uma solução assíncrona no estado da arte, nosso mais novo template apresenta uma eficiência energética quase duas vezes maior. As contribuições desta Tese permitiram a construção de uma infraestrutura para o projeto de circuitos assíncronos, abrindo caminho para a exploração do uso de templates assíncronos para solucionar problemas modernos e futuros no projeto de circuitos integrados.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-06-15T14:23:09Z No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5)
Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-26T12:27:11Z (GMT) No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5)
Made available in DSpace on 2018-06-26T12:45:06Z (GMT). No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) Previous issue date: 2018-03-21
Atualmente, a abordagem s?ncrona ? a mais utilizada em projeto de circuitos integrados por ser altamente automatizado pelas ferramentas comerciais e por incorporar margens de tempo para garantir o funcionamento correto nos piores cen?rios de varia??es de processo e ambiente, limitando otimiza??es no per?odo do rel?gio e aumentando o consumo de pot?ncia. Por um lado, circuitos ass?ncronos apresentam algumas vantagens em potencial quando comparados com os circuitos s?ncronos, como menor consumo de pot?ncia e maior vaz?o de dados, mas tamb?m podem sofrer com varia??es de processo e ambiente. Por outro lado, circuitos resilientes s?o uma alternativa para manter o circuito funcionando na presen?a de efeitos de varia??o. Sendo assim, foi proposto o circuito Blade que combina as vantagens de circuitos ass?ncronos com circuitos resilientes. Blade utiliza latches em sua implementa??o e mant?m seu desempenho em cen?rios de caso m?dio. Independentemente do estilo de projeto (s?ncrono ou ass?ncrono), durante o processo de fabrica??o de circuitos integrados, algumas imperfei??es podem acontecer, causando defeitos que reduzem o rendimento de fabrica??o. Circuitos defeituosos podem apresentar um comportamento falho, gerando uma sa?da diferente da esperada, devendo ser identificados antes de sua comercializa??o. Metodologias de teste podem ajudar na identifica??o e diagn?stico desse comportamento falho. Projeto visando testabilidade (do ingl?s, Design for Testability - DfT) aumenta a testabilidade do circuito adicionando um grau de controlabilidade e observabilidade atrav?s de diferentes t?cnicas. Scan ? uma t?cnica de DfT que fornece para um equipamento de teste externo acesso aos elementos de mem?ria internos do circuito, permitindo inser??o de padr?es de teste e compara??o da resposta. O objetivo deste trabalho ? propor uma abordagem de DfT estrutural, completamente autom?tica e integrada com as ferramentas comerciais de projeto de circuitos, incluindo uma s?rie de m?todos para lidar com os desafios relacionados ao teste de circuitos ass?ncronos e resilientes, com foco no Blade. O fluxo de DfT proposto ? avaliado usando um m?dulo criptogr?fico e um microprocessador. Os resultados obtidos para o m?dulo criptogr?fico mostram uma cobertura de falha de 98,17% para falhas do tipo stuck-at e 89,37% para falhas do tipo path-delay, com um acr?scimo de ?rea de 112,16%. Os resultados obtidos para o microprocessador mostram uma cobertura de 96,04% para falhas do tipo stuck-at e 99,00% para falhas do tipo path-delay, com um acr?scimo de ?rea de 50,57%.
Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worstcase scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.

This thesis offers means for simplifying project control in small and middle-sized businesses using a set of process-control documents and procedures. The set consists of several document templates to be mostly used in businesses not employing any specialized personnel. The set covers all the necessary tasks in preparation, implementation and evaluation of a project, thus avoiding any omission in fundamental essentials and leading to a successful and efficient project control.

Thesis (Ed. D.)--West Virginia University, 2001.
Title from document title page. Document formatted into pages; contains ix, 168 p. Includes abstract. Includes bibliographical references (p. 160-168).

Test staff working in modern software consultancy companies often have to work in multiple customer projects that differ not only technically, but also regarding organisational, management and social aspects. The ease and speed with which the staff can adapt to new projects and environments is crucial for the success and profitability of the consultancy company. This paper presents the results of a study on how management in a Swedish software company can facilitate test staff relocation. Interviews with consultants in the testing department were conducted to elicit the differences between testing projects they have and are involved in and their views on the challenges of and learning needed when relocating between projects. Based on this we present an approach to better support such staff relocations in the future. The approach is based on a knowledge sharing structure and process and the introduction of specific templates to capture and document testing experience. An initial, static validation in the test consultancy show that the approach has merit and should be further evaluated.

This thesis explores leadership from an inverted or inner perspective of a leader. It draws on humanistic, psychological approaches to leadership, and develops a theory of systemic, constructivist leadership. While systemic, constructivist concepts are well known and accepted methods in therapy, counselling, coaching, and organisational consulting, in leadership there is still a gap between theory and practise. In this study systemic, constructivist ideas such as self-organization of human systems, radical constructivism, and systems theory are transferred, through an experiential learning project to leadership practise. Previous research (Steinkellner, 2005) indicated that in addition to the understanding of systemic theory and the application of systemic interventions, the specific mental attitude of a leader is required. So this thesis (1) explores the qualities of the mental attitude of a systemic, constructivist leader, (2) reflects on the transformation of the self of a leader in an experiential learning process, and (3) develops a theory of systemic, constructivist leadership. The methodology is heuristic inquiry, which involves the subjectivity of the researcher, and includes introspective procedures such as self-searching, self-dialogue, and self-discovery (Moustakas, 1990). Its focus on the inner perspective of a leader is unusual, if not unique. Various concepts from humanistic psychology including tacit knowledge (Polanyi & Sen, 2009), awareness (Perls, 1973), and focusing (Gendlin, 2003) were applied to transcend the concept of rationality both in science and in business. The main contributions of this study are: the description of a theory of systemic, constructivist leadership and; the design of appropriate training to implement this.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-05-21T13:19:36Z No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5)
Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-01T12:13:22Z (GMT) No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5)
Made available in DSpace on 2018-06-01T12:33:57Z (GMT). No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) Previous issue date: 2018-03-28
? medida que o projeto de VLSI avan?a para tecnologias ultra submicron, as margens de atraso adicionadas para compensar variabilidades de processo de fabrica??o, temperatura de opera??o e tens?o de alimenta??o, tornam-se uma parte significativa do per?odo de rel?gio em circuitos s?ncronos tradicionais. As arquiteturas resilientes a varia??es de atraso surgiram como uma solu??o promissora para aliviar essas margens de tempo projetadas para o pior caso, melhorando o desempenho do sistema e reduzindo o consumo de energia. Essas arquiteturas incorporam circuitos adicionais para detec??o e recupera??o de viola??es de atraso que podem surgir ao projetar o circuito com margens de tempo menores. Os sistemas ass?ncronos apresentam potencial para melhorar a efici?ncia energ?tica e o desempenho devido ? aus?ncia de um sinal de rel?gio global. Al?m disso, os circuitos ass?ncronos s?o conhecidos por serem robustos a varia??es de processo, tens?o e temperatura. Blade ? um modelo que incorpora as vantagens de projeto ass?ncrono e resilientes a varia??es de atraso. No entanto, o Blade ainda apresenta desafios em rela??o ? sua testabilidade, o que dificulta sua aplica??o comercial ou em larga escala. Embora o projeto visando testabilidade com Scan seja amplamente utilizado na ind?stria, os altos custos de sil?cio associados com o seu uso no Blade podem ser proibitivos. Por outro lado, os circuitos ass?ncronos podem apresentar vantagens para testes funcionais, enquanto o circuito resiliente fornece feedback cont?nuo durante o funcionamento normal do circuito, uma caracter?stica que pode ser aplicada para testes concorrentes. Nesta Tese, a testabilidade do Blade ? avaliada sob uma perspectiva diferente, onde o circuito implementado com o Blade apresenta propriedades de confiabilidade que podem ser exploradas para testes. Inicialmente, um m?todo de classifica??o de falhas que relaciona padr?es comportamentais com falhas estruturais dentro da l?gica de detec??o de erro e uma nova implementa??o orientada para teste desse m?dulo de detec??o s?o propostos. A parte de controle ? analisada para falhas internas, e um novo projeto ? proposto, onde o teste ? melhorado e o circuito pode ser otimizado pelo fluxo de projeto. Um m?todo original de medi??o de tempo das linhas de atraso tamb?m ? abordado. Finalmente, o teste de falhas de atrasos em caminhos cr?ticos do caminho de dados ? explorado como uma consequ?ncia natural de um circuito implementado com Blade, onde o monitoramento cont?nuo para detec??o de viola??es de atraso fornece a informa??o necess?ria para a detec??o concorrente de viola??es que extrapolam a capacidade de recupera??o do circuito resiliente. A integra??o de todas as contribui??es fornece uma cobertura de falha satisfat?ria para um custo de ?rea que, para os circuitos avaliados nesta Tese, pode variar de 4,24% a 6,87%, enquanto que a abordagem Scan para os mesmos circuitos apresenta custo que varia de 50,19% a 112,70% em ?rea, respectivamente. As contribui??es desta Tese demonstraram que, com algumas melhorias na arquitetura do Blade, ? poss?vel expandir sua confiabilidade para al?m de um sistema de toler?ncia a viola??es de atraso no caminho de dados, e tamb?m um avan?o para teste de falhas (inclusive falhas online) de todo o circuito, bem como melhorar seu rendimento, e lidar com quest?es de envelhecimento.
As the VLSI design moves into ultra-deep-submicron technologies, timing margins added due to variabilities in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance and/or reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise after designing the circuit with reduced time margins. Asynchronous systems, on the other hand, have a potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. Asynchronous circuits can also present advantages for functional testing, and the timing resilient characteristic provides continuous feedback during normal circuit operation, which can be applied for concurrent testing. In this Thesis, Blade?s testability is evaluated from a different perspective, where circuits implemented with Blade present reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a Blade circuit, where the continuous monitoring for detecting timing violations provide the necessary feedback for online detection of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overhead that, for the evaluated circuits in this thesis, can vary from 4.24% to 6.87%, while the scan approach for the same circuits implies an area overhead varying from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also advances for fault testing (including online faults) of the entire circuit, yield, and aging.

Cette thèse est une étude théorique sur la interface de porphyrine de cobalt avec des surfaces métalliques avec le code VASP DFT. Le cadre DFT nécessaire a été introduit dans le chapitre 1. La structure de la jBardeen, une programme ecrit en Java, pour la simulation de la STM est expliqué dans le chapitre 2 et le code source est jointe en annexe. Une étude de l'adsorption de CoTPP sur les surfaces métalliques a été entrepris dans le chapitre 3. Différents paramètres de calcul ont été évalués: Le site d'adsorption et de la géométrie à la fois la molécule et la surface ont été étudiés par rapport à la xc-fonctionnel et correction de la dispersion utilisée. Une adsorption site le plus stable est identifié. Par conséquent, ce site plus stable a été étudiée pour sa structure électronique. Calculés images STM avec le code jBardeen ont été comparés avec une experimentation de CoTPP Cu sur une surface (111) avec une couverture sous monocouche. Dans le chapitre 4, un adatome Fe a été présenté à la CoTPP sur Ag système (111). Trois sites de liaison symétrique différentes pour l'atome Fe ont été identifiés sur le macrocycle, marqué les , bi-, brd- et bru-positions. Un moment magnétique pouvait être attestée qui a été principalement situé sur l'atome Fe. Voies possibles entre les quatre, symétriquement équivalentes, sites bi- ont été étudiées avec des méthodes différentes. Simples calculs dans le vacuum et calculs de la “Nudged Elastic Band” (NEB) de l'ensemble du système a révélé une hauteur de barrière légèrement au-dessus de 0,2 eV allant de position bi à la posititon brd. Une analyse de vibration a montré que la commutation de l'atome Fe est susceptible, lorsqu'il est perturbé hors d'équilibre dans les positions brd et bru
This thesis is a theoretical study on the cobalt porphyrin - coinage metal surface interface with the DFT code VASP. The necessary DFT framework has been introduced in chapter 1. The structure of the Java program jBardeen for STM simulation is explained in chapter 2 and the source code is attached as Appendix. A study of the adsorption of CoTPP on coinage metal surfaces has been undertaken in chapter 3. Different parameters of the calculation have been evaluated: the adsorption site and the geometry of both the molecule and surface have been investigated with respect to the xc-functional and dispersion correction used. A most stable adsorption site -bridge down- is identified. Consequently, this most stable site was investigated for its electronic structure. Calculated STM images with the jBardeen code were compared with an experiment of CoTPP on a Cu(111) surface with sub monolayer coverage. In chapter 4 an Fe adatom was introduced to the CoTPP on Ag(111) system. Three symmetrically different binding sites for the Fe atom were identified on the macrocycle, labelled the bi-, brd- and bru-positions for bisector, bridge down and bridge up respectively. A magnetic moment could be evidenced which was mainly located on the Fe atom. Possible pathways between the four symmetrically equivalent bisector sites were investigated with different methods. Single point calculations in vacuum and Nudged Elastic Band (NEB) of the whole system revealed a barrier height of slightly above 0.2 eV going from bi- to the brd-position. A vibrational analysis showed that switching of the Fe atom is likely, when perturbed out of equilibrium in the brd- and bru- positions

The subject of the diploma thesis entitled Development of pedagogical staff in relation to trends in the management of secondary schools is the analysis of approaches in terms of national strategy, but also in terms of secondary schools themselves. The theoretical part presents the educational policy and educational system in the Czech Republic, the legislative concept and definition of education and a description of the control body, which is the Czech School Inspectorate. The work also contains a theoretical basis and theoretical background of the issues focused on the strategic management of human resources in general, but also in the concept of secondary education. The starting point of the research is the approach to strategic management of human resources in the field of education of teachers at secondary schools according to conceptual documents focusing on the quality of education and development of teachers in the Czech Republic and the use of funds offered by the Ministry of Education, Youth and Sports. Documents and approaches related to the strategy of educational policy for the following period had examined, as well as the set quality criteria of secondary schools and grammar schools. Based on the findings from the above strategic and conceptual documents concerning secondary schools...

碩士
世新大學
資訊傳播學研究所(含碩專班)
101
Digital signage has become part of our daily life due innovative display technology, hardware price drop and increasing demand of entertainment. However, digital signage content is always being copies of TV commercial because of longer product period and higher cost, and those contents never change. Company “A” tries to develop digital signage advertisement module to solve issues mentioned above. In this case, the digital signage template module intends to be a system to help customer to build up digital signage ads within budget and time frame. But developer faces the difficulty that the customer could not provide specific requirements and every customer has their own ideas and demand. It causes project delay and increasing cost. To explore the digital signage template development process status through an example company “A” with research method Case Study, how impact to each development stage and participator by proposing a project management improvement. To ensure that project can be carried out and close as planned, must regulate the project scope and progress control when process digital signage template development project. Through the project management to assist each project has a responsible and dedicated project manager to work out the most favorable project's decision and carried out and completed as planned. The results of this study with project team to organize and analyze the problem of past digital signage template development process and reexamined with project management and propose a better way for the future.

The ultimate goal of the i-RoCs project is to provide an e cient automatic robotic solution to clean industrial oors. The solution will integrate stateof- art computer vision algorithms for the navigation of the robot and for the monitoring of the cleaning process. Industrial oor cleaning is one of the most important tasks for the security of the personnel in a factory. In the worst case, a damaged/slippery oor can lead to the most various accidents. This is the main reason why the most advanced technologies should be involved in this area. In this thesis we pretend to give a step towards that goal. Digital cameras with the proper use and the proper algorithms can be one of the most rich sensors that can be used in the industrial environment due to the information they can capture. This information is a conversion of the real world into digital information that can be further processed. From this information, low-level computer vision algorithms can detect a lot of features from an image such as colors, lines, blobs, contours, edges, patterns, among others. In this thesis, we give an introduction of state-of-art technology to the cleaning task in a factory. For that purpose, we present a study about the implementation of cameras and digital image processing to detect dirt in industrial oors. We propose a method for automatic calibration of the camera parameters to tackle the di cult environment that can be found inside factories in terms of the light conditions. We developed algorithms for extraction of low-level characteristics to be used in the detection of dirt that obtained promising results in terms of detection results. However, they are not satisfactory in terms of performance if we consider them to be applied in real time on a mobile robot. The last step was the implementation of Deep Learning, one of the most promising technologies of the past few years used in image processing. This proposed solution is a segmentation network followed by a regression network. The segmentation will classify the several types of patterns existing on the ground and the regression will output the level of dirtiness of each area.
O objectivo final do projecto i-RoCs é fornecer uma solução robótica automática e eficiente para a limpeza de pavimentos industriais. A solução integrará algoritmos de visão por computador de última geração para a navegação do robô e para a monitorização do processo de limpeza. A limpeza de superfícies industriais é uma das tarefas mais importantes para a segurança do pessoal de uma fábrica. No pior dos casos, um piso danificado/escorregadio pode levar aos mais variados acidentes. Esta é a principal razão pela qual as tecnologias mais avançadas devem estar envolvidas nesta área. Nesta tese é dado um passo nesse sentido. As câmaras digitais com o uso adequado e os algoritmos adequados podem ser um dos sensores mais ricos que podem ser utilizados no ambiente industrial devido à informação que podem captar. Esta informação é uma conversão do mundo real em informação digital que pode ser processada posteriormente. A partir desta informação os algoritmos de baixo nível de visão por computador podem detectar muitas características tais como cores, linhas, formas, contornos, bordas, entre outros. Nesta tese, é feita uma introdução de tecnologia de ponta para a tarefa de limpeza de uma fábrica. Para tal, apresentamos um estudo sobre a implementação de câmaras e processamento digital de imagem para detetar sujidade em pavimentos industriais. É proposto um método de calibração automática dos parâmetros da câmara para enfrentar o ambiente difícil que pode ser encontrado dentro das fábricas em termos das condições de luz. Desenvolvemos algoritmos de extracção de características de baixo nível a utilizar na deteção de sujidade que obtiveram bons resultados em termos de detecção. No entanto, não são satisfatórios em termos de desempenho se considerarmos que serão aplicados num robô móvel. O último passo foi a implementação de algoritmos baseados no Deep Learning, uma das tecnologias mais promissoras dos últimos anos, utilizada no processamento de imagens. Esta solução proposta é uma rede de segmentação seguida de uma rede de regressão. A segmentação irá classificar os vários tipos de padrões existentes no terreno e a regressão irá produzir o nível de sujidade de cada área.
Mestrado em Engenharia Eletrónica e Telecomunicações

Dissertação de mestrado em Gestão de Projetos de Engenharia
A identificação e implementação das melhores práticas de gestão de projetos são fatores preponderantes e decisivos para o sucesso das empresas, independentemente da sua área de intervenção. Este destaque surgiu da necessidade das empresas responderem de forma rápida, eficiente e de modo integrado aos desafios que um ambiente em constante mutação oferece. Numa empresa pública de transportes públicos, que se encontra certificada na norma NP4457:2007, os desafios devem focar-se nas iniciativas de melhoria de gestão de projetos, tendo em consideração o seu contexto organizacional e o baixo nível de maturidade organizacional em gestão de projetos existente. Para o desenvolvimento desta proposta foi considerado: Conhecimento Organizacional; Processos, Ferramentas e Sistema de Gestão Integrado; certificação IDI. Esta proposta envolve assim o desenvolvimento de um template de Business Case que se pretende integrar no ciclo de vida de gestão de projetos com o ciclo de vida dos projetos da empresa em estudo, transversal a todas as áreas de conhecimento descritas pelo PMBoK, diversos inputs fornecidos pelo PRINCE2 e sustentado por orientações sugeridas pela revisão de literatura para uma melhor gestão dos projetos. A finalidade do trabalho de investigação focou-se em desenvolver uma solução para justificar iniciativas que levem a projetos e facilitar uma correta gestão ao longo de todo o ciclo de vida de cada projeto.
The identification and implementation of the best practices of project management are preponderant and decisive factors for the success of the companies, regardless of their area of intervention. This highlight arose from the need for companies to respond quickly, efficiently and in an integrated manner to the challenges that an ever-changing environment offers. In a public transportation company, which is certified in NP4457: 2007, the challenges should focus on project management improvement initiatives, considering their organizational context and the low level of organizational maturity in project management existing. For the development of this proposal, it was considered: Organizational Knowledge; Processes, Tools and Integrated Management System and the existing IDI certification. This proposal involves the development of a Business Case template that is intended to be integrated into the life cycle of project management with the life cycle of the projects of the company under study, transversal to all the areas of knowledge described by PMBoK, having several inputs provided by PRINCE2 and supported by guidelines suggested by the literature review for a better project management. The purpose of the research work was to develop a solution to justify initiatives that lead to projects and ensure a correct management throughout the life cycle of each project.